X28HC256 ® 256K, 32K x 8 Bit Data Sheet June 1, 2005 5 Volt, Byte Alterable EEPROM FN8108.0 DESCRIPTION FEATURES • Access time: 70ns • Simple byte and page write —Single 5V supply —No external high voltages or VPP control circuits —Self-timed —No erase before write —No complex programming algorithms —No overerase problem • Low power CMOS —Active: 60mA —Standby: 500µA • Software data protection —Protects data against system level inadvertent writes • High speed page write capability • Highly reliable Direct Write™ cell —Endurance: 1,000,000 cycles —Data retention: 100 years • Early end of write detection —DATA polling —Toggle bit polling The X28HC256 is a second generation high performance CMOS 32K x 8 EEPROM. It is fabricated with Intersil’s proprietary, textured poly floating gate technology, providing a highly reliable 5 Volt only nonvolatile memory. The X28HC256 supports a 128-byte page write operation, effectively providing a 24µs/byte write cycle, and enabling the entire memory to be typically rewritten in less than 0.8 seconds. The X28HC256 also features DATA Polling and Toggle Bit Polling, two methods of providing early end of write detection. The X28HC256 also supports the JEDEC standard Software Data Protection feature for protecting against inadvertent writes during power-up and power-down. Endurance for the X28HC256 is specified as a minimum 1,000,000 write cycles per byte and an inherent data retention of 100 years. BLOCK DIAGRAM X Buffers Latches and Decoder 256Kbit EEPROM Array A0–A14 Address Inputs Y Buffers Latches and DECODER I/O Buffers and Latches I/O0–I/O7 CE OE WE Control Logic and Timing Data Inputs/Outputs VCC VSS 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X28HC256 PIN CONFIGURATION TSOP Plastic DIP CERDIP Flat Plastic SOIC 25 A8 A5 5 24 A9 A4 6 A3 7 A2 8 21 A10 A1 9 20 CE A0 10 19 I/O7 I/O0 11 18 I/O6 X28HC256 23 A11 22 OE I/O1 12 17 I/O5 I/O2 13 16 I/O4 VSS 14 15 I/O3 A13 WE 1 32 31 30 A6 5 29 A8 A5 6 28 A9 A4 7 27 A11 A3 8 26 NC A2 9 A1 X28HC256 (Top View) 25 OE 10 24 A10 A0 11 23 CE NC 12 22 I/O7 13 21 14 15 16 17 18 19 20 I/O6 I/O0 A2 A1 A0 I/O 0 I/O 1 I/O 2 NC VSS NC I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CE A10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 X28HC256 A3 A4 A5 A6 A7 A 12 A 14 NC VCC NC WE A13 A8 A9 A 11 OE PGA I/O5 4 2 I/O4 A6 NC A13 3 I/O3 26 A14 3 4 NC A7 A12 WE VSS VCC 27 A7 28 2 I/O2 1 A12 I/O1 A14 VCC LCC PLCC I/O1 12 I/O 2 13 I/O3 15 I/O5 17 I/O 6 18 I/O0 11 A0 10 VSS 14 I/O4 16 I/O 7 19 A1 9 A3 7 5 4 A 10 21 CE A2 20 8 X28HC256 A4 OE 6 22 A5 A12 2 A6 A7 3 VCC 28 1 A14 A11 23 A9 24 A8 25 WE 27 A13 26 (Bottom View) PIN DESCRIPTIONS Write Enable (WE) Addresses (A0-A14) The Write Enable input controls the writing of data to the X28HC256. The Address inputs select an 8-bit memory location during a read or write operation. PIN NAMES Symbol Description A0-A14 Address Inputs I/O0-I/O7 Data Input/Output WE Write Enable Output Enable (OE) CE Chip Enable The Output Enable input controls the data output buffers, and is used to initiate read operations. OE Output Enable VCC +5V VSS Ground NC No Connect Chip Enable (CE) The Chip Enable input must be LOW to enable all read/write operations. When CE is HIGH, power consumption is reduced. Data In/Data Out (I/O0-I/O7) Data is written to or read from the X28HC256 through the I/O pins. 2 FN8108.0 June 1, 2005 X28HC256 Write Operation Status Bits DEVICE OPERATION Read Read operations are initiated by both OE and CE LOW. The read operation is terminated by either CE or OE returning HIGH. This two line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH. The X28HC256 provides the user two write operation status bits. These can be used to optimize a system write cycle time. The status bits are mapped onto the I/O bus as shown in Figure 1. Figure 1. Status Bit Assignment I/O Write Write operations are initiated when both CE and WE are LOW and OE is HIGH. The X28HC256 supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 3ms. Page Write Operation The page write feature of the X28HC256 allows the entire memory to be written in typically 0.8 seconds. Page write allows up to one hundred twenty-eight bytes of data to be consecutively written to the X28HC256, prior to the commencement of the internal programming cycle. The host can fetch data from another device within the system during a page write operation (change the source address), but the page address (A7 through A14) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address. The page write mode can be initiated during any write operation. Following the initial byte write cycle, the host can write an additional one to one hundred twenty-seven bytes in the same manner as the first byte was written. Each successive byte load cycle, started by the WE HIGH to LOW transition, must begin within 100µs of the falling edge of the preceding WE. If a subsequent WE HIGH to LOW transition is not detected within 100µs, the internal automatic programming cycle will commence. There is no page write window limitation. Effectively the page write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 100µs. 3 DP TB 5 4 3 2 1 0 Reserved Toggle Bit DATA Polling DATA Polling (I/O7) The X28HC256 features DATA Polling as a method to indicate to the host system that the byte write or page write cycle has completed. DATA Polling allows a simple bit test operation to determine the status of the X28HC256. This eliminates additional interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on I/O7 (i.e., write data = 0xxx xxxx, read data = 1xxx xxxx). Once the programming cycle is complete, I/O7 will reflect true data. Toggle Bit (I/O6) The X28HC256 also provides another method for determining when the internal write cycle is complete. During the internal programming cycle I/O6 will toggle from HIGH to LOW and LOW to HIGH on subsequent attempts to read the device. When the internal cycle is complete the toggling will cease, and the device will be accessible for additional read and write operations. FN8108.0 June 1, 2005 X28HC256 DATA POLLING I/O7 Figure 2. DATA Polling Bus Sequence WE Last Write CE OE VIH VOH HIGH Z I/O7 VOL A0–A14 An An An Figure 3. DATA Polling Software Flow Write Data X28HC256 Ready An An An An DATA Polling can effectively halve the time for writing to the X28HC256. The timing diagram in Figure 2 illustrates the sequence of events on the bus. The software flow diagram in Figure 3 illustrates one method of implementing the routine. No Writes Complete? Yes Save Last Data and Address Read Last Address IO7 Compare? No Yes X28HC256 Ready 4 FN8108.0 June 1, 2005 X28HC256 THE TOGGLE BIT I/O6 Figure 4. Toggle Bit Bus Sequence Last WE Write CE OE VOH I/O6 HIGH Z * VOL * X28C512/513 Ready * I/O6 Beginning and ending state of I/O6 will vary. Figure 5. Toggle Bit Software Flow HARDWARE DATA PROTECTION ¬ The X28HC256 provides two hardware features that protect nonvolatile data from inadvertent writes. Last Write – Default VCC Sense—All write functions are inhibited when VCC is 3.5V typically. Yes – Write Inhibit—Holding either OE LOW, WE HIGH, or CE HIGH will prevent an inadvertent write cycle during power-up and power-down, maintaining data integrity. Load Accum From Addr n SOFTWARE DATA PROTECTION Compare Accum with Addr n No Compare ok? Yes X28C256 Ready The Toggle Bit can eliminate the chore of saving and fetching the last address and data in order to implement DATA Polling. This can be especially helpful in an array comprised of multiple X28HC256 memories that is frequently updated. The timing diagram in Figure 4 illustrates the sequence of events on the bus. The software flow diagram in Figure 5 illustrates a method for polling the Toggle Bit. 5 The X28HC256 offers a software-controlled data protection feature. The X28HC256 is shipped from Intersil with the software data protection NOT ENABLED; that is, the device will be in the standard operating mode. In this mode data should be protected during powerup/down operations through the use of external circuits. The host would then have open read and write access of the device once VCC was stable. The X28HC256 can be automatically protected during power-up and power-down (without the need for external circuits) by employing the software data protection feature. The internal software data protection circuit is enabled after the first write operation, utilizing the software algorithm. This circuit is nonvolatile, and will remain set for the life of the device unless the reset command is issued. Once the software protection is enabled, the X28HC256 is also protected from inadvertent and accidental writes in the powered-up state. That is, the software algorithm must be issued prior to writing additional data to the device. FN8108.0 June 1, 2005 X28HC256 SOFTWARE ALGORITHM Selecting the software data protection mode requires the host system to precede data write operations by a series of three write operations to three specific addresses. Refer to Figure 6 and 7 for the sequence. The three-byte sequence opens the page write window, enabling the host to write from one to one hundred twenty-eight bytes of data. Once the page load cycle has been completed, the device will automatically be returned to the data protected state. SOFTWARE DATA PROTECTION Figure 6. Timing Sequence—Byte or Page Write VCC (VCC) 0V Data Address AAA 5555 55 2AAA A0 5555 Writes ok tWC Write Protected CE ≤ tBLC MAX WE Figure 7. Write Sequence for Software Data Protection Write Data AA to Address 5555 Write Data 55 to Address 2AAA Byte or Age Regardless of whether the device has previously been protected or not, once the software data protection algorithm is used and data has been written, the X28HC256 will automatically disable further writes unless another command is issued to cancel it. If no further commands are issued the X28HC256 will be write protected during power-down and after any subsequent power-up. Note: Once initiated, the sequence of write operations should not be interrupted. Write Data A0 to Address 5555 Byte/Page Load Enabled Write Data XX to Any Address Optional Byte/Page Load Operation Write Last Byte to Last Address After tWC Re-Enters Data Protected State 6 FN8108.0 June 1, 2005 X28HC256 RESETTING SOFTWARE DATA PROTECTION Figure 8. Reset Software Data Protection Timing Sequence VCC Data Address AAA 5555 55 2AAA 80 5555 AA 5555 55 2AAA 20 5555 tWC Standard Operating Mode CE WE Figure 9. Write Sequence for resetting Software Data Protection Write Data AA to Address 5555 Write Data 55 to Address 2AAA Write Data 80 to Address 5555 Write Data AA to Address 5555 Write Data 55 to Address 2AAA Write Data 20 to Address 5555 After tWC, Re-Enters Unprotected State In the event the user wants to deactivate the software data protection feature for testing or reprogramming in an EEPROM programmer, the following six step algorithm will reset the internal protection circuit. After tWC, the X28HC256 will be in standard operating mode. 7 Note: Once initiated, the sequence of write operations should not be interrupted. SYSTEM CONSIDERATIONS Because the X28HC256 is frequently used in large memory arrays, it is provided with a two line control architecture for both read and write operations. Proper usage can provide the lowest possible power dissipation, and eliminate the possibility of contention where multiple I/O pins share the same bus. To gain the most benefit, it is recommended that CE be decoded from the address bus and be used as the primary device selection input. Both OE and WE would then be common among all devices in the array. For a read operation, this assures that all deselected devices are in their standby mode, and that only the selected device(s) is/are outputting data on the bus. Because the X28HC256 has two power modes, standby and active, proper decoupling of the memory array is of prime concern. Enabling CE will cause transient current spikes. The magnitude of these spikes is dependent on the output capacitive loading of the l/Os. Therefore, the larger the array sharing a common bus, the larger the transient spikes. The voltage peaks associated with the current transients can be suppressed by the proper selection and placement of decoupling capacitors. As a minimum, it is recommended that a 0.1µF high frequency ceramic capacitor be used between VCC and VSS at each device. Depending on the size of the array, the value of the capacitor may have to be larger. In addition, it is recommended that a 4.7µF electrolytic bulk capacitor be placed between VCC and VSS for each eight devices employed in the array. This bulk capacitor is employed to overcome the voltage droop caused by the inductive effects of the PC board traces. FN8108.0 June 1, 2005 X28HC256 ABSOLUTE MAXIMUM RATINGS COMMENT Temperature under bias X28HC256 ....................................... -10°C to +85°C X28HC256I, X28HC256M .............. -65°C to +135°C Storage temperature ......................... -65°C to +150°C Voltage on any pin with respect to VSS ........................................ -1V to +7V D.C. output current ............................................. 10mA Lead temperature (soldering, 10 seconds) ........ 300°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those indicated in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Supply Voltage Limits Commercial 0°C +70°C X28HC256 5V ±10% Industrial -40°C +85°C Military -55°C +125°C D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.) Limits Typ.(7) Max. Unit Test Conditions VCC active current (TTL Inputs) 30 60 mA CE = OE = VIL, WE = VIH, All I/O’s = open, address inputs = .4V/2.4V levels @ f = 10MHz ISB1 VCC standby current (TTL Inputs) 1 2 mA CE = VIH, OE = VIL, All I/O’s = open, other inputs = VIH ISB2 VCC standby current (CMOS Inputs) 200 500 µA CE = VCC - 0.3V, OE = GND, All I/Os = open, other inputs = VCC - 0.3V ILI Input leakage current 10 µA VIN = VSS to VCC ILO Output leakage current 10 µA VOUT = VSS to VCC, CE = VIH Symbol Parameter ICC VlL(2) VIH(2) Min. Input LOW voltage -1 0.8 V Input HIGH voltage 2 VCC + 1 V 0.4 V IOL = 6mA V IOH = -4mA VOL Output LOW voltage VOH Output HIGH voltage 2.4 Notes: (1) Typical values are for TA = 25°C and nominal supply voltage. (2) VIL min. and VIH max. are for reference only and are not tested. POWER-UP TIMING Symbol tPUR Parameter Max. Unit (3) Power-up to read 100 µs (3) Power-up to write 5 ms tPUW Note: (3) This parameter is periodically sampled and not 100% tested. 8 FN8108.0 June 1, 2005 X28HC256 CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V Symbol Test Max. Unit Conditions (9) Input/output capacitance 10 pF VI/O = 0V (9) Input capacitance 6 pF VIN = 0V CI/O CIN ENDURANCE AND DATA RETENTION Parameter Min. Endurance 1,000,000 Cycles Data retention 100 Years A.C. CONDITIONS OF TEST Max. Unit SYMBOL TABLE Input pulse levels 0V to 3V Input rise and fall times 5ns Input and output timing levels 1.5V WAVEFORM MODE SELECTION CE OE WE Mode I/O Power L L H Read DOUT active L H L Write DIN active H X X Standby and write inhibit High Z standby X L X Write inhibit — — X X H Write inhibit — — INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance EQUIVALENT A.C. LOAD CIRCUIT 5V 1.92kΩ OUTPUT 1.37kΩ 30pF 9 FN8108.0 June 1, 2005 X28HC256 A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.) Read Cycle Limits X28HC256-70 X28HC256-90 X28HC256-12 X28HC256-15 Symbol tRC(5) tCE(5) tAA(5) (4) tOLZ tHZ (4) (4) tOHZ Min. Read cycle time tOE tLZ Parameter (4) tOH Max. 70 Min. Max. 90 Min. Max. 120 Min. Max. Unit 150 ns Chip enable access time 70 90 120 150 ns Address access time 70 90 120 150 ns Output enable access time 35 40 50 50 ns CE LOW to active output 0 0 0 0 ns OE LOW to active output 0 0 0 0 ns CE HIGH to high Z output 35 40 50 50 ns OE HIGH to high Z output 35 40 50 50 ns Output hold from address change 0 0 0 0 ns Read Cycle tRC Address tCE CE tOE OE VIH WE tOLZ tOHZ tLZ Data I/O HIGH Z tOH tHZ Data Valid Data Valid tAA Notes: (4) tLZ min., tHZ, tOLZ min. and tOHZ are periodically sampled and not 100% tested, tHZ and tOHZ are measured with CL = 5pF, from the point when CE, OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven. (5) For faster 256K products, refer to X28VC256 product line. 10 FN8108.0 June 1, 2005 X28HC256 Write Cycle Limits Symbol tWC (7) Parameter Min. Write cycle time Typ.(6) Max. Unit 3 5 ms tAS Address setup time 0 ns tAH Address hold time 50 ns tCS Write setup time 0 ns tCH Write hold time 0 ns tCW CE pulse width 50 ns tOES OE HIGH setup time 0 ns tOEH OE HIGH hold time 0 ns tWP WE pulse width 50 ns WE HIGH recovery (page write only) 50 ns tWPH(8) tDV Data valid tDS Data setup 50 ns tDH Data hold 0 ns Delay to next write after polling is true 10 µs tDW (8) tBLC 1 Byte load cycle 0.15 100 µs µs Notes: (6) Typical values are for TA = 25°C and nominal supply voltage. (7) tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to automatically complete the internal write operation. (8) tWPH and tDW are periodically sampled and not 100% tested. WE Controlled Write Cycle tWC Address tAS tAH tCS tCH CE OE tOES tOEH tWP WE Data In Data Valid tDS tDH HIGH Z Data Out 11 FN8108.0 June 1, 2005 X28HC256 CE Controlled Write Cycle tWC Address tAS tAH tCW CE tOES OE tOEH tCS tCH WE Data Valid Data In tDS tDH HIGH Z Data Out Page Write Cycle OE(9) CE tBLC tWP WE tWPH Address(10) Last Byte I/O Byte 0 Byte 1 Byte 2 Byte n Byte n+1 Byte n+2 tWC *For each successive write within the page write operation, A7–A15 should be the same or writes to an unknown address could occur. Notes: (9) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation. (10)The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the CE or WE controlled write cycle timing. 12 FN8108.0 June 1, 2005 X28HC256 DATA Polling Timing Diagram(11) Address An An An CE WE tOEH tOES OE tDW I/O7 DIN = X DOUT = X DOUT = X tWC Toggle Bit Timing Diagram(11) CE WE tOES tOEH OE tDW I/O6 HIGH Z * * tWC * I/O6 beginning and ending state will vary, depending upon actual tWC. Note: (11)Polling operations are by definition read cycles and are therefore subject to read cycle timings. 13 FN8108.0 June 1, 2005 X28HC256 Ordering Information X28HC256 X X -X Access Time -70 = 70ns -90 = 90ns -12 = 120ns -15 = 150ns Device Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = -40°C to +85°C M = Military = -55°C to +125°C MB = MIL-STD-883 Package P = 28-Lead Plastic DIP D = 28-Lead CERDIP J = 32-Lead PLCC S = 28-Lead plastic SOIC E = 32-Pad LCC K = 28-Pin grid array F = 28-Lead flat pack T = 32-Lead TSOP All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 14 FN8108.0 June 1, 2005