PI6LC48P0201 2-Output LVPECL Networking Clock Generator Features Description ÎÎTwo differential LVPECL output pairs The PI6LC48P0201 is a 2-output LVPECL synthesizer optimized to generate Ethernet reference clock frequencies and is a member of Pericom’s HiFlex family of high performance clock solutions. Using a 25MHz crystal, the most popular Ethernet frequencies can be generated based on the settings of 2 frequency select pins. ÎÎSelectable crystal oscillator interface or LVCMOS/LVTTL single-ended clock input ÎÎSupports the following output frequencies: 62.5MHz, 125MHz, 156.25MHz ÎÎRMS phase jitter @ 156.25MHz, using a 25MHz crystal The PI6LC48P0201 uses Pericom’s proprietary low phase noise PLL technology to achieve ultra low phase jitter, so it is ideal for Ethernet interface in all kind of systems. (1.875MHz – 20MHz): 0.14ps (typical) ÎÎRMS phase jitter @ 156.25MHz, using a 25MHz crystal (12kHz – 20MHz): 0.3ps (typical) ÎÎFull 3.3V or 2.5V supply modes ÎÎIndustrial operating temperature ÎÎAvailable in lead-free package: 20-TSSOP Applications ÎÎNetworking systems Block Diagram XTAL_IN XTAL_OUT OSC PFD VCO CLK0 /N CLK0# Ref_IN IN_SEL CLK1 M CLK1# PLL_ByPass N_SEL[0:1] M_reset 15-0107 1 www.pericom.com PI6LC48P0201 Rev. D 08/05/15 PI6LC48P0201 2-Output LVPECL Networking Clock Generator Pin Configuration - TSSOP NC 1 20 VDDO VDDO 2 19 CLK1 CLK0 3 18 CLK1# CLK0# 4 17 GND M_reset 5 16 VDD PLL_ByPass 6 15 IN_SEL NC 7 14 Ref_IN VDDA 8 13 XTAL_IN N_SEL0 9 12 XTAL_OUT VDD 10 11 N_SEL1 Pinout Table - TSSOP Pin No. Pin Name 1, 7 NC 2, 20 VDDO Power - Output Power Supply 3,4 CLK0, CLK0# Output - LVPECL Output clock 0 5 M_reset Input Pull-down Master reset. “1”, CLK0/CLK1 go to “low”, CLK0#/CLK1# go to “high”; “0” outputs are enabled 6 PLL_ByPass Input Pull-down PLL bypass select. “0” PLL is enabled, “1” PLL is bypassed 8 VDDA Power - 9, 11 N_SEL0, N_SEL1 Input Pull-down Output frequency select 10, 16 VDD Power - Core Power Supply 12, 13 XTAL_OUT, XTAL_IN Crystal - Crystal input and output 14 Ref_IN Input Pull-down CMOS reference clock input 15 IN_SEL Input Pull-down “0” selects Crystal, “1” selects reference input 17 GND Ground - Ground Output - LVPECL Output clock 1 18, 19 CLK1#, CLK1 15-0107 I/O Type Description No connection Analog Power Supply 2 www.pericom.com PI6LC48P0201 Rev. D 08/05/15 PI6LC48P0201 2-Output LVPECL Networking Clock Generator Output Frequency Selection Table Xtal Frequency (MHz) N_SEL1 N_SEL0 Output Frequency (MHz) 00 156.25 01 125 10 62.5 11 125 25 Typical Crystal Requirement Parameter Minimum Maximum Units 27.2 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF Drive Level 1 mW Mode of Oscillation Frequency Typical Fundamental 22.4 25 Recommended Crystal Specification Pericom recommends: a) FL2500047, SMD 3.2x2.5(4P), 25MHz, CL=18pF, +/-20ppm, http://www.pericom.com/pdf/datasheets/se/FL.pdf b) FY2500091, SMD 5x3.2(4P), 25MHz, CL=18pF, +/-30ppm, http://www.pericom.com/pdf/datasheets/se/FY_F9.pdf 15-0107 3 www.pericom.com PI6LC48P0201 Rev. D 08/05/15 PI6LC48P0201 2-Output LVPECL Networking Clock Generator Maximum Ratings (Over operating free-air temperature range) Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Storage Temperature............................................... -65ºC to+155ºC Ambient Temperature with Power Applied..........-40ºC to+85ºC 3.3V Supply Voltage.....................................................-0.5 to +3.7V ESD Protection (HBM).......................................................... 2000V DC Electrical Characteristics Power Supply DC Characterisitcs, (TA = -40ºC to 85ºC) Symbol Parameter VDD, VDDA, VDDO Condition Min Typ Max Units Supply Voltage 2.97 3.3 3.63 V VDD, VDDA, VDDO Supply Voltage 2.375 2.5 2.625 V IGND Power Supply Current 110 mA IDDA Analog Supply Current 26 mA Max Units LVCMOS/LVTTL DC Characterisitcs, (TA = -40ºC to 85ºC) Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current M_reset, PLL_ByPass, N_SEL[0:1], IN_SEL, Ref_IN VDD = VIN = 3.63V Input Low Current M_reset, PLL_ByPass, N_SEL[0:1], IN_SEL, Ref_IN VDD = 3.63V, VIN = 0V -5 Condition Min IIL Condition Min Typ VDD = 3.3 V +/- 10% 2 VDD+ 0.3 V VDD = 2.5 V +/- 5% 1.7 VDD+ 0.3 V VDD = 3.3 V +/- 10% -0.3 0.8 V VDD = 2.5 V +/- 5% -0.3 0.7 V 150 µA µA Pin Characterisitcs Symbol Parameter CIN Input Capacitance 4 pF R PULLDOWNN Pull down resistor 51 kΩ 15-0107 4 www.pericom.com Typ PI6LC48P0201 Max Rev. D Units 08/05/15 PI6LC48P0201 2-Output LVPECL Networking Clock Generator LVPECL DC Characterisitcs, (TA = -40ºC to 85ºC) Symbol Parameter VOH Output High Voltage(1) VOL Output Low Voltage(1) Condition Min Typ Max VDD = 3.3V 1.9 2.4 VDD = 2.5V 1.1 1.6 VDD = 3.3V 1.2 1.6 VDD = 2.5V 0.4 0.8 Units V V Note: 1. LVPECL Termination: Source 150ohm to GND and 100ohm across CLK and CLK#. AC Electrical Characteristics, (TA = -40ºC to 85ºC) LVPECL Termination: Source 150ohm to GND and using 0.01uF ac-coupled to 50ohm to GND Symbol Parameter Output Frequency fOUT Output Skew(1, 3) tsk(o) Condition Min. N_SEL[1:0] = 00 Typ. Max Units 140 170 MHz N_SEL[1:0] = 01, 11 112 136 MHz N_SEL[1:0] = 10 56 68 MHz 70 ps Outputs with the same loading 156.25MHz, (1.875MHz - 20MHz) 0.14 ps 0.3 ps 0.13 ps 0.28 ps 0.25 ps 0.36 ps 156.25MHz, (12kHz - 20MHz) 125MHz, RMS Phase Jitter, (Random)(2) t jit(Ø) (1.875MHz - 20MHz) 125MHz, (12kHz - 20MHz) 62.5MHz, (1.875MHz - 20MHz) 62.5MHz, (12kHz - 20MHz) tR / tF Output Rise/Fall Time odc Output Duty Cycle 20% to 80% 48 400 ps 52 % Note: 1. Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points. 2. Please refer to the Phase Noise Plots. 3. This parameter is defined in accordance with JEDEC Standard 65. 15-0107 5 www.pericom.com PI6LC48P0201 Rev. D 08/05/15 PI6LC48P0201 2-Output LVPECL Networking Clock Generator Phase Noise Plots fOUT = 156.25MHz fOUT = 125MHz fOUT = 62.5MHz 15-0107 6 www.pericom.com PI6LC48P0201 Rev. D 08/05/15 PI6LC48P0201 2-Output LVPECL Networking Clock Generator LVPECL Test Circuit ZO = 50Ω 0.01µF L = 0 ~ 10in Device ZO = 50Ω 150Ω 50Ω 0.01µF 50Ω 150Ω Power Supply Filtering Techniques As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The PI6LC48P0201 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO should be individually connected to the power supply plane through vias, and 0.1μF bypass capacitors should be used for each pin. Figure below illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10Ω resistor along with a 10μF bypass capacitor be connected to the VDDA pin. 3.3V or 2.5V VDD 0.1µF 10Ω * VDDA 0.1µF 10µF * If VDD is 2.5V, the resistor value will be different, see app note for details 15-0107 7 www.pericom.com PI6LC48P0201 Rev. D 08/05/15 PI6LC48P0201 2-Output LVPECL Networking Clock Generator Recommendations for Unused Input and Output Pins Inputs: Crystal Inputs: For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. A 1kΩ resistor can be tied from XTAL_IN to ground for additional protection. Ref_IN Input: For applications not requiring the use of the clock, it can be left floating. A 1kΩ resistor tied from the Ref_IN to ground can provide additional protection. LVCMOS Control Pins: All control pins have internal pulldowns; A 1kΩ resistor tied from each control pin to ground can provide additional protection. Outputs: LVPECL Outputs: All unused LVPECL outputs can be left floating. Crystal Input Interface The clock generator has been characterized with 18pF parallel resonant crystals. The capacitor values shown in the figure below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. XTAL_IN C1 33pF X1 18pF Parallel Crystal XTAL_OUT C2 27pF 15-0107 8 www.pericom.com PI6LC48P0201 Rev. D 08/05/15 PI6LC48P0201 2-Output LVPECL Networking Clock Generator LVCMOS to XTAL Interface The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in the figure below. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS signals, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of the two ways. First, R1 and R2 in parallel should equal the transmission line empedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. By overdriving the crystal oscillator, the device will be functional, but note, the device performance is quaranteed by using a quartz crystal. VDD VDD R1 Rs Ro 50Ω 0.1µF XTAL_IN Zo = Ro + Rs R2 XTAL_OUT Thermal Information Symbol Description QJA Junction-to-ambient thermal resistance 84.0 OC/W QJC Junction-to-case thermal resistance 17.0 OC/W 15-0107 9 www.pericom.com PI6LC48P0201 Rev. D 08/05/15 PI6LC48P0201 2-Output LVPECL Networking Clock Generator Packaging Mechanical: 20-Contact TSSOP (L) DATE: 05/03/12 Notes: 1. Refer JEDEC MO-153F/AC 2. Controlling dimensions in millimeters 3. Package outline exclusive of mold flash and metal burr DESCRIPTION: 20-pin, 173mil Wide TSSOP PACKAGE CODE: L DOCUMENT CONTROL #: PD-1311 REVISION: F 12-0373 Ordering Information Ordering Code Packaging Type Package Description Operating Temperature PI6LC48P0201LIE L Pb-free & Green, 20-pin TSSOP Industrial PI6LC48P0201LIEX L Pb-free & Green, 20-pin TSSOP, Tape & Reel Industrial Notes: • Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ • "E" denotes Pb-free and Green • Adding an "X" at the end of the ordering code denotes tape and reel packaging Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com 15-0107 10 www.pericom.com PI6LC48P0201 Rev. D 08/05/15