PLX Technology PCI Express Overview May 2007 PLX PCIe May 2007 1 Corporate Overview ¾ Public U.S. Company Founded in 1986 IPO in 1999 NASDAQ: PLXT ¾ Headquarters in Sunnyvale, CA +150 Employees Sales & Technical Support Worldwide Fabless Semiconductor Business Model ¾ Over 1000 customers worldwide PLX PCIe May 2007 2 PLX Interconnect Products ¾ PLX is a Leader in I/O Interconnect Products ¾ Our broad product line of devices can bridge popular I/O standards including PCI Express Local Bus Bridges Conceptual Conceptual Drawing, Drawing, not not every every possible possible option option available available currently currently from from PLX PLX PLX PCIe May 2007 3 PCI Express Focus = Leadership ¾ PLX started investing in PCI Express in 2001 100% of all Current Development is PCI Express ¾ Broad Offering of PCI Express Bridges & Switches ¾ Objective: Switches #1 Supplier of PCI Express Switches and Bridges in the Industry Bridges PLX PCIe May 2007 4 PCI Express in Servers Bridge CPU GE Switch GE Chip Set Memory Adapter Adapter & & Riser Riser Cards Cards Switch Stand-alone I/O Switch I/O Rackmount Blade I/O Bridge Server Server I/O Motherboard Motherboard PLX PCIe May 2007 5 PCI Express in Storage Systems CPU CPU NAS SAN Chip Set Memory Chip Set Memory Storage NT FC NT Switch Switch FC Switch I/O I/O I/O I/O SAS Bridge SAS I/O Bridge I/O Switch High Availability Storage System PLX PCIe May 2007 6 PCI Express in Peripherals & Consumer GPU GPU Bridge Graphics - Reverse Bridge TV Tuner Switch GPU Graphics – More Monitors or Higher Resolution TV Bridge Mobile PCI Express TV Tuner Printer Computer Peripheral and Consumer Electronics Graphics/ Video Wireless LAN PLX PCIe May 2007 7 PCI Express in Communications Co-ProcessorSecurity/DSP DSLAM Base Station Controller Wireless LAN Gateway Switch Enterprise Storage NPU/ASIC NT VoIP Gateway Remote Access Router/Switch Concentrator Local Processor Framer PHY Line Card 1 Communications Communications Line Card n Switch Control Processor Memory Supervisory or Controller Card PLX PCIe May 2007 8 PCI Express in Embedded Memory FPGA Printer Bridge Imaging/Graphics CPU Industrial Medical FPGA Bridge Embedded Embedded Switch FPGA Bridge Industrial Control & Instrumentation I/O I/O Host CPU Bridge PCIe ASIC Embedded Host System PLX PCIe May 2007 9 ExpressLane PCI Express Switches ¾ 5, 8, 12, 16, 24, 32, & 48 PCIe Lanes Others in Development/Planned ¾ 3 to 9 Flexible Ports x1 to x16 Port Configurations PEX 8500 Series ¾ Additional Features Lowest Latency ~110ns Non-Transparent Port for Dual Hosts True Peer-to-Peer & Fan-Out Capabilities Up to 2 Virtual Channels Low Power ¾ Available Now PLX PCIe May 2007 10 PLX PCIe Gen 1 Switch Road Map PEX 8548 48 48 Lanes Lanes st 1st Generation Vega Architecture 32 32 Lanes Lanes 24 24 Lanes Lanes 16 16 Lanes Lanes PEX 8532 PEX 8533 32 Lanes, 6 Ports, 1KB 3 HPC, 115ns Cut-Thru PEX 8524 PEX 8517 Pin Compatible Migration* * Pin compatible with some feature changes. Discuss with PLX 3rd Generation Altair Architecture Future Products: PEX 8525 Pin Compatible Migration* 24 Lanes, 6 Ports, NT 6 HPC, 2VC, Peer-Peer 16 Lanes, 4 Ports, NT 4 HPC, 2VC, Peer-Peer Planned/Concept 48 Lanes, 3 x16 Ports, for Graphics Apps Pin Compatible Migration* PEX 8516 In Development PEX 8547 32 Lanes, 8 Ports, NT 8 HPC, 2VC, Peer-Peer 24 Lanes, 5 Ports, 1KB 3 HPC, 115ns Cut-Thru More Gen 1 Gen 2 (5GTps) Specialty Switches 16 Lanes, 4 Ports, NT 4 HPC, 150ns Cut-Thru PEX 8518 16 Lanes, 5 Ports, NT 5 HPC, 150ns Cut-Thru 12 12 Lanes Lanes 88 Lanes Lanes Shipping Now 48 Lanes, 9 Ports, 1KB 3 HPC, 110ns Cut-Thru 2nd Generation Vega Lite Architecture PEX 8512 12 Lanes, 5 Ports, NT 5 HPC, 150ns Cut-Thru Additional Product Details can be shared under NDA PEX 8508 PEX 8509 8 Lanes, 5 Ports, NT 5 HPC, 150ns Cut-Thru 8 Lanes, 8 Ports, 1KB 140ns 15x15 PEX 8505 5 Lanes, 5 Ports, 1KB 3HPC, 140ns 15x15 55 Lanes Lanes 2004/2005 2006 High Port Count Small Switches 2007 PLX PCIe May 2007 11 PLX: Switch Market Leading Supplier ¾ First devices in Late 2004 Three Generations of Architecture have been introduced Constantly improving based on internal learning curve and customer input • Shipping Production…. …..while other sample/power point ¾ Broadest Switch Portfolio 13 Devices Available today • 5 to 48 Lanes • 3 to 9 Ports Many More Planned and in Development PLX PCIe May 2007 12 Optimized for Different Applications ¾ Fan-out for Servers & HBAs Cost Optimized Industry best performance & latency • 110ns Latency ¾ Peer-to-Peer for Backplanes No CPU intervention required ¾ Non-Transparency for Address Isolation Dual Host and Failover ¾ High Port Count For Control Planes needing lots of connectivity PLX PCIe May 2007 13 Port Flexibility ¾ Flexible Ports configurable as x1, x2, x4, x8, x16 • Customize to meet your design’s needs Auto-negotiation of port width supported • Will negotiate down to x8, x4, x2, or x1 ¾ Versatile Any port can be upstream Movable upstream port Cross-link capability • Dual-host support PCIe Switch 4 x2 ports 2 x4 ports 1 x8 port PLX PCIe May 2007 14 Dual-Host & Failover Options ¾ Two methods of implementing Failover Systems Non-Transparent Port Crosslink & Moveable Upstream Port Primary Host Secondary Host ¾ Crosslink & Moveable Upstream Port Utilized when user has full control of system software (OS) and enumeration process Switch ¾ Non-Transparent Port Utilized when user has no or limited control of system software (OS) and/or enumeration process PLX PCIe May 2007 15 Crosslink or Non-Transparency Intelligent I/O Adaptor I/O CPU 2 CPU 1 Non-Transparent Port CPU Memory Chip Set Chip Set Memory I/O NT Upstream Upstream End Point End Point Switch Downstream Downstream Crosslink Crosslink Primary Primary Host Host Secondary Secondary Host Host CPU Blade CPU Blade Switch End Point Switch End Point I/O I/O NT Switch I/O Crosslink is useful when user has full control of system software (OS) and enumeration process Non-Transparent Port NT is needed when user has no or limited control of system software (OS) and/or enumeration process PLX PCIe May 2007 16 PLX Switches with Hot-Plug PLX PCIe Switch Voltage Cont. Power HPPE RST PCIe hot-plug control registers PCIe Switch w/o Hot Plug Controller Clk Voltage Cont. CPLD $5 Clock Power HPPE RST No PCIe hot-plug control registers Clk Clock ¾ PLX PCIe Switches ¾ Other PCIe Switches Internal Hot-Plug Controllers Require External CPLD D $! Provide PCIe Hot-Plug Registers May not provide PCIe Hot-Plug and 9 Hot-Plug signals Registers D Software burden! Minimal External Circuitry Needed Additional External Circuitry Needed Available on 2 to 8 ports PLX PCIe May 2007 17 Cut-Thru ¾ Cut-Thru Architecture – reduced latency Moves packet to Egress port after reading packet header Increased performance with bursty traffic ¾ Store & Forward Architecture Moves packet to Egress port after reading entire packet Cut-Thru Path Ingress Port Egress Port 100101100011 0110 100101100011 0110 Payload Payload Header Header PCIe Switch Egress Port Ingress Port 1001011000110110 Payload 100101100011 0110 Header Payload Header Store & Forward Path PLX PCIe May 2007 18 True Peer-to-Peer Support Root Complex End Point Root Complex End Point Switch End Point End Point ¾ PLX PCIe Switches No host involvement • • • End Point Reduced latency Enhanced CPU Performance Optimized Peer-to-Peer Bandwidth/Performance Other PCIe Switches End Point End Point End Point ¾ Other PCIe Switches Claim Peer-to-Peer…but… May require host-support • • • Added latency Reduced CPU Performance Bandwidth/Performance impact for Peer-to-Peer traffic PLX PCIe May 2007 19 Port Arbitration ¾ Allows priority assignment to specific ports Round Robin or Weighted Round Robin schemes can be used Egress Port Switch 010101000011110101011 010101000011110101011 010101000011110101011 010101000011110101011 010101000011110101011 010101000011110101011 010101000011110101011 010101000011110101011 Packet Queue User assigns priority or weight for ports Example: Green port weight = 2 Yellow and Gray weight = 1 Port arbiter serves green port twice the rate of other ports Ingress Ports PLX PCIe May 2007 20 Device Configuration ¾ Register Configuration via: I2C – Two wire protocol defined by Philips ¾ Hardware Strapping Using Pull-up/Pull-down resistors • Out of band device configuration EEPROM – Serial Load • Configures device prior to BIOS access In Band – Memory mapped via PCIe link • In band device configuration by host Switch Upstream Link CSRs PCIe Signal Strapping I22C EEPROM Multiple Ways to Configure PLX Switches PLX PCIe May 2007 21 Non-Blocking Internal Architecture ¾ ¾ Allows traffic between ports at full line rates Flexible buffer allocation Prevents head of line blocking Switch Non-Blocking PLX PCIe May 2007 22 Spread Spectrum Clock Support ¾ SSC Systems Supports Single Clock Domain Reduces EMI Host 1 SSC Domain 1 Host 2 SSC Domain 2 ¾ Supports Two clock domains SSC Domain • Modulated clock input Constant clock domain • Constant clock input ¾ Advantages for having Two clock domains Removes requirement for single source clock • Important for Modular Systems PLX PCIe May 2007 23 Spread Spectrum Clock Support Host 1 SSC Domain 1 Host 2 SSC Domain 2 CPU CPU Constant Clock Domain (Non-SSC) Bridge Bridge I/O NT NT T Switch T I/O I/O I/O Switch I/O I/O PLX PCIe May 2007 24 Power Management ¾ Supports all required PCIe Link & Device Power Management States ¾ Additional Power Management Support WAKE# • Out of band mechanism used by endpoints to inform host of power state change Beacon • In-band mechanism used by PCIe devices to inform host of power state change VAUX • Auxiliary voltage supply for Beacon internal circuit ¾ VAUX/WAKE#/Beacon support WAKE# - Input Signal to Switch Switch generates in-band Beacon sequence to host when WAKE# is active PLX PCIe May 2007 25 VAUX/WAKE#/Beacon WAKE#/Beacon Support present in Switch WAKE#/Beacon Support not present in Switch CPU CPU Chipset Chipset WAKE# Beacon I/O I/O VAUX I/O Switch Switch I/O Switch I/O I/O WAKE# PLX PCIe May 2007 26 Reliability & Serviceability ¾ Performance Monitoring Allows users to monitor device and system performance on a per port basis: • TLP throughput & Queue depths • Blocking, stalling, over-subscription detection ¾ Internal Testability Features JTAG support BIST for internal memories Lane/Port status indicators ¾ Debug Features PRBS generator for bit error rate characterization SerDes loopback mode (four levels) Error Injection PLX PCIe May 2007 27 Additional Key Features ¾ Quality of Service Up to Two Virtual Channels ¾ Lane and polarity reversal supported on all ports ¾ Up to 32 General Purpose Output Pins ¾ FATAL_ERR# and INTA# support ¾ Error Handler PCI Express Advanced error reporting Poison-bit & end-to-end CRC ¾ Industrial Temp Support ¾ SerDes power control Off, low, typical and high • Turn off unused SerDes blocks PLX PCIe May 2007 28 PCI Express Switches Device Information Gen 1 (2.5GT/s) PLX PCIe May 2007 29 48 Lane Switch ¾ PEX 8548 Industry’s first 48 lanes and 9 ports PCIe switch Servers, ATCA Blades, Fan-out, Peer-to-Peer Communication, Graphics Feature PEX 8548 Lanes 48 Ports 9 Latency Non-Transparency Hot Plug Ports Maximum Payload Size Availability Package Typical Power 110ns (in x16 to x16 configuration) No 3 1 KB Samples Now / Production in Q1 07 37.5 x 37.5 mm2 4.9 W PLX PCIe May 2007 30 48 Lane Port Configurations PEX 8548 x8 x8 x16 x8 PEX 8548 PEX 8548 x4 x8 x8 x8 x8 x8 PEX 8548 PEX 8548 x8 x8 x8 x4 x4 x8 PEX 8548 PEX 8548 x4 x4 x16 x8 x8 x16 x8 x4 x4 x4 x4 x16 x16 x4 x4 x4 x4 x8 x8 x8 x8 x16 x16 x8 x8 x4 x8 x8 PEX 8548 PEX 8548 x4 x4 x4 x4 x4 x8 x4 ¾ Many other configurations possible ¾ Higher lane-width port will auto-negotiation down PLX PCIe May 2007 31 Storage Servers CPU Memory Chip Set x16 End Point x8 PEX 8548 x16 x8 Bridge Bridge Switch x8 or x4 ports PEX Switch 8524 x8 or x4 ports PLX PCIe May 2007 32 32 Lane Switches ¾ PEX 8532 Non-Transparent switch Redundant Systems, Dual-Host, Fail-over Systems ¾ PEX 8533 Performance optimized switch with industry’s lowest latency - 115ns Servers, Storage, Graphics, Fan-Out, Peer-to-Peer Communication Feature PEX 8532 PEX 8533 Lanes 32 32 Ports 8 6 > 200ns 115ns (in x8 to x8 configuration) Yes No 8 3 256 B 1 KB In Production Samples Now / Production in Q1 07 35 x 35 mm2 35 x 35 mm2 5.7 W 3.3 W Latency Non-Transparency Hot Plug Ports Maximum Payload Size Availability Package Typical Power PLX PCIe May 2007 33 32 Lane Port Configurations PEX 8533 PEX 8532 x4 x16 x8 x16 x4 x4 PEX 8532 PEX 8532 x4 x8 x8 x8 x8 x8 PEX 8532 x4 x4 PEX 8533 x8 x8 x4 x4x4x4 x4 x4 x4 x4 x8 x8 PEX 8533 x8 x8 x8 PEX 8532 PEX 8533 PEX 8533 x4 x4 x4 x4 x8 x8 x8 x4x4 x8 x8 ¾ Many other configurations possible ¾ Higher lane-width port will auto-negotiation down PLX PCIe May 2007 34 24 Lane Switches ¾ PEX 8524 Non-Transparent switch Redundant Systems, Dual-Host, Fail-over Systems ¾ PEX 8525 Performance optimized switch with industry’s lowest latency - 115ns Servers, Storage, Graphics, Peer-to-Peer Communication Feature PEX 8524 PEX 8525 Lanes 24 24 Ports 6 5 > 200ns 115ns (in x8 to x8 configuration) Yes No 6 3 256 B 1 KB In Production Samples Now / Production in Q1 07 31 x 31 mm2 31 x 31 mm2 3.9 W 2.6 W Latency Non-Transparency Hot Plug Ports Maximum Payload Size Availability Package Typical Power PLX PCIe May 2007 35 24 Lane Port Configurations PEX 8525 PEX 8524 x4 x8 x8 x8 x4 PEX 8524 PEX 8524 x8 PEX 8525 x8 PEX 8525 x8 x8 x4 x4x4x4 x4 x4 x4 x4 x8 x8 x4 x8 x2 PEX 8524 PEX 8524 PEX 8525 PEX 8525 x4 x4 x4 x4 x4 x4 x4 x2 x8 x4 x4 x4x4 x4 x4 ¾ Many other configurations possible ¾ Higher lane-width port will auto-negotiation down PLX PCIe May 2007 36 16 Lane Switches ¾ PEX 8518 Non-Transparent switch with SSC and Vaux/WAKE#/Beacon Redundant Systems, Fan-Out, Servers, HBAs, NICs, Mezzanine cards ¾ PEX 8517 Pin compatible migration from 1st generation 16-lane PEX 8516 switch Feature PEX 8518* PEX 8517 PEX 8516 Lanes 16 16 16 Ports 5 5 4 150ns 150ns > 200ns Yes Yes Yes 5 4 4 256 B 256 B 256 B In Production In Production In Production 23 x 23 mm2 27 x 27 mm2 27 x 27 mm2 2.6 W 2.6 W 3.2 W Latency Non-Transparency Hot Plug Ports Maximum Payload Size Availability Package Typical Power * PEX 8518 recommended for all new 16 lane designs PLX PCIe May 2007 37 16 Lane Port Configurations PEX 8518 x4 x8 PEX 8518 PEX 8518 x4 x4 x4 x4 x2 x2 x4 x8 PEX 8518 PEX 8518 x4 x4 x2 x2 x2 x2 x2 x2 ¾ Many other configurations possible ¾ Higher lane-width port will auto-negotiation down PLX PCIe May 2007 38 12 Lane Switch ¾ PEX 8512 Non-Transparent switch with SSC and Vaux/WAKE#/Beacon Fan-Out, HBAs, NICs, AMC/XMC plug-in cards, Redundant Systems, Host Isolation Feature PEX 8512 Lanes 12 Ports 5 Latency Non-Transparency Hot Plug Ports Maximum Payload Size Availability Package Typical Power 150ns Yes 3 256 B May 07 23 x23 mm2 2.2 W PLX PCIe May 2007 39 12 Lane Port Configurations PEX 8512 x4 x4 PEX 8512 x4 PEX 8512 x4 x2 x2 x4 x4 PEX 8512 x2 x2 x2 x2 ¾ Higher lane-width port will auto-negotiation down PLX PCIe May 2007 40 8 Lane Switches ¾ PEX 8508 Non-Transparent switch with SSC and Vaux/WAKE#/Beacon Redundant Systems, Host Isolation, AMC/XMC plug-in cards ¾ PEX 8509 Industry’s only 8 lanes & 8 ports PCIe switch Control Planes, Docking Stations, NICs, High-end Printers Feature PEX 8508 PEX 8509 Lanes 8 8 Ports 5 8 150ns 140ns (in x4 to x1 configuration) Yes No 5 3 256 B 1 KB In Production Q2 07 19 x 19 mm2 15 x 15 mm2 1.6 W 1.5 W Latency Non-Transparency Hot Plug Ports Maximum Payload Size Availability Package Typical Power PLX PCIe May 2007 41 8 Lane Port Configurations PEX 8509 PEX 8508 x4 x4 x4 PEX 8508 x1 x1 x1 x1 x4 PEX 8509 PEX 8508 x2 x2 x2 PEX 8509 x1 x1x1x1 x2 x1 x1x1x1 x1 x2 x2 x1 PEX 8508 PEX 8508 x2 x1 x1 x2 x2 x2 x1 PEX 8509 x1 x1 x1 x1x1x1 PEX 8509 x1 x1x1 x1 x1 ¾ Many other configurations possible ¾ Higher lane-width port will auto-negotiation down PLX PCIe May 2007 42 5 Lane Switch ¾ PEX 8505 5 lanes & 5 ports PCIe switch Control Planes, Docking Stations, I/O expansion in PCs, High-end Printers, Consumer Electronic Systems Feature PEX 8505 Lanes 5 Ports 5 Latency Non-Transparency Hot Plug Ports Maximum Payload Size Availability Package Typical Power 138ns (in x2 to x1 configuration) No 3 1 KB June 07 15 x 15 mm2 0.8 W PLX PCIe May 2007 43 5 Lane Port Configurations PEX 8505 x1 x2 PEX 8505 PEX 8505 x1 x1 x1 x1 x1 x1 x1 x1 PEX 8505 x1 x1 x1 x2 x1 PEX 8505 x2 x1 PEX 8505 x1 x1 PLX PCIe May 2007 44 Notebook Docking Station Mother Board CPU Memory North Bridge Graphics South Bridge USB/SATA/GE Low Cost and Power PCI Express aggregator • Single lane PCI Express slots/cards 4 End Point 1 Network 1 1 PEX 8509 1 Docking Station PLX PCIe May 2007 End Point 45 Control Planes For Large Systems To Line Cards 7 ports PEX 8509 6 ports PEX 8509 Control Processor Memory Controller Card ¾ Controller Processor has dual PCIe ports ¾ Now there is no bottleneck between the 2 PEX 8509 devices PLX PCIe May 2007 46 PEX Rapid Development Kits (RDK) ¾ Configurable in up to 7 PCI Express Ports One male edge connector Up to 4 on-board female connectors Breakout Boards used for further port expansion ¾ Plugs in a standard PCI Express slot ¾ Usable on bench-top while powered by an external power supply ¾ On-board clock buffer, Hot Plug controller, EEPROM, etc. ¾ RDKs available for all PLX switches! PLX PCIe May 2007 47 PLX PCIe Switch Summary ¾ Broadest Portfolio of Switches in the Industry ¾ Industry-wide Acceptance All production products on PCI-SIG Integrators List Shipping in Production ¾ Active Participation in Multiple Standards Bodies PCI-SIG, IOV, Gen 2 Specification, Geneseo ¾ Undisputed Leader in PCIe Switches PLX PCIe May 2007 48 ExpressLane PCI Express Bridges ¾ PCI to PCI Express 32-Bit PCI (66MHz) x1 PCIe PCI or PCI-X ¾ PCI-X to PCI Express 64-Bit PCI-X (133MHz) x4 PCIe PEX 8100 Series ¾ Additional Features Forward & Reverse Low Power Small Packages ¾ Available TODAY! PLX PCIe May 2007 49 Forward and Reverse Bridging Primary Primary Bridge Primary Bus Bridge Secondary Bus Secondary Secondary Forward Bridge Reverse Bridge PLX PCIe May 2007 50 Bridge Road Map - PCI, PCI-X, PCIe PCI/PCI-X Bus Speeds PCI 6540 64 Bits 133 MHz PCI-X PCI-X Non-Transparent Non-Transparent Asynchronous Asynchronous PEX 8114 PCI 6520 64-Bit 133MHz PCI-X to x4 PCIe PCI-X PCI-X Asynchronous Asynchronous 27x27 27x27 mm mm22 380 380 PBGA PBGA 64 Bits 66 MHz PCI 6254 PCI 6466 • Forward & Reverse Mode Non-Transparent Non-Transparent Asynchronous Asynchronous Non-Transparent Non-Transparent Asynchronous Asynchronous • Small 17x17mm Package • No Heat Sink Required PCI 6154 Asynchronous Asynchronous 31x31 31x31 mm mm22 304 304 PBGA PBGA PCI 6150 32 Bits 66MHz High High Performance Performance Asynchronous Asynchronous PEX 8111 PCI 6152 32-Bit 32-Bit 66MHz 66MHz PCI PCI to to x1 x1 PCIe PCIe Smallest Smallest Footprint Footprint 15x15 15x15 mm mm22 160 160 TBGA TBGA 32 Bits 33MHz PCI 6140 Lowest Lowest Power Power (200mW) (200mW) 2003 & Before Shipping Now • Forward & Reverse Mode In Development • Small 10x10 & 13x13mm Package Planned/Concept • No Heat Sink Required 2004 2005 PLX PCIe May 2007 2007 51 PEX 8111 Overview ¾ Forward or Reverse Bridging ¾ PCI Express to PCI Transparent Reversible Bridge ¾ PCI Express – 1 lane, 1 virtual channel, with integrated 2.5 GHz SerDes ¾ PCI Bus – 66 MHz, 32-Bit, CardBus Compatible ¾ 8K of shared memory accessible from both sides ¾ Four GPIO pins ¾ Packaging 13mm x 13mm 144 ball BGA package 10mm x 10mm 161 ball Fine-pitch BGA package (Smallest in Industry) ¾ In Production! PEX 8111 PCI 32-bit, 66MHz PLX PCIe May 2007 52 Example in Add-in Cards Forward Mode Reverse Mode PCIe PCI Device Endpoint PEX 8111 PEX 8111 PLX PCIe May 2007 53 Example on Motherboard PCI Slots PCI Chipset PCI Bus PCI Express Add-On Slot Host CPU Creating PCI Slots PEX 8111 PCI-to-PCI Express Bridge PCI Slots PEX 8111 Providing PCI Express Host CPU Root Complex PEX 8111 PLX PCIe May 2007 PCI Device 54 PCI Express Features ¾ Compliant with PCIe 1.0a specification Listed on PCI-SIG integrators list ¾ Maximum payload size 128 Bytes ¾ Interrupts transferred between ports ¾ Message signal interrupts (MSI) propagates to PCI ¾ PCI interrupt propagates to MSI ¾ Power management ¾ Supports in-band power management ¾ Link power states: L0, L0s, L1, L2/3, L2, L3 ¾ Device power management states: D0, D3 (hot) ¾ Hot Plug PEX 8111 PCI 32-bit, 66MHz PLX PCIe May 2007 55 PCI Features ¾ PCI r3.0 compliant ¾ 32-bit PCI operation up to 66 MHz ¾ 64-bit addressing as master and slave ¾ Memory and I/O data transfers ¾ PCI power management support ¾ Supports D0, D3 (hot) PEX 8111 ¾ Arbiter supports 4 external masters PCI 32-bit, 66MHz ¾ Arbiter can be disabled to allow external arbiter PLX PCIe May 2007 56 PCI Express to PCI-X Bridge ¾ PCI Express to PCI-X Bridge 4 lane PCI Express port (x1, x2, or x4 config.) Supports Forward & Reverse modes ¾ 17 x 17 mm PBGA package No heat sink, no air flow required ¾ Low power (2 watts max) ¾ PCI-X 64-/32-bit, 133/100/66 MHz PCI-X 64-/32-bit, 66/50/33/25 MHz PCI Arbiter supports up to 4 masters ¾ PCI Express Maximum payload size = 256B RAS features Polarity Reversal Hot Plug PEX 8114 PLX PCIe May 2007 57 PCIe to PCI-X Bridge Example 4 4 PEX PEX 8114 8114 4 Host CPU Root Root Complex 8 PEX8532 2 PEX 8532 Complex Native 4 Native Native 1 Native ¾ PEX 8114 can create legacy PCI-X slots in a PCI Express System PLX PCIe May 2007 58 PCI Express Features ¾ ¾ ¾ ¾ Maximum payload size 256B Support for polarity reversal EEPROM support Interrupts transferred between ports Message signal interrupt propagates to PCI-X interrupt PCI-X interrupt propagates to message signal interrupt ¾ Power management: Link power management states: L0, L0s, L1, L2/L3 Ready, L2, L3 Device power management states: D0, D3HOT ¾ RAS features Hot Plug master & slave TLP Digest support: PEX 8114 • Poison bit and End to end CRC PLX PCIe May 2007 59 PCI-X/PCI Bus Features ¾ PCI-X r1.0b and PCI r 3.0 compliant PCI-X operation up to 133 MHz 64-bit/32-bit PCI operation up to 66 MHz 64-bit addressing as master and slave Memory and I/O data transfers Up to 8 outstanding split PCI-X transactions PEX 8114 ¾ PCI Power Management r1.1 compliant Supports D0, D3HOT ¾ Arbiter supports 4 external masters Arbiter can be disabled to allow external arbiter PLX PCIe May 2007 60 Bridge on Add-in Card Forward Mode PCI-X Device PCI-X Bus PEX 8114 PCI Express PCI Express Reverse Mode PCIe Endpoint PEX 8114 PCI-X Bus PLX PCIe May 2007 61 AdvancedTCA with AMC ¾ ¾ ¾ ¾ 4 811 X PE X -PXCI PCI cDeevice i Dev PEX P8114 Bridge PCI-X PCI-- X Device Device 8U Form Factor 2.4 times board real estate as 6U Up to eight (8) mezzanine slots Robust power budget exists on ATCA board PPEX Bridge 8114 PCI-X PCI- X Device Device uProc CPU PCI PCI Device Device PEX P8114 Bridge Switch PLX PCIe May 2007 62 Local Bus to PCI Express Bridge ¾ Generic Local to PCI Express 32-Bit Local (up to 66MHz) x1 PCIe 32-Bit Generic Local ¾ Local Bus Modes Non-Multiplexed 32-Bit address/data (C Mode) Multiplexed 32-Bit address/data (J-Mode) PEX 8300 Series ¾ Root Complex & End Point Modes ¾ 2 DMA Channels ¾ Available in volume production PLX PCIe May 2007 63 Local Bus Bridge Road Map Local/PCI Bus Speeds 64 Bits 133 MHz Target (Slave) Devices Bus Master Devices PCI 9656 64 Bits 66 MHz 66MHz 66MHz Local Local Bus Bus Dual Dual DMA DMA • Easy way to Bridge Local Bus to PCI Express • Compatible with PCI 9056 • Works well with FPGAs 32 Bits 66MHz PCI 9056 PEX 8311 66MHz 66MHz Local Local Bus Bus Dual Dual DMA DMA 32-Bit, 32-Bit, 66MHz 66MHz Local Local Bus Bus to to x1 x1 PCIe PCIe PCI 9030 32 Bits 33MHz 32-Bit, 32-Bit, 60MHz 60MHz LB LB to to 32-Bit 32-Bit 33MHZ 33MHZ PCI PCI PCI 9054 PCI 9052 32-Bit, 32-Bit, 50MHz 50MHz LB LB to to 32-Bit, 33MHz 32-Bit, 33MHz PCI PCI Shipping Now In Development 40MHz 40MHz Local Local Bus Bus ISA ISA Compatible Compatible Planned/Concept 2005 & Before 2006 PLX PCIe May 2007 64 PEX 8311 Overview ¾ Generic Local bus to PCI Express Bridge Available in volume production ¾ Generic Local Bus 32-Bit, Up to 66MHz Multiplexed (C-Mode) & Non-Multiplex (J-Mode) 2 DMA Channels Register Backward compatible with PLX PCI 9056, 9656 & 9054 Local Bus protocol backward compatible with PLX PCI 9056 & 9656 up to 66MHz PEX 8311 32-bit / 66MHz Local Bus ¾ PCI Express x1 Lane PCIe Integrated SerDes Rev 1.0a compliant Maximum payload size: 128B 1 Virtual Channel Hot plug support in EndPoint mode PLX PCIe May 2007 65 System Controller Card EEPROM SRAM FPGA DSP Proprietary ASIC Local CPU PEX 8311 Generic Local Bus ¾ Root Complex mode ¾ Control Path implementation: x1 lane ¾ Interface to Switching Fabric cards & I/O Cards ¾ Generic interface to local bus devices ¾ Backward compatible to PCI 9xxx family ¾ 2 Gbps generic local bus/PCIe link PLX PCIe May 2007 66 Industrial Control Video Monitor FPGA FPGA PEX 8311 CPU PEX 8311 PEX 8532 FPGA FPGA SDRAM PEX 8311 PEX 8311 Host Host ¾ x1 links ¾ 2Gbps local bus throughput ¾ More sources per board driving bandwidth ¾ Unidirectional traffic ¾ 1 DMA sufficient ¾ Scatter/gather manages multiple flows PLX PCIe May 2007 67 End of Presentation Thank You PLX PCIe May 2007 68