HD74HC299 8-bit Universal Shift/Storage Register (with 3-state outputs) REJ03D0609–0200 (Previous ADE-205-488) Rev.2.00 Jan 31, 2006 Description The HD74HC299 features multiplexed inputs/outputs to achieve full 8-bit data handling in a single 20-pin package. Due to the large output drive capability and 3-state feature, this device is ideally suited for interfacing with bus lines in a bus oriented system. Two function select inputs and two output control inputs are used to choose the mode of operation as listed in the function table. Synchronous parallel loading is accomplished by taking both function select lines S0 and S1 high. This places the 3-state outputs in a high impedance state, which permits data applied to the input/output lines to be clocked into the register. Reading out of the register can be done while the outputs are enabled in any mode. A direct overriding clear input is provided to clear the register whether the outputs are enabled or disabled. Features • • • • • • High Speed Operation High Output Current: Fanout of 15 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation Taping Abbreviation (Quantity) HD74HC299FPEL SOP-20 pin (JEITA) PRSP0020DD-B (FP-20DAV) FP EL (2,000 pcs/reel) HD74HC299RPEL SOP-20 pin (JEDEC) PRSP0020DC-A (FP-20DBV) RP EL (1,000 pcs/reel) Note: Please consult the sales office for the above package availability. Rev.2.00 Jan 31, 2006 page 1 of 8 HD74HC299 Function Table Inputs Mode Clear Hold Shift Right Shift Left Load Clear L L H H H H H H H Function Select S0 S1 X L L X L L X X L H L H H L H L H H Output Control Clock G1 † G2 † L L X L L X L L X L L L L L L L L L L L X X Inputs/Outputs Serial SL X X X X X X H L X SR X X X X H L X X X A/QA L L QA0 QA0 H L QBn QBn a B/QB L L QB0 QB0 QAn QAn QCn QCn b C/QC L L QC0 QC0 QBn QBn QDn QDn c D/QD L L QD0 QD0 QCn QCn QEn QEn d E/QE L L QE0 QE0 QDn QDn QFn QFn e F/QF L L QF0 QF0 QEn QEn QGn QGn f Outputs G/QG L L QG0 QG0 QFn QFn QHn QHn g H/QH L L QH0 QH0 QGn QGn H L h QA’ L L QA0 QA0 H L QBn QBn a QH’ L L QH0 QH0 QGn QGn H L h Notes: 1. a to h; the level of steady-state input at inputs A through H, respectively. These data are loaded into the flipflop outputs are isolated from the input/output terminals. 2. QA0 to QH0; the level of QA through QH, respectively, before the indicated steady-state input conditions were established. transition of the clock. 3. QAn to QHn; the level of QA through QH, respectively, before the most-recent 4. † ; When one or both output controls are high the eight input/output terminals are disabled to the highimpedance state, however, sequential operation or clearing of the register is not affected. 5. When clear is low, outputs of QA’ and QH’ are low, in spite of other inputs. Pin Arrangement S0 Output controls G1 1 20 VCC S0 2 S1 19 S1 SL 18 17 QH G 3 G/QC 4 G/QG QH E/QE 5 E/QE H/QH 16 H/QH C/QC 6 C/QC F/QF 15 F/QF A/QA 7 A/QA D/QD 14 D/QD QA 8 QA B/QB 13 B/QB Clear 9 Clear SR CK 12 Clock 11 Shift right SR GND 10 (Top view) Rev.2.00 Jan 31, 2006 page 2 of 8 Shift left SL G2 HD74HC299 Logic Diagram Sift right serial-input S1 Sift left serial-input S0 D Clear D D D D D D D Q Q Q Q Q Q Q Q C C CLR C C CLR C C CLR C C CLR C C CLR C C CLR C C CLR C C CLR Clock G1 G2 Q/A A/QA B/QB C/QC D/QD E/QE F/QF G/QG QH H/QH Absolute Maximum Ratings Item Supply voltage range Input / Output voltage Input / Output diode current Output current VCC, GND current Power dissipation Storage temperature Symbol VCC VIN, VOUT IIK, IOK IO ICC or IGND PT Tstg Ratings –0.5 to 7.0 –0.5 to VCC +0.5 ±20 ±35 ±75 500 –65 to +150 Unit V V mA mA mA mW °C Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. Recommended Operating Conditions Item Supply voltage Input / Output voltage Operating temperature Input rise / fall time*1 Symbol VCC VIN, VOUT Ta tr, tf Ratings 2 to 6 0 to VCC –40 to 85 0 to 1000 0 to 500 0 to 400 Notes: 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics. Rev.2.00 Jan 31, 2006 page 3 of 8 Unit V V °C ns Conditions VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V HD74HC299 Electrical Characteristics Item Input voltage Symbol VCC (V) VIH IOZ 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 4.5 6.0 6.0 Iin ICC 6.0 6.0 VIL Output voltage VOH VOL Off-state output current Input current Quiescent supply current Rev.2.00 Jan 31, 2006 page 4 of 8 Ta = 25°C Min Typ Max 1.5 — — 3.15 — — 4.2 — — — — 0.5 — — 1.35 — — 1.8 1.9 2.0 — 4.4 4.5 — 5.9 6.0 — 4.18 — — 5.68 — — 4.18 — — 5.68 — — — 0.0 0.1 — 0.0 0.1 — 0.0 0.1 — — 0.26 — — 0.26 — — 0.26 — — 0.26 — — ±0.5 — — — — ±0.1 4.0 Ta = –40 to+85°C Unit Test Conditions Min Max 1.5 — V 3.15 — 4.2 — — 0.5 V — 1.35 — 1.8 1.9 — V Vin = VIH or VIL IOH = –20 µA 4.4 — 5.9 — 4.13 — IOH = –4 mA QA’ & QH’ Outputs 5.63 — IOH = –5.2 mA 4.13 — IOH = –6 mA A/QA thru H/QH Outputs IOH = –7.8 mA 5.63 — — 0.1 V Vin = VIH or VIL IOL = 20 µA — 0.1 — 0.1 — 0.33 IOH = 4 mA QA’ & QH’ Outputs — 0.33 IOH = 5.2 mA — 0.33 IOH = 6 mA A/QA thru H/QH Outputs IOH = 7.8 mA — 0.33 — ±5.0 µA Vin = VIH or VIL, Vout = VCC or GND — ±1.0 µA Vin = VCC or GND — 40 µA Vin = VCC or GND, Iout = 0 µA HD74HC299 Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns) Item Symbol VCC (V) Maximum clock frequency fmax Propagation delay time tPLH tPHL tPHL tPLH tPHL tPHL Output enable time tZH tZL Output disable time tHZ tLZ Setup time tsu Hold time th Removal time Pulse width Output rise/fall time Input capacitance trem tw tTLH tTHL Cin Ta = 25°C Typ Max — 5 — 25 — 29 — 190 — 38 — 32 — 220 — 44 — 37 — 190 — 38 — 32 — 220 — 44 — 37 — 160 Ta = –40 to +85°C Unit Test Conditions Min Max — 4 MHz — 20 — 23 — 240 ns Clock to QA’ or QH’ — 48 — 41 — 275 ns Clear to QA’ or QH’ — 55 — 47 — 240 ns Clock to QA – QH — 48 — 41 — 275 ns Clear to QA – QH — 55 — 47 — 200 ns 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 Min — — — — — — — — — — — — — — — — 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 — — — — — 100 20 17 5 5 5 50 10 9 80 16 14 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 32 27 160 32 27 — — — — — — — — — — — — 60 12 10 75 15 13 — — — — — 125 25 21 5 5 5 65 13 11 100 20 17 — — — — — — 40 34 200 40 34 — — — — — — — — — — — — 75 15 13 95 19 16 — — 5 10 — 10 Rev.2.00 Jan 31, 2006 page 5 of 8 ns ns Select ns Select ns Clear ns ns A/QA thru H/QH outputs ns QA’ & QH’ outputs pF HD74HC299 Test Circuit VCC VCC G1 G Input Input Pulse Generator Zout = 50 Ω G2 See Function Table Pulse Generator Zout = 50 Ω Output S1 1 kΩ A/QA to H/QH S0 Output SR Output SL CL = 50 pF QH' Clear GND CL = 50 pF QA' Clock OPEN S1 VCC TEST t PLH / t PHL S1 OPEN t ZH/ t HZ t ZL / t LZ GND VCC CL = 50 pF Note : 1. CL includes probe and jig capacitance. Waveforms • Waveform – 1 tr tf Clock VCC 90 % 50 % 90 % 50 % 10 % 0V th t rem Clear VCC 50 % 50 % 0V t su VCC SR or SL 50 % 50 % 0V t su VCC S0 or S1 50 % 50 % 0V tPLH, tPHL QA', QH' 90 % 50 % 10 % QA, QH tTLH, tTHL tPHL, tPLH 90 % 50 % 10 % tTHL, tTLH Note : 1. Input pulse : PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns Rev.2.00 Jan 31, 2006 page 6 of 8 t PHL VOH 50 % VOL HD74HC299 • Waveform – 2 tr tf 90 % 50 % Clock 10 % 10 % tr 0V tf 90 % 50 % S0, S1 VCC 90 % VCC 90 % 50 % 50 % 50 % 10 % 10 % t su 0V th VIH A to H 50 % 50 % VIL VOH QA to QH VOL A to H enabled A to H enabled A to H disabled QA to QH disabled QA to QH enabled QA to QH disabled A to H disabled QA to QH enabled Note : 1. Input pulse : PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns • Waveform – 3 G1, G2 tr tf 90 % 50 % VCC 90 % 50 % 10 % 10 % t ZL 0V t LZ VOH Waveform - A 50 % t ZH Waveform - B 50 % 10 % VOL t HZ 90 % VOH VOL Notes : 1. Input waveform : PRR ≤ 1 MHz, duty cycle 50%, tr ≤ 6 ns, tf ≤ 6 ns 2. Waveform– A is for an output with internal conditions such that the output is low except when disabled by the output control. 3. Waveform– B is for an output with internal conditions such that the output is high except when disabled by the output control. 4. The output are measured one at a time with one transition per measurement. Rev.2.00 Jan 31, 2006 page 7 of 8 HD74HC299 Package Dimensions JEITA Package Code P-SOP20-5.5x12.6-1.27 RENESAS Code PRSP0020DD-B *1 Previous Code FP-20DAV MASS[Typ.] 0.31g D NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. F 20 11 *2 c HE E bp Index mark Reference Symbol Terminal cross section ( Ni/Pd/Au plating ) *3 e Z bp Nom Max D 12.60 13.0 E 5.50 A2 10 1 Dimension in Millimeters Min A1 x M 0.00 0.10 0.34 0.40 0.46 0.15 0.20 0.25 7.80 8.00 A L1 0.20 2.20 bp b1 c A c 1 θ 0° HE A1 θ y e L Detail F 1.27 0.12 y 0.15 0.80 Z L RENESAS Code PRSP0020DC-A *1 Previous Code FP-20DBV 8° x L JEITA Package Code P-SOP20-7.5x12.8-1.27 7.50 0.50 0.70 0.90 1.15 1 MASS[Typ.] 0.52g D F 20 NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" @ DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT @ INCLUDE TRIM OFFSET. 11 HE c *2 E bp Index mark Reference Symbol Terminal cross section ( Ni/Pd/Au plating ) Dimension in Millimeters Min Nom Max D 12.80 13.2 E 7.50 A2 1 Z 10 e *3 bp x A1 M 0.10 0.20 0.34 0.40 0.46 0.20 0.25 0.30 10.40 10.65 A L1 0.30 2.65 bp b1 c A c A1 θ L y 1 θ 0° HE 10.00 e 8° 1.27 x 0.12 y 0.15 0.935 Z Detail F L L Rev.2.00 Jan 31, 2006 page 8 of 8 0.40 1 0.70 1.45 1.27 Sales Strategic Planning Div. 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