RENESAS M16C57

Datasheet
M16C/5M Group, M16C/57 Group
RENESAS MCU
1.
REJ03B0267-0101
Rev.1.01
Jul 23, 2010
Overview
1.1
Features
The M16C/5M and M16C/57 Group’s microcomputers (MCUs) are single-chip control units that utilize
high-performance silicon gate CMOS technology with the M16C/60 Series CPU core. The M16C/5M
Group and M16C/57 Group are available in 64-pin, 80-pin, and 100-pin plastic molded LQFP packages.
The MCUs employ sophisticated instructions for a high level of efficiency and they are capable of
executing instructions at high speed.
The MCUs have the CAN module (M16C/5M Group) and LIN module, which makes them suitable for
automotive control and factory automation LAN systems. In addition, the CPU core boasts a multiplier and
DMAC for high-speed operation processing which makes it adequate for controlling office equipment,
home appliances, and industrial equipment.
The M16C/5M and M16C/57 Group’s MCUs are a high-end microcontroller series in the M16C/5L and
M16C/56 Group, featuring a single architecture as well as compatible pin assignments and peripheral
functions. They have an on-chip E2PROM emulation data flash (E2dataFlash) which is a data flash with
serial E2PROM.
1.1.1
Applications
Automotive, car audio, factory automation LAN system, etc.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 1 of 156
M16C/5M Group, M16C/57 Group
1.2
1. Overview
Specifications
Table 1.1 to Table 1.6 list specifications of the M16C/5M Group, M16C/57 Group.
Table 1.1
Item
CPU
Specifications (100-pin Package) (1/2)
Function
Specification
M16C/60 Series CPU Core (Multiplier: 16 × 16 32 bits, Multiply-accumulate
unit: 16 × 16 + 32 32 bits))
Central processing unit • Basic instructions: 91
• Minimum instruction execution time:
• Operating mode: Single-chip mode
Memory
ROM, RAM, data flash,
See Table 1.7 to Table 1.10.
E2dataFlash
Voltage
Detection
Voltage detector
• 2 voltage detect points
• 5 circuits (Main clock, sub clock, PLL frequency synthesizer, 125 kHz onchip oscillator, 40 MHz on-chip oscillator)
Clock
Clock generator
I/O Ports
Programmable I/O
ports
Interrupts
Watchdog Timer
DMA
Timers
DMAC
16-bit timer × 5
Timer mode, event counter mode, one-shot timer mode, pulse-width
modulation (PWM) mode
Timer A
Two-phase pulse signal processing in event counter mode (two-phase
encoder input) × 3
Programmable output mode × 3
16-bit timer × 6
Timer B
Timer mode, event counter mode, pulse frequency measurement mode,
pulse-width measurement mode
Timer function for three- Three-phase motor control timer × 1 (timers A1, A2, A4, and B2 used)
phase motor control
On-chip dead time timer
Timer S (Input capture/
output compare)
Task monitoring timer
Real-time clock
Serial
Interface
• Oscillation stop detector: Main clock oscillator stop/restart detection
• Frequency divide circuit: Divide-by-1, 2, 4, 8, or 16 selectable
• Low-power consumption modes: Wait mode, stop mode
• Real-time clock
• 70 CMOS inputs/outputs, a pull-up resistor selectable
• N-channel open drain ports: 1
• Interrupt vectors: 70
• External interrupt inputs: 13 (NMI, INT × 8, key input × 4)
• Interrupt priority levels: 7
• 15 bits × 1 (with prescaler)
• Automatic reset start function selectable
• Dedicated 125 kHz on-chip oscillator for the watchdog timer contained
• 4 channels, Cycle-steal transfer mode
• Trigger sources: 50
• Transfer modes: 2 (single transfer, repeat transfer)
UART0 to UART4
Multi-master I2C-bus Interface
A/D Converter
D/A Converter
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
• 16-bit timer × 1 (base timer)
• I/O: 8 channels
16-bit timer × 1 channel
Count: seconds, minutes, hours, weeks
4 channels (UART, clock synchronous serial interface)
1 channels (UART, clock synchronous serial interface, I2C-bus, IEBus)
1 channel
10-bit resolution × 26 channels
8-bit resolution × 1 channel
Page 2 of 156
M16C/5M Group, M16C/57 Group
Table 1.2
1. Overview
Specifications (100-pin Package) (2/2)
Item
Function
Specification
• 1 circuit
• CRC-CCITT (X16 + X12 + X5 + 1), CRC-16 (X16 + X15 + X2 + 1) compliant
• MSB/LSB selectable
CRC Calculator
Serial Bus Interface
1 channel
• Clock synchronous serial communication mode
• 4-wire bus communication mode
• Programmable character length: 8 to 16 bits
LIN Module
1 channel
CAN Module
32-slot message buffer × 2 channels or 1 channel (M16C/5M Group) (1)
• Programming and erasure supply voltage: 3.0 to 5.5 V
• Programming and erasure endurance: 1,000 times (program ROM 1,
Flash Memory
program ROM 2)/10,000 times (data flash)
• Program security: ROM code protect, ID code check
E2dataFlash
Debug Functions
Operating Frequency/Power Supply
Voltage
Current Consumption
Operating Temperature
Package
Programming and erasure endurance: 100,000 (1)
On-board flash rewrite function, address match × 4
32 MHz / 3.0 to 5.5 V
Described in 31. “Electrical Characteristics”
-40°C to 85°C
-40°C to 125°C (1)
100-pin plastic mold LQFP: PLQP0100KB-A (Previous package code:
100P6Q-A)
Note:
1. Refer to Table 1.7 “M16C/5M Group Product List (J-Version)” to Table 1.10 “M16C/57 Group Product
List (K-Version) for Operating Temperature, CAN Module, and E2dataFlash.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 3 of 156
M16C/5M Group, M16C/57 Group
Table 1.3
Item
CPU
1. Overview
Specifications (80-pin Package) (1/2)
Function
Specification
M16C/60 Series CPU Core (Multiplier: 16 × 16 32 bits, Multiply-accumulate
unit: 16 × 16 + 32 32 bits))
Central processing unit • Basic instructions: 91
• Minimum instruction execution time:
• Operating mode: Single-chip mode
Memory
ROM, RAM, data flash,
See Table 1.7 to Table 1.10.
E2dataFlash
Voltage
Detection
Voltage detector
• 2 voltage detect points
• 5 circuits (Main clock, sub clock, PLL frequency synthesizer, 125 kHz onchip oscillator, 40 MHz on-chip oscillator)
Clock
Clock generator
I/O Ports
Programmable I/O
ports
Interrupts
Watchdog Timer
DMA
Timers
DMAC
16-bit timer × 5
Timer mode, event counter mode, one-shot timer mode, pulse-width
modulation (PWM) mode
Timer A
Two-phase pulse signal processing in event counter mode (two-phase
encoder input) × 3
Programmable output mode × 3
16-bit timer × 3
Timer B
Timer mode, event counter mode, pulse frequency measurement mode,
pulse-width measurement mode
Timer function for three- Three-phase motor control timer × 1 (timers A1, A2, A4, and B2 used)
phase motor control
On-chip dead time timer
Timer S (Input capture/
output compare)
Task monitoring timer
Real-time clock
Serial
Interface
• Oscillation stop detector: Main clock oscillator stop/restart detection
• Frequency divide circuit: Divide-by-1, 2, 4, 8, or 16 selectable
• Low-power consumption modes: Wait mode, stop mode
• Real-time clock
• 70 CMOS inputs/outputs, a pull-up resistor selectable
• N-channel open drain ports: 1
• Interrupt vectors: 70
• External interrupt inputs: 11 (NMI, INT × 6, key input × 4)
• Interrupt priority levels: 7
• 15 bits × 1 (with prescaler)
• Automatic reset start function selectable
• Dedicated 125 kHz on-chip oscillator for the watchdog timer contained
• 4 channels, Cycle-steal transfer mode
• Trigger sources: 43
• Transfer modes: 2 (single transfer, repeat transfer)
UART0 to UART4
Multi-master I2C-bus Interface
A/D Converter
D/A Converter
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
• 16-bit timer × 1 (base timer)
• I/O: 8 channels
16-bit timer × 1 channel
Count: seconds, minutes, hours, weeks
4 channels (UART, clock synchronous serial interface)
1 channels (UART, clock synchronous serial interface, I2C-bus, IEBus)
1 channel
10-bit resolution × 27 channels
8-bit resolution × 1 channel
Page 4 of 156
M16C/5M Group, M16C/57 Group
Table 1.4
1. Overview
Specifications (80-pin Package) (2/2)
Item
Function
Specification
• 1 circuit
• CRC-CCITT (X16 + X12 + X5 + 1), CRC-16 (X16 + X15 + X2 + 1) compliant
• MSB/LSB selectable
CRC Calculator
Serial Bus Interface
1 channel
• Clock synchronous serial communication mode
• 4-wire bus communication mode
• Programmable character length: 8 to 16 bits
LIN Module
1 channel
CAN Module
32-slot message buffer × 2 channels or 1 channel (M16C/5M Group) (1)
• Programming and erasure supply voltage: 3.0 to 5.5 V
• Programming and erasure endurance: 1,000 times (program ROM 1,
Flash Memory
program ROM 2)/10,000 times (data flash)
• Program security: ROM code protect, ID code check
E2dataFlash
Debug Functions
Operating Frequency/Power Supply
Voltage
Current Consumption
Operating Temperature
Package
Programming and erasure endurance: 100,000 (1)
On-board flash rewrite function, address match × 4
32 MHz / 3.0 to 5.5 V
Described in 31. “Electrical Characteristics”
-40°C to 85°C
-40°C to 125°C (1)
80-pin plastic mold LQFP: PLQP0080KB-A (Previous package code: 80P6Q-A)
Note:
1. Refer to Table 1.7 “M16C/5M Group Product List (J-Version)” to Table 1.10 “M16C/57 Group Product
List (K-Version) for Operating Temperature, CAN Module, and E2dataFlash.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 5 of 156
M16C/5M Group, M16C/57 Group
Table 1.5
Item
CPU
1. Overview
Specifications (64-pin Package) (1/2)
Function
Specification
M16C/60 Series CPU Core (Multiplier: 16 × 16 32 bits, Multiply-accumulate
unit: 16 × 16 + 32 32 bits))
Central processing unit • Basic instructions: 91
• Minimum instruction execution time:
• Operating mode: Single-chip mode
Memory
ROM, RAM, data flash,
See Table 1.7 to Table 1.10.
E2dataFlash
Voltage
Detection
Voltage detector
• 2 voltage detect points
• 5 circuits (Main clock, sub clock, PLL frequency synthesizer, 125 kHz onchip oscillator, 40 MHz on-chip oscillator)
Clock
Clock generator
I/O Ports
Programmable I/O
ports
Interrupts
Watchdog Timer
DMA
Timers
DMAC
16-bit timer × 5
Timer mode, event counter mode, one-shot timer mode, pulse-width
modulation (PWM) mode
Timer A
Two-phase pulse signal processing in event counter mode (two-phase
encoder input) × 3
Programmable output mode × 3
16-bit timer × 3
Timer B
Timer mode, event counter mode, pulse frequency measurement mode,
pulse-width measurement mode
Timer function for three- Three-phase motor control timer × 1 (timers A1, A2, A4, and B2 used)
phase motor control
On-chip dead time timer
Timer S (Input capture/
output compare)
Task monitoring timer
Real-time clock
Serial
Interface
• Oscillation stop detector: Main clock oscillator stop/restart detection
• Frequency divide circuit: Divide-by-1, 2, 4, 8, or 16 selectable
• Low-power consumption modes: Wait mode, stop mode
• Real-time clock
• 54 CMOS inputs/outputs, a pull-up resistor selectable
• N-channel open drain ports: 1
• Interrupt vectors: 70
• External interrupt inputs: 11 (NMI, INT × 6, key input × 4)
• Interrupt priority levels: 7
• 15 bits × 1 (with prescaler)
• Automatic reset start function selectable
• Dedicated 125 kHz on-chip oscillator for the watchdog timer contained
• 4 channels, Cycle-steal transfer mode
• Trigger sources: 41
• Transfer modes: 2 (single transfer, repeat transfer)
UART0 to UART3
Multi-master I2C-bus Interface
A/D Converter
D/A Converter
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
• 16-bit timer × 1 (base timer)
• I/O: 8 channels
16-bit timer × 1 channel
Count: seconds, minutes, hours, weeks
3 channels (UART, clock synchronous serial interface)
1 channels (UART, clock synchronous serial interface, I2C-bus, IEBus)
1 channel
10-bit resolution × 16 channels
8-bit resolution × 1 channel
Page 6 of 156
M16C/5M Group, M16C/57 Group
Table 1.6
1. Overview
Specifications (64-pin Package) (2/2)
Item
Function
Specification
• 1 circuit
• CRC-CCITT (X16 + X12 + X5 + 1), CRC-16 (X16 + X15 + X2 + 1) compliant
• MSB/LSB selectable
CRC Calculator
Serial Bus Interface
1 channel
• Clock synchronous serial communication mode
• 4-wire bus communication mode
• Programmable character length: 8 to 16 bits
LIN Module
1 channel
CAN Module
32-slot message buffer × 2 channels or 1 channel (M16C/5M Group) (1)
• Programming and erasure supply voltage: 3.0 to 5.5 V
• Programming and erasure endurance: 1,000 times (program ROM 1,
Flash Memory
program ROM 2)/10,000 times (data flash)
• Program security: ROM code protect, ID code check
E2dataFlash
Debug Functions
Operating Frequency/Power Supply
Voltage
Current Consumption
Operating Temperature
Package
Programming and erasure endurance: 100,000 (1)
On-board flash rewrite function, address match × 4
32 MHz / 3.0 to 5.5 V
Described in 31. “Electrical Characteristics”
-40°C to 85°C
-40°C to 125°C (1)
64-pin plastic mold LQFP: PLQP0064KB-A (Previous package code: 64P6Q-A)
Note:
1. Refer to Table 1.7 “M16C/5M Group Product List (J-Version)” to Table 1.10 “M16C/57 Group Product
List (K-Version) for Operating Temperature, CAN Module, and E2dataFlash.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 7 of 156
M16C/5M Group, M16C/57 Group
1.3
1. Overview
Product List
Table 1.7 to Table 1.8 list product informations. Figure 1.1 shows part numbers, memory sizes, and
packages. Figure 1.2 shows marking drawing (top view).
Table 1.7
M16C/5M Group Product List (J-Version)
ROM Capacity
Part Number
R5F35M23JFE
(P)
R5F35M33JFF
(P)
R5F35M73JFE
(P)
R5F35M83JFF
(P)
R5F35M16JFB
(P)
R5F35M26JFE
(P)
R5F35M36JFF
(P)
R5F35M66JFB
(P)
R5F35M76JFE
(P)
R5F35M86JFF
(P)
Program
ROM 1
96 Kbytes
Program
ROM 2
Data flash
16 Kbytes
4 Kbytes
× 2 blocks
As of May. 2010
RAM
E2dataFlash Capacity
CAN
PLQP0064KB-A
8 Kbytes
PLQP0080KB-A
—–
PLQP0064KB-A
PLQP0100KB-A
4 Kbytes
128 Kbytes 16 Kbytes
4 Kbytes
× 2 blocks
PLQP0080KB-A
PLQP0064KB-A
12 Kbytes
1 channel
—–
R5F35M6EJFB (P)
256 Kbytes 16 Kbytes
4 Kbytes
× 2 blocks
PLQP0080KB-A
PLQP0064KB-A
20 Kbytes
PLQP0100KB-A
—–
PLQP0080KB-A
Operating
Temperature
PLQP0080KB-A -40°C to 85°C
PLQP0064KB-A
(P)
PLQP0064KB-A
R5F35MB3JFE (P)
R5F35MC3JFF (P)
96 Kbytes
R5F35ME3JFE (P)
R5F35MF3JFF
16 Kbytes
4 Kbytes
× 2 blocks
(P)
4 Kbytes
8 Kbytes
PLQP0080KB-A
—–
PLQP0064KB-A
PLQP0100KB-A
R5F35MA6JFB (P)
4 Kbytes
R5F35MB6JFE (P)
R5F35MC6JFF (P)
R5F35MD6JFB (P)
128 Kbytes 16 Kbytes
4 Kbytes
× 2 blocks
PLQP0080KB-A
2 channels
(P)
PLQP0080KB-A
PLQP0100KB-A
4 Kbytes
R5F35MBEJFE (D)
R5F35MDEJFB (P)
PLQP0100KB-A
PLQP0064KB-A
R5F35MAEJFB (D)
R5F35MCEJFF (D)
PLQP0064KB-A
12 Kbytes
—–
R5F35ME6JFE (P)
R5F35MF6JFF
PLQP0080KB-A
PLQP0100KB-A
4 Kbytes
R5F35M7EJFE (P)
R5F35M8EJFF
PLQP0100KB-A
PLQP0064KB-A
R5F35M2EJFE (P)
(P)
Remarks
PLQP0080KB-A
4 Kbytes
R5F35M1EJFB (P)
R5F35M3EJFF
Package Name
256 Kbytes 16 Kbytes
4 Kbytes
× 2 blocks
20 Kbytes
—–
R5F35MEEJFE (P)
R5F35MFEJFF (P)
PLQP0080KB-A
PLQP0064KB-A
PLQP0100KB-A
PLQP0080KB-A
PLQP0064KB-A
(D): Under development
(P): Under planning
The old package names are as follows:
PLQP00100KB-A: 100P6Q-A
PLQP0080KB-A: 80P6Q-A
PLQP0064KB-A: 64P6Q-A
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 8 of 156
M16C/5M Group, M16C/57 Group
Table 1.8
1. Overview
M6C/5M Group Product List (K-Version)
ROM Capacity
Part Number
Program
ROM 1
Program
ROM 2
Data flash
16 Kbytes
4 Kbytes
× 2 blocks
R5F35M23KFE (P)
R5F35M33KFF (P)
96 Kbytes
R5F35M73KFE (P)
R5F35M83KFF (P)
As of May. 2010
RAM
E2dataFlash Capacity
CAN
PLQP0064KB-A
8 Kbytes
PLQP0080KB-A
—–
PLQP0064KB-A
PLQP0100KB-A
4 Kbytes
R5F35M26KFE (P)
R5F35M66KFB (P)
128 Kbytes 16 Kbytes
4 Kbytes
× 2 blocks
PLQP0080KB-A
PLQP0064KB-A
12 Kbytes
1 channel
—–
R5F35M76KFE (P)
R5F35M86KFF (P)
256 Kbytes 16 Kbytes
4 Kbytes
× 2 blocks
PLQP0080KB-A
PLQP0064KB-A
20 Kbytes
PLQP0100KB-A
—–
R5F35M7EKFE (P)
PLQP0080KB-A
Operating Temperature
PLQP0080KB-A
-40°C to 125°C
PLQP0064KB-A
R5F35M8EKFF (P)
PLQP0064KB-A
R5F35MB3KFE (P)
R5F35MC3KFF (P)
96 Kbytes
R5F35ME3KFE (P)
16 Kbytes
4 Kbytes
× 2 blocks
R5F35MF3KFF (P)
4 Kbytes
8 Kbytes
PLQP0080KB-A
—–
PLQP0064KB-A
PLQP0100KB-A
R5F35MA6KFB (P)
4 Kbytes
R5F35MB6KFE (P)
R5F35MC6KFF (P)
R5F35MD6KFB (P)
128 Kbytes 16 Kbytes
4 Kbytes
× 2 blocks
PLQP0080KB-A
2 channels
R5F35MF6KFF (P)
PLQP0100KB-A
PLQP0080KB-A
PLQP0064KB-A
R5F35MAEKFB (P)
PLQP0100KB-A
4 Kbytes
R5F35MBEKFE (P)
R5F35MDEKFB (P)
PLQP0064KB-A
12 Kbytes
—–
R5F35ME6KFE (P)
R5F35MCEKFF (P)
PLQP0080KB-A
PLQP0100KB-A
4 Kbytes
R5F35M2EKFE (P)
R5F35M6EKFB (P)
PLQP0100KB-A
PLQP0064KB-A
R5F35M1EKFB (P)
R5F35M3EKFF (P)
Remarks
PLQP0080KB-A
4 Kbytes
R5F35M16KFB (P)
R5F35M36KFF (P)
Package Name
256 Kbytes 16 Kbytes
4 Kbytes
× 2 blocks
20 Kbytes
—–
R5F35MEEKFE (P)
R5F35MFEKFF (P)
PLQP0080KB-A
PLQP0064KB-A
PLQP0100KB-A
PLQP0080KB-A
PLQP0064KB-A
(D): Under development
(P): Under planning
The old package names are as follows:
PLQP00100KB-A: 100P6Q-A
PLQP0080KB-A: 80P6Q-A
PLQP0064KB-A: 64P6Q-A
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 9 of 156
M16C/5M Group, M16C/57 Group
Table 1.9
1. Overview
M16C/57 Group Product List (J-Version)
ROM Capacity
Part Number
R5F35723JFE
(P)
R5F35733JFF
(P)
R5F35773JFE
(P)
R5F35783JFF
(P)
R5F35716JFB
(P)
R5F35726JFE
(P)
R5F35736JFF
(P)
R5F35766JFB
(P)
R5F35776JFE
(P)
R5F35786JFF
(P)
R5F3571EJFB
(P)
R5F3572EJFE
(P)
R5F3573EJFF
(P)
R5F3576EJFB
(P)
R5F3577EJFE
(P)
R5F3578EJFF
(P)
Program
ROM 1
96 Kbytes
Program
ROM 2
Data flash
16 Kbytes
4 Kbytes
× 2 blocks
As of May. 2010
RAM
E2dataFlash Capacity
CAN
Package Name
Remarks
PLQP0080KB-A
4 Kbytes
PLQP0064KB-A
8 Kbytes
PLQP0080KB-A
—–
PLQP0064KB-A
PLQP0100KB-A
4 Kbytes
128 Kbytes 16 Kbytes
4 Kbytes
× 2 blocks
PLQP0080KB-A
PLQP0064KB-A
12 Kbytes
N/A
—–
Operating
Temperature
PLQP0080KB-A
-40°C to 85°C
PLQP0064KB-A
PLQP0100KB-A
PLQP0100KB-A
4 Kbytes
256 Kbytes 16 Kbytes
4 Kbytes
× 2 blocks
PLQP0080KB-A
PLQP0064KB-A
20 Kbytes
PLQP0100KB-A
—–
PLQP0080KB-A
PLQP0064KB-A
(D): Under development
(P): Under planning
The old package names are as follows:
PLQP00100KB-A: 100P6Q-A
PLQP0080KB-A: 80P6Q-A
PLQP0064KB-A: 64P6Q-A
Table 1.10
M16C/57 Group Product List (K-Version)
ROM Capacity
Part Number
R5F35723KFE
(P)
R5F35733KFF
(P)
R5F35773KFE
(P)
R5F35783KFF
(P)
R5F35716KFB
(P)
R5F35726KFE
(P)
R5F35736KFF
(P)
R5F35766KFB
(P)
R5F35776KFE
(P)
R5F35786KFF
(P)
R5F3571EKFB
(P)
R5F3572EKFE
(P)
R5F3573EKFF
(P)
R5F3576EKFB
(P)
R5F3577EKFE
(P)
R5F3578EKFF
(P)
Program
ROM 1
96 Kbytes
Program
ROM 2
Data flash
16 Kbytes
4 Kbytes
× 2 blocks
As of May. 2010
RAM
E2dataFlash Capacity
CAN
Package Name
Remarks
PLQP0080KB-A
4 Kbytes
PLQP0064KB-A
8 Kbytes
PLQP0080KB-A
—–
PLQP0064KB-A
PLQP0100KB-A
4 Kbytes
128 Kbytes 16 Kbytes
4 Kbytes
× 2 blocks
PLQP0080KB-A
PLQP0064KB-A
12 Kbytes
N/A
—–
Operating
Temperature
PLQP0080KB-A -40°C to 125°C
PLQP0064KB-A
PLQP0100KB-A
PLQP0100KB-A
4 Kbytes
256 Kbytes 16 Kbytes
4 Kbytes
× 2 blocks
PLQP0080KB-A
20 Kbytes
—–
PLQP0064KB-A
PLQP0100KB-A
PLQP0080KB-A
PLQP0064KB-A
(D): Under development
(P): Under planning
The old package names are as follows:
PLQP00100KB-A: 100P6Q-A
PLQP0080KB-A: 80P6Q-A
PLQP0064KB-A: 64P6Q-A
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 10 of 156
M16C/5M Group, M16C/57 Group
MCU Part No.
1. Overview
R 5 F 3 5M 2 E J FE
Package type
FB: PLQP0100KB-A (100P6Q-A)
FE: PLQP0080KB-A (80P6Q-A)
FF: PLQP0064KB-A (64P6Q-A)
Property code
J: Operating temperature -40°C to 85°C
K: Operating temperature -40°C to 125°C
Memory capacity
Program ROM 1/RAM
3: 96 Kbytes/8 Kbytes
6: 128 Kbytes/12 Kbytes
E: 256 Kbytes/20 Kbytes
Pin / CAN module / E 2 data flash capacity
1: 100 pins / 1 channel / 4 Kbytes
2: 80 pins / 1 channel / 4 Kbytes
3: 64 pins / 1 channel / 4 Kbytes
57 Group has no CAN Module
6: 100 pins / 1 channel / —
7: 80 pins / 1 channel / —
8: 64 pins / 1 channel / —
A: 100 pins / 2 channels / 4 Kbytes
B: 80 pins / 2 channels / 4 Kbytes
C: 64 pins / 2 channels / 4 Kbytes
D: 100 pins / 2 channels / —
E: 80 pins / 2 channels / —
F: 64 pins / 2 channels / —
Group Name
5M: M16C/5M Group,
57: M16C/57 Group
16-bit MCU
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.1
Part Number, Memory Size, and Package
M16C
R5F35M2EJFE
XXXXXXX
Figure 1.2
Part number
(See Figure 1.1 “Part Number, Memory Size, and Package”.)
Seven digit date code
Marking Diagram of Flash Memory Version (Top View)
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 11 of 156
M16C/5M Group, M16C/57 Group
1.4
1. Overview
Block Diagrams
Figure 1.3 to Figure 1.5 show a block diagram of M16C/5M Group and M16C/57 Group.
I/O ports
8
8
8
8
8
8
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Peripherals
Clock generator
Three-phase motor control circuit
Multi-master I2C-bus (1 channel)
E2dataFlash
Voltage detector
Power-on reset
8
Real-time clock
CRC calculator
(CCITT, CRC-16)
CAN module
(32-slot message buffer,
2 or 1 channel)
(M16C/5M Group only) (1)
Port P8
Task monitoring timer (1 channel)
LIN module (1 channel)
8
Timer S
(Input capture/output compare)
Time measurement: 8 channels
Waveform generating: 8 channels
Port P7
XIN-XOUT
XCIN-XCOUT
40 MHz on-chip oscillator
125 kHz on-chip oscillator
PLL frequency synthesizer
DMAC (4 channels)
8
UART/clock synchronous serial
interface (5 channels)
Port P6
Timer (16-bit)
Output (timer A): 5
Input (timer B): 6
(1)
On-chip debugger
D/A converter (8-bit x 1 circuit)
R0L
R1L
R2
R3
R3
SB
USP
RAM (1)
ISP
8
Watchdog timer (15 bits,
with the dedicated 125 kHz on-chip
oscillator for the watchdog timer)
R0H
R1H
Memory
ROM (1)
Port P10
Serial bus interface
(1 channel)
M16C/60 Series CPU core
8
Port P9
A/D converter
(10-bit x 26 channel)
INTB
A0
A1
FB
FB
PC
FLG
Multiplier
Note:
1. The ROM size, RAM size, number of channels for the CAN module, and whether the E 2dataFlash is provided or not
depend on the MCU type.
Figure 1.3
100-Pin Block Diagram
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 12 of 156
M16C/5M Group, M16C/57 Group
I/O ports
1. Overview
8
8
8
8
Port P0
Port P1
Port P2
Port P3
Peripherals
Clock generator
Multi-master I2C-bus (1 channel)
E2dataFlash
CRC calculator
(CCITT, CRC-16)
Voltage detector
(1)
Power-on reset
R0L
R1L
R2
R3
R3
SB
USP
ISP
8
R0H
R1H
Memory
ROM (1)
7
Watchdog timer (15 bits,
with the dedicated 125 kHz on-chip
oscillator for the watchdog timer)
M16C/60 Series CPU core
Port P10
Serial bus interface
(1 channel)
Port P9
On-chip debugger
A/D converter
(10-bit x 27 channel)
D/A converter (8-bit x 1 circuit)
8
Real-time clock
CAN module
(32-slot message buffer,
2 or 1 channel)
(M16C/5M Group only) (1)
Port P8
Task monitoring timer (1 channel)
LIN module (1 channel)
8
Timer S
(Input capture/output compare)
Time measurement: 8 channels
Waveform generating: 8 channels
Port P7
XIN-XOUT
XCIN-XCOUT
40 MHz on-chip oscillator
125 kHz on-chip oscillator
PLL frequency synthesizer
DMAC (4 channels)
8
Three-phase motor control circuit
UART/clock synchronous serial
interface (5 channels)
Port P6
Timer (16-bit)
Output (timer A): 5
Input (timer B): 3
RAM (1)
INTB
A0
A1
FB
FB
PC
FLG
Multiplier
Note:
1. The ROM size, RAM size, number of channels for the CAN module, and whether the E 2dataFlash is provided or not
depend on the MCU type.
Figure 1.4
80-Pin Block Diagram
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 13 of 156
M16C/5M Group, M16C/57 Group
1. Overview
I/O ports
4
3
8
4
Port P0
Port P1
Port P2
Port P3
Peripherals
Clock generator
Three-phase motor control circuit
Multi-master I2C-bus (1 channel)
E2dataFlash
CRC calculator
(CCITT, CRC-16)
Voltage detector
(1)
8
CAN module
(32-slot message buffer,
2 or 1 channel)
(M16C/5M Group only) (1)
8
Task monitoring timer (1 channel)
LIN module (1 channel)
Port P8
Timer S
(Input capture/output compare)
Time measurement: 8 channels
Waveform generating: 8 channels
Port P7
XIN-XOUT
XCIN-XCOUT
40 MHz on-chip oscillator
125 kHz on-chip oscillator
PLL frequency synthesizer
DMAC(4 channels)
8
UART/clock synchronous serial
interface (4 channels)
Port P6
Timer (16-bit)
Output (timer A): 5
Input (timer B): 3
Power-on reset
On-chip debugger
Watchdog timer (15 bits,
the dedicated 125 kHz on-chip
oscillator for the watchdog timer)
R0H
R1H
R0L
R1L
R2
R3
R3
SB
Memory
ROM (1)
8
Serial bus interface
(1 channel)
M16C/60 Series CPU core
Port P10
D/A converter (8-bit x 1 circuit)
4
A/D converter
(10-bit x 16 channels)
Port P9
Real-time clock
USP
ISP
RAM (1)
INTB
A0
A1
FB
FB
PC
FLG
Multiplier
Note:
1. The ROM size, RAM size, number of channels for the CAN module, and whether the E 2dataFlash is provided or not
depend on the MCU type.
Figure 1.5
64-Pin Block Diagram
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 14 of 156
M16C/5M Group, M16C/57 Group
1.5
1. Overview
Pin Assignments
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
76
50
77
49
78
48
79
47
80
46
81
45
82
44
M16C/5M Group
M16C/57 Group
83
84
85
86
43
42
41
40
87
39
88
38
PLQP0100KB-A
(100P6Q-A)
(Top view)
89
90
91
92
93
37
36
35
34
33
25
24
23
22
21
20
19
18
17
16
15
14
13
12
P4_2
P4_3
P4_4
P4_5
P4_6
P4_7
P5_0
P5_1
P5_2
P5_3
P5_4
P5_5
P5_6
P5_7
P6_0 / RTCOUT / CTS0 / RTS0
P6_1 / CLK0
P6_2 / RXD0
P6_3 / TXD0
P6_4 / CTS1 / RTS1
P6_5 / CLK1
P6_6 / RXD1
P6_7 / TXD1
P7_0 / TXD2 / SDA2 / CTS1 / RTS1 / TA0OUT
P7_1 / RXD2 / SCL2 / CLK1 / TA0IN / TB5IN
P7_2 / CLK2 / TA1OUT / V / RXD1
P9_4 / TB4IN
P9_3/DA0/TB3IN
P9_2 / TB2IN / AN3_2
P9_1 / TB1IN / AN3_1
P9_0 / TB0IN / CLKOUT / AN3_0
NC
CNVSS
P8_7 / XCIN
P8_6 / XCOUT
RESET
XOUT
VSS
XIN
VCC
P8_5 / NMI / SD
P8_4 / INT2 / ZP
P8_3 / INT1
P8_2 / INT0
P8_1 / TA4IN / U / TSUDB
P8_0 / TA4OUT / U / TSUDA
P7_7 / TA3IN / CRX1 (1)
P7_6 / TA3OUT / CTX1 (1)
P7_5 / TA2IN / W / LIN0IN
P7_4 / TA2OUT / W / LIN0OUT
P7_3 / CTS2 / RTS2 / TA1IN / V /TXD1
11
26
9
10
27
100
8
28
99
7
29
98
6
97
5
31
30
4
96
3
32
95
2
94
1
P1_2 / AN2_2
P1_1 / AN2_1
P1_0 / AN2_0
P0_7 / AN0_7
P0_6 / AN0_6
P0_5 / AN0_5
P0_4 / AN0_4
P0_3 / AN0_3
P0_2 / AN0_2
P0_1 / AN0_1
P0_0 / AN0_0
P10_7 / AN_7 / KI3
P10_6 / AN_6 / KI2
P10_5 / AN_5 / KI1
P10_4 / AN_4 / KI0
P10_3 / AN_3
P10_2 / AN_2
P10_1 / AN_1
AVSS
P10_0 / AN_0
VREF
AVCC
P9_7 / RXD4 / AN2_7
P9_6 / TXD4 / CTX0 (1) / AN2_6
P9_5 / CLK4 / CRX0 (1) / AN2_5
74
75
P1_3 / AN2_3
P1_4
P1_5 / INT3 / IDV / ADTRG
P1_6 / INT4 / IDW
P1_7 / INT5 / IDU / INPC1_7
P2_0 / OUTC1_0 / INPC1_0 / SDAMM
P2_1 / OUTC1_1 / INPC1_1 / SCLMM
P2_2 / OUTC1_2 / INPC1_2
P2_3 / / OUTC1_3 / INPC1_3
P2_4 / INT6 / OUTC1_4 / INPC1_4
P2_5 / INT7 / OUTC1_5 / INPC1_5
P2_6 / OUTC1_6 / INPC1_6
P2_7 / OUTC1_7 / INPC1_7
VSS
P3_0 / CLK3 / SSCK0
VCC
P3_1 / RXD3 / SSI0
P3_2 / TXD3 / SSO0
P3_3 / CTS3 / RTS3 / SCS0
P3_4
P3_5
P3_6
P3_7
P4_0
P4_1
Figure 1.6 shows the pin assignments for the 100-pin package, Figure 1.7 shows the pin assignments for
the 80-pin package, and Figure 1.8 shows the pin assignments for the 64-pin package.
Note:
1. Pins CTX0, CRX0, CTX1, and CRX1 are only available in the M16C/5M Group.
Figure 1.6
Pin Assignments for 100-Pin Package (Top View)
Set bits PACR2 to PACR0 in the PACR register to 100b before signals are input or output to individual
pins after reset. When the PACR register is not set, signals are not input or output for some of the pins.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 15 of 156
M16C/5M Group, M16C/57 Group
Table 1.11
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
1. Overview
Pin Names, 100-Pin Package(1/2)
Control
Pin
Port
Interrupt
Pin
Timer Pin
21
P9_4
P9_3
P9_2
P9_1
CLKOUT P9_0
NC
CNVSS
XCIN
P8_7
XCOUT
P8_6
RESET
XOUT
VSS
XIN
VCC
P8_5
P8_4
P8_3
P8_2
P8_1
P8_0
P7_7
22
P7_6
TA3OUT
23
24
25
P7_5
P7_4
P7_3
TA2IN/W
TA2OUT/W
TA1IN/V
26
27
P7_2
P7_1
TA1OUT/V
TA0IN/TB5IN
28
P7_0
TA0OUT
29
P6_7
P6_6
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Timer S Pin
TB4IN
TB3IN
TB2IN
TB1IN
TB0IN
NMI
INT2
INT1
INT0
Multimaster
Analog Pin
I2C-bus Pin
DA0
AN3_2
AN3_1
AN3_0
SD
ZP
TA4IN/U
TA4OUT/U
TA3IN
TSUDB
TSUDA
P6_5
P6_4
P6_3
P6_2
P6_1
P6_0
UART/CAN/LIN/Serial
Bus Interface Pin
RTCOUT
CRX1(1)
CTX1 (1)
LIN0IN
LIN0OUT
CTS2/RTS2/TXD1
CLK2/RXD1
RXD2/SCL2/CLK1
TXD2/SDA2/CTS1/RTS1
TXD1
RXD1
CLK1
CTS1/RTS1
TXD0
RXD0
CLK0
CTS0/RTS0
P5_7
P5_6
P5_5
P5_4
P5_3
P5_2
P5_1
P5_0
P4_7
P4_6
P4_5
P4_4
P4_3
P4_2
Note:
1.
There are pins CTX1 and CRX1 only in the M16C/5M Group.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 16 of 156
M16C/5M Group, M16C/57 Group
Table 1.12
Pin
No.
1. Overview
Pin Names, 100-Pin Package(2/2)
Control
Pin
Port
Interrupt
Pin
Timer Pin
UART/CAN/LIN/Serial
Bus Interface Pin
Timer S Pin
51
52
53
54
55
56
57
P4_1
P4_0
P3_7
P3_6
P3_5
P3_4
P3_3
CTS3/RTS3/SCS0
58
59
60
61
P3_2
P3_1
TXD3/SSO0
RXD3/SSI0
P3_0
CLK3/SSCK0
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
Multimaster I2C- Analog Pin
bus Pin
VCC
VSS
P2_7
P2_6
P2_5
P2_4
P2_3
P2_2
P2_1
P2_0
P1_7
P1_6
P1_5
P1_4
P1_3
P1_2
P1_1
P1_0
P0_7
P0_6
P0_5
P0_4
P0_3
P0_2
P0_1
P0_0
P10_7
P10_6
P10_5
P10_4
P10_3
P10_2
P10_1
INT7
INT6
INT5
INT4
INT3
IDU
IDW
IDV
OUTC1_7/INPC1_7
OUTC1_6/INPC1_6
OUTC1_5/INPC1_5
OUTC1_4/INPC1_4
OUTC1_3/INPC1_3
OUTC1_2/INPC1_2
OUTC1_1/INPC1_1
OUTC1_0/INPC1_0
INPC1_7
SCLMM
SDAMM
ADTRG
AN2_3
AN2_2
AN2_1
AN2_0
AN0_7
AN0_6
AN0_5
AN0_4
AN0_3
AN0_2
AN0_1
AN0_0
AN_7
AN_6
AN_5
AN_4
AN_3
AN_2
AN_1
KI3
KI2
KI1
KI0
AVSS
P10_0
AN_0
VREF
AVCC
99
P9_7
P9_6
100
P9_5
RXD4
TXD4/CTX0 (1)
CLK4/CRX0 (1)
AN2_7
AN2_6
AN2_5
Note:
1.
Pins CTX0 and CRX0 are only available in the M16C/5M Group.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 17 of 156
1. Overview
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
61
40
62
39
63
38
64
37
65
36
M16C/5M Group
M16C/57 Group
66
67
68
69
35
34
33
32
70
31
71
30
PLQP0080KB-A
(80P6Q-A)
(Top view)
72
73
74
75
76
29
28
27
26
25
20
19
18
17
16
15
14
13
12
11
10
9
8
7
P6_3 / TXD0
P3_0 / CLK3 / SSCK0
P3_1 / RXD3 / SSI0
P3_2 / TXD3 / SSO0
P3_3 / CTS3 / RTS3 / SCS0
P3_4
P3_5
P3_6
P3_7
P6_4 / CTS1 / RTS1
P6_5 / CLK1
P6_6 / RXD1
P6_7 / TXD1
P7_0 / TXD2 / SDA2 / TA0OUT / CTS1 / RTS1
P7_1 / RXD2 / SCL2 / TA0IN / CLK1
P7_2 / CLK2 / TA1OUT / V / RXD1
P7_3 / CTS2 / RTS2 / TA1IN / V / TXD1
P7_4 / TA2OUT / W / LIN0OUT
P7_5 / TA2IN / W / LIN0IN
P7_6 / TA3OUT / CTX1 (1)
P9_5 / AN2_5/ CLK4
P9_3 / AN2_4 /CTX0 (1)
P9_2 / AN3_2 / TB2IN / CRX0 (1)
P9_1 / AN3_1 / TB1IN / DA0
P9_0 / AN3_0 / TB0IN / CLKOUT
CNVSS
P8_7 / XCIN
P8_6 / XCOUT
RESET
XOUT
VSS
XIN
VCC
P8_5 / NMI / SD
P8_4 / INT2 / ZP
P8_3 / INT1
P8_2 / INT0
P8_1 / TA4IN / U/ TSUDB
P8_0 / TA4OUT / U/ TSUDA
P7_7 / TA3IN / CRX1 (1)
6
21
5
22
80
4
23
79
3
24
78
2
77
1
P0_6 / AN0_6
P0_5 / AN0_5
P0_4 / AN0_4
P0_3 / AN0_3
P0_2 / AN0_2
P0_1 / AN0_1
P0_0 / AN0_0
P10_7 / AN_7 / KI3
P10_6 / AN_6 / KI2
P10_5 / AN_5 / KI1
P10_4 / AN_4 / KI0
P10_3 / AN_3
P10_2 / AN_2
P10_1 / AN_1
AVSS
P10_0 / AN_0
VREF
AVCC
P9_7 / AN2_7 / RXD4
P9_6 / AN2_6 / TXD4
59
60
P0_7 / AN0_7
P1_0 / AN2_0
P1_1 / AN2_1
P1_2 / AN2_2
P1_3 / AN2_3
P1_4
P1_5 / INT3 / ADTRG / IDV
P1_6 / INT4 / IDW
P1_7 / INT5 / INPC1_7 / IDU
P2_0 / OUTC1_0 / INPC1_0 / SDAMM
P2_1 / OUTC1_1 / INPC1_1 / SCLMM
P2_2 / OUTC1_2 / INPC1_2
P2_3 / OUTC1_3 / INPC1_3
P2_4 / OUTC1_4 / INPC1_4
P2_5 / OUTC1_5 / INPC1_5
P2_6 / OUTC1_6 / INPC1_6
P2_7 / OUTC1_7 / INPC1_7
P6_0 / RTCOUT / CTS0 / RTS0
P6_1 / CLK0
P6_2 / RXD0
M16C/5M Group, M16C/57 Group
Note:
1. Pins CTX0, CRX0, CTX1, and CRX1 are only available in the M16C/5M Group.
Figure 1.7
Pin Assignment for 80-Pin Package (Top View)
Set bits PACR2 to PACR0 in the PACR register to 011b before signals are input or output to individual
pins after reset. When the PACR register is not set, signals are not input or output for some of the pins.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 18 of 156
M16C/5M Group, M16C/57 Group
Table 1.13
Pin
No.
Control
pin
1. Overview
Pin Names, 80-Pin Package (1/2)
Port
Interrupt
Pin
Timer Pin
Timer S Pin
UART/CAN/LIN/Serial
Bus Interface Pin
Multimaster
I2C-bus
pin
Analog Pin
1
P9_5
CLK4
AN2_5
2
P9_3
CTX0 (1)
AN2_4
3
P9_2
TB2IN
CRX0 (1)
AN3_2
P9_1
TB1IN
AN3_1/
DA0
CLKOUT P9_0
TB0IN
AN3_0
4
5
6
CNVSS
7
XCIN
P8_7
8
XCOUT
P8_6
9
RESET
10 XOUT
11 VSS
12 XIN
13 VCC
14
P8_5
NMI
SD
15
P8_4
INT2
ZP
16
P8_3
INT1
17
P8_2
INT0
18
P8_1
TA4IN/U
TSUDB
19
P8_0
TA4OUT/U
TSUDA
20
P7_7
TA3IN
CRX1 (1)
21
P7_6
TA3OUT
CTX1 (1)
22
P7_5
TA2IN/W
LIN0IN
23
P7_4
TA2OUT/W
LIN0OUT
24
P7_3
TA1IN/V
CTS2/RTS2/TXD1
25
P7_2
TA1OUT/V
CLK2/RXD1
26
P7_1
TA0IN
RXD2/SCL2/CLK1
27
P7_0
TA0OUT
TXD2/SDA2/CTS1/RTS1
28
P6_7
TXD1
29
P6_6
RXD1
30
P6_5
CLK1
31
P6_4
CTS1/RTS1
32
P3_7
33
P3_6
34
P3_5
35
P3_4
36
P3_3
CTS3/RTS3/SCS0
37
P3_2
TXD3/SSO0
38
P3_1
RXD3/SSI0
39
P3_0
CLK3/SSCK0
40
P6_3
TXD0
Note:
1. Pins CTX0, CRX0, CTX1 and CRX1 are only available in the M16C/5M Group.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 19 of 156
M16C/5M Group, M16C/57 Group
Table 1.14
Pin
No.
Control
pin
1. Overview
Pin Names, 80-Pin Package (2/2)
Port
Interrupt
Pin
Timer Pin
Timer S Pin
UART/CAN/LIN/Serial
Bus Interface Pin
Multimaster
I2C-bus
pin
Analog Pin
41
P6_2
RXD0
42
P6_1
CLK0
43
P6_0
44
P2_7
OUTC1_7/INPC1_7
45
P2_6
OUTC1_6/INPC1_6
46
P2_5
OUTC1_5/INPC1_5
47
P2_4
OUTC1_4/INPC1_4
48
P2_3
OUTC1_3/INPC1_3
49
P2_2
OUTC1_2/INPC1_2
50
P2_1
OUTC1_1/INPC1_1
SCLMM
51
P2_0
OUTC1_0/INPC1_0
SDAMM
52
P1_7
INT5
IDU
53
P1_6
INT4
IDW
54
P1_5
INT3
IDV
55
P1_4
56
P1_3
AN2_3
57
P1_2
AN2_2
58
P1_1
AN2_1
59
P1_0
AN2_0
60
P0_7
AN0_7
61
P0_6
AN0_6
62
P0_5
AN0_5
63
P0_4
AN0_4
64
P0_3
AN0_3
65
P0_2
AN0_2
66
P0_1
AN0_1
67
P0_0
AN0_0
68
P10_7 KI3
AN_7
69
P10_6 KI2
AN_6
70
P10_5 KI1
AN_5
71
P10_4 KI0
AN_4
72
P10_3
AN_3
73
P10_2
AN_2
74
P10_1
AN_1
P10_0
AN_0
CTS0/RTS0
RTCOUT
INPC1_7
ADTRG
75 AVSS
76
77 VREF
78 AVCC
79
P9_7
RXD4
AN2_7
80
P9_6
TXD4
AN2_6
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1. Overview
33
34
35
36
37
38
39
40
41
42
43
44
45
46
49
32
50
31
51
30
M16C/5M Group
M16C/57 Group
52
53
54
55
29
28
27
26
56
25
PLQP0064KB-A
(64P6Q-A)
(Top view)
57
58
59
60
61
62
24
23
22
21
20
19
16
15
14
13
12
11
10
9
8
7
6
5
P3_0 / CLK3 / SSCK0
P3_1 / RXD3 / SSI0
P3_2 / TXD3 / SSO0
P3_3 / CTS3 / RTS3 / SCS0
P6_4 / RTS1 / CTS1
P6_5 / CLK1
P6_6 / RXD1
P6_7 / TXD1
P7_0 / TXD2 / SDA2 / TA0OUT / CTS1 / RTS1
P7_1 / RXD2 / SCL2 / TA0IN / CLK1
P7_2 / CLK2 / TA1OUT / V / RXD1
P7_3 / CTS2 / RTS2 / TA1IN / V / TXD1
P7_4 / TA2OUT / W / LIN0OUT
P7_5 / TA2IN / W / LIN0IN
P7_6 / TA3OUT / CTX1 (1)
P7_7 / TA3IN / CRX1 (1)
P9_1 / AN3_1 / TB1IN / DA0
P9_0 / AN3_0 / TB0IN / CLKOUT
CNVSS
P8_7 / XCIN
P8_6 / XCOUT
RESET
XOUT
VSS
XIN
VCC
P8_5 / NMI / SD
P8_4 / INT2 / ZP
P8_3 / INT1
P8_2 / INT0
P8_1 / TA4IN / U / TSUDB
P8_0 / TA4OUT / U / TSUDA
4
17
3
18
64
2
63
1
P0_2 / AN0_2
P0_1 / AN0_1
P0_0 / AN0_0
P10_7 / AN_7 / KI3
P10_6 / AN_6 / KI2
P10_5 / AN_5 / KI1
P10_4 / AN_4 / KI0
P10_3 / AN_3
P10_2 / AN_2
P10_1 / AN_1
AVSS
P10_0 / AN_0
VREF
AVCC
P9_3 / AN2_4 /CTX0 (1)
P9_2 / AN3_2 / TB2IN / CRX0 (1)
47
48
P0_3 / AN0_3
P1_5 / INT3 / ADTRG / IDV
P1_6 / INT4 / IDW
P1_7 / INT5 / INPC1_7 / IDU
P2_0 / OUTC1_0 / INPC1_0 / SDAMM
P2_1 / OUTC1_1 / INPC1_1 / SCLMM
P2_2 / OUTC1_2 / INPC1_2
P2_3 / OUTC1_3 / INPC1_3
P2_4 / OUTC1_4 / INPC1_4
P2_5 / OUTC1_5 / INPC1_5
P2_6 / OUTC1_6 / INPC1_6
P2_7 / OUTC1_7 / INPC1_7
P6_0 / RTCOUT / CTS0 / RTS0
P6_1 / CLK0
P6_2 / RXD0
P6_3 / TXD0
M16C/5M Group, M16C/57 Group
Note:
1. Pins CTX0, CRX0, CTX1, and CRX1 are only available in the M16C/5M Group.
Figure 1.8
Pin Assignments for 64-Pin Package (Top View)
Set bits PACR2 to PACR0 in the PACR register to 010b before signals are input or output to individual
pins after reset. When the PACR register is not set, signals are not input or output for some of the pins.
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Table 1.15
Pin
No.
Control
pin
1
1. Overview
Pin Names, 64-Pin Package (1/2)
Port
Interrupt
Pin
Timer Pin
Timer S Pin
UART/CAN/LIN/Serial
Bus Interface Pin
Multimaster
I2C-bus
Pin
Analog Pin
P9_1
TB1IN
AN3_1/
DA0
TB0IN
AN3_0
2
CLKOUT P9_0
3
CNVSS
4
XCIN
P8_7
5
XCOUT
P8_6
6
RESET
7
XOUT
8
VSS
9
XIN
10 VCC
11
P8_5
NMI
SD
12
P8_4
INT2
ZP
13
P8_3
INT1
14
P8_2
INT0
15
P8_1
TA4IN/U
TSUDB
16
P8_0
TA4OUT/U
TSUDA
17
P7_7
TA3IN
CRX1 (1)
18
P7_6
TA3OUT
CTX1 (1)
19
P7_5
TA2IN/W
LIN0IN
20
P7_4
TA2OUT/W
LIN0OUT
21
P7_3
TA1IN/V
CTS2/RTS2/TXD1
22
P7_2
TA1OUT/V
CLK2/RXD1
23
P7_1
TA0IN
RXD2/SCL2/CLK1
24
P7_0
TA0OUT
TXD2/SDA2/CTS1/RTS1
25
P6_7
TXD1
26
P6_6
RXD1
27
P6_5
CLK1
28
P6_4
CTS1/RTS1
29
P3_3
CTS3/RTS3 / SCS0
30
P3_2
TXD3 / SSO0
Note:
1.
Pins CTX1 and CRX1 are only available in the M16C/5M Group.
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Table 1.16
Pin
No.
Control
pin
1. Overview
Pin Names, 64-Pin Package (2/2)
Port
Interrupt
Pin
Timer Pin
Timer S Pin
UART/CAN/LIN/Serial
Bus Interface Pin
31
P3_1
RXD3 / SSI0
32
P3_0
CLK3 / SSCK0
33
P6_3
TXD0
34
P6_2
RXD0
35
P6_1
36
P6_0
37
P2_7
OUTC1_7/INPC1_7
38
P2_6
OUTC1_6/INPC1_6
39
P2_5
OUTC1_5/INPC1_5
40
P2_4
OUTC1_4/INPC1_4
41
P2_3
OUTC1_3/INPC1_3
42
P2_2
OUTC1_2/INPC1_2
Multimaster
I2C-bus
pin
Analog Pin
CLK0
CTS0/RTS0
RTCOUT
43
P2_1
OUTC1_1/INPC1_1
SCLMM
44
P2_0
OUTC1_0/INPC1_0
SDAMM
45
P1_7
INT5
IDU
46
P1_6
INT4
IDW
47
P1_5
INT3
IDV
48
P0_3
AN0_3
49
P0_2
AN0_2
50
P0_1
AN0_1
51
P0_0
AN0_0
52
P10_7 KI3
AN_7
53
P10_6 KI2
AN_6
54
P10_5 KI1
AN_5
55
P10_4 KI0
AN_4
56
P10_3
AN_3
57
P10_2
AN_2
58
P10_1
AN_1
P10_0
AN_0
INPC1_7
ADTRG
59 AVSS
60
61 VREF
62 AVCC
63
P9_3
64
P9_2
TB2IN
CTX0 (1)
AN2_4
CRX0 (1)
AN3_2
Note:
1. Pins CTX0 and CRX0 are only available in the M16C/5M Group.
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1.6
1. Overview
Pin Functions
Table 1.17
Pin Functions (64-Pin, 80-Pin, and 100-Pin Packages)
Signal Name
Pin Name
I/O
Description
Power supply
VCC, VSS
I
Apply 3.0 V to 5.5 V to the VCC pin and 0 V to the VSS pin.
Analog power
supply
AVCC,
AVSS
I
Power supply for the A/D converter and D/A converter. Pins
AVCC and AVSS should be connected to VCC and VSS,
respectively.
Reset input
RESET
I
Driving this pin low resets the MCU.
CNVSS
CNVSS
I
Main clock input
XIN
Main clock output
XOUT
O
Sub clock input
XCIN
I
Sub clock output
XCOUT
O
Clock output
CLKOUT
O
This pin outputs the clock having the same frequency as f1, f8,
f32, or fC.
INT interrupt input
INT0 to INT5
I
Input for INT interrupt
NMI input
NMI
I
Input for NMI
Key input interrupt
KI0 to KI3
I
Input for the key input interrupt
TA0OUT to
TA4OUT
I/O
Timer A
Timer B
I
Connect to VSS via a resistor.
Input/output for the main clock oscillator. Connect a ceramic
resonator or crystal oscillator between XIN and XOUT. (1)
To apply an external clock, connect it to XIN and leave XOUT
open. When XIN is not used, connect XIN to VCC pin and leave
XOUT open.
Input/output for the sub clock oscillator. Connect a crystal
oscillator between XCIN and XCOUT. (1)
Timers A0 to A4 input/output
TA0IN to TA4IN
I
Timers A0 to A4 input
ZP
I
Input for Z-phase
I
Timers B0 to B2 input
Three-phase motor U,U,V,V,W,W
control timer
IDU, IDW, IDV, SD
O
Output for three-phase motor control timer
I
Input for three-phase motor control timer
Real-time clock
O
Output for real-time clock
CTS0 to CTS3
I
Input to control data transmission
RTS0 to RTS3
O
Output to control data reception
CLK0 to CLK3
I/O
Transfer clock input/output
RXD0 to RXD3
I
Serial interface
UART0 to UART3
TB0IN to TB2IN
RTCOUT
Serial data input
TXD0 to TXD3
O
Serial data output
UART2
I2C mode
SDA2
I/O
Serial data input/output
SCL2
I/O
Transfer clock input/output
Multi-master I2C
bus
SDAMM
SCLMM
I/O
Serial data input/output
Transfer clock input/output
Note:
1. Please contact the oscillator manufacturer for oscillation characteristic.
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Table 1.18
1. Overview
Pin Functions (64-Pin, 80-Pin, and 100-Pin Packages)
Signal Name
Reference voltage
input
A/D converter
Timer S
CAN Module (1)
D/A converter
LIN module
Serial bus interface
Pin Name
I/O
Description
VREF
I
Reference voltage input for the A/D converter and D/A converter.
AN_0 to AN_7
AN0_0 to AN0_3
AN3_0 to AN3_2
I
Analog input
ADTRG
I
Input for an external trigger
INPC1_0 to INPC1_7
I
Input for time measurement function
OUTC1_0 to OUTC1_7
O
Output for waveform generating function
TSUDA, TSUDB
I
Two-phase pulse input
CRX0, CRX1
I
Receive data input for CAN communication
CTX0, CTX1
O
Transmit data output for CAN communication
DA0
O
Output for the D/A converter
LIN0OUT
O
Transmit data output for LIN communication
LIN0IN
I
Receive data input for LIN communication
SSO0
O
Serial data output
SSI0
SSCK0
SCS0
I/O port
P0_0 to P0_3
P1_5 to P1_7
P2_0 to P2_7
P3_0 to P3_3
P6_0 to P6_7
P7_0 to P7_7
P8_0 to P8_7
P9_0 to P9_3
P10_0 to P10_7
I
I/O
I
I/O
Serial data input
Input/output for transmit/receive clock
Input to control the serial interface
CMOS I/O ports. A direction register determines whether each
pin is used as an input port or an output port. For input ports,
pull-up resistor is selectable for every unit of 4 bits.
However, P8_5 output is N-channel open drain output and does
not have a pull-up resistor.
Port P8_5 shares the pin with NMI, so that the NMI input level
can be read from the P8 register P8_5 bit.
Note:
1.
There is the CAN module only in the M16C/5M Group.
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Table 1.19
1. Overview
Pin Functions (100-Pin Package Only)
Signal Name
Pin Name
I/O
Description
INT interrupt input
INT6 and INT7
I
Input for INT interrupt
Timer B
TB3IN to TB5IN
I
Timers B3 to B5 input
I/O port
P4_0 to P4_7
P5_0 to P5_7
P9_4
Table 1.20
pull-up resistor is selectable for every unit of 4 bits.
Pin Functions (80-Pin and 64-Pin Package Only)
Signal Name
A/D converter
Table 1.21
CMOS I/O ports. A direction register determines whether each
I/O pin is used as an input port or an output port. For input ports,
Pin Name
AN2_4
I/O
I
Description
Analog input
Pin Functions (100-Pin and 80-Pin Package Only)
Signal Name
Pin Name
CLK4
Serial Interface
UART4
I/O
Description
I/O Transfer clock input/output
RXD4
I
Serial data input
TXD4
O
Serial data output
A/D converter
AN0_4 to AN0_7
AN2_0 to AN2_3
AN2_5 to AN2_7
I
Analog input
I/O port
P0_4 to P0_7
P1_0 to P1_4
P3_4 to P3_7
P9_5 to P9_7
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CMOS I/O ports. A direction register determines whether each
I/O pin is used as an input port or an output port. For input ports,
Pull-up resistor is selectable for every unit of 4 bits.
Page 26 of 156
M16C/5M Group, M16C/57 Group
2.
2. Central Processing Unit (CPU)
Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. Seven registers (R0, R1, R2, R3, A0, A1, and FB) out of 13 compose a
register bank, and there are two register banks.
b31
b15
b8 b7
b0
R2
R0H (upper bits of R0)
R0L (lower bits of R0)
R3
R1H (upper bits of R1)
R1L (lower bits of R1)
Data registers (1)
R2
R3
A0
Address registers (1)
A1
FB
b19
Frame base registers (1)
b15
b0
INTBH
Interrupt table register
INTBL
INTBH is the 4 upper bits of the INTB register and INTBL
is the 16 lower bits.
b19
b0
PC
Program counter
b15
b0
USP
User stack pointer
ISP
Interrupt stack pointer
SB
Static base register
b15
b0
FLG
b15
b8
IPL
Flag register
b7
U
b0
I
O B
S
Z
D
C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Note:
1. These registers compose a register bank. There are two register banks.
Figure 2.1
CPU Registers
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2.1
2. Central Processing Unit (CPU)
Data Registers (R0, R1, R2, and R3)
R0, R1, R2, and R3 are 16-bit registers used for transfer, arithmetic, and logic operations. R0 and R1 can
be split into upper (R0H/R1H) and lower (R0L/R1L) bits to be used separately as 8-bit data registers.
R0 can be combined with R2, and R3 can be combined with R1 and be used as 32-bit data registers
R2R0 and R3R1, respectively.
2.2
Address Registers (A0 and A1)
A0 and A1 are 16-bit registers used for indirect addressing, relative addressing, transfer, arithmetic, and
logic operations. A0 can be combined with A1 and used as a 32-bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is a 16-bit register that is used for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the start address of a relocatable interrupt vector table.
2.5
Program Counter (PC)
The PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The USP and ISP stack pointers (SP) are each comprised of 16 bits. The U flag is used to switch between
USP and ISP.
2.7
Static Base Register (SB)
SB is a 16-bit register used for SB relative addressing.
2.8
Flag Register (FLG)
FLG is an 11-bit register that indicates the CPU state.
2.8.1
Carry Flag (C Flag)
The C flag retains a carry, borrow, or shift-out bit generated by the arithmetic/logic unit.
2.8.2
Debug Flag (D Flag)
The D flag is for debugging only. Set it to 0.
2.8.3
Zero Flag (Z Flag)
The Z flag becomes 1 when an arithmetic operation results in 0. Otherwise, it becomes 0.
2.8.4
Sign Flag (S Flag)
The S flag becomes 1 when an arithmetic operation results in a negative value. Otherwise, it becomes
0.
2.8.5
Register Bank Select Flag (B Flag)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is 1.
2.8.6
Overflow Flag (O Flag)
The O flag becomes 1 when an arithmetic operation results in an overflow. Otherwise, it becomes 0.
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M16C/5M Group, M16C/57 Group
2.8.7
2. Central Processing Unit (CPU)
Interrupt Enable Flag (I Flag)
The I flag enables maskable interrupts.
Maskable interrupts are disabled when the I flag is 0, and enabled when it is 1. The I flag becomes 0
when an interrupt request is accepted.
2.8.8
Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is 0. USP is selected when the U flag is 1.
The U flag becomes 0 when a hardware interrupt request is accepted, or the INT instruction of software
interrupt number 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from 0 to 7.
If a requested interrupt has higher priority than IPL, the interrupt request is enabled.
2.8.10
Reserved Areas
Only set these bits to 0. The read value is undefined.
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3.
3. Memory
Memory
Special function registers (SFRs) are allocated from address 00000h to 003FFh and from 0D000h to
0D7FFh. Peripheral function control registers are located here. All blank spaces within SFRs are reserved,
so do not access any blank spaces.
The internal RAM is allocated from address 00400h to superior direction. For example, a 8-Kbyte internal
RAM is addressed from 00400h to 023FFh. The internal RAM is used not only for data storage but also for
stack area when subroutines are called or when interrupt request are acknowledged.
The internal ROM is flash memory. Four internal ROM areas are available: E 2 dataFlash, data flash,
program ROM 1, and program ROM 2.
The data flash is addressed from 0E000h to 0FFFFh. This data flash space is used not only for data storage
but also for program storage.
Program ROM 2 is assigned addresses 10000h to 13FFFh. Program ROM 1 is assigned addresses
FFFFFh to inferior direction. For example, the 64-Kbyte program ROM 1 space has addresses F0000h to
FFFFFh.
The E2dataFlash is not shown in the memory map because the E2FA register value is used as an address.
The E2dataFlash cannot be used for program storage. Whether the E2dataFlash is provided or not depends
on the product.
The special page vectors are assigned addresses FFE00h to FFFD7h. They are used for the JMPS
instruction and JSRS instruction. Refer to the M16C/60, M16C/20, M16C/Tiny Series Software Manual for
details.
The fixed vector table for interrupts, ID code write address, OFS1 address and OSF2 address are assigned
addresses FFFDBh to FFFFFh.
The 256 bytes beginning with the start address set in the INTB register compose the relocatable vector table
for interrupts.
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M16C/5M Group, M16C/57 Group
3. Memory
00000h
SFRs
00400h
Internal RAM
Relocatable vector table
256 bytes beginning with the start
address set in the INTB register
XXXXXh
Reserved (1)
Internal RAM
Capacity
XXXXXh
8 Kbytes
023FFh
12 Kbytes
033FFh
20 Kbytes
053FFh
0D000h
SFRs
0D800h
Reserved (1)
0E000h
Internal ROM
(Data flash)
10000h
Internal ROM
(Program ROM 2)
13000h
On-chip debugger
monitor area
13FF0h
User boot code area
13FFFh
14000h
Reserved (1)
Internal ROM
Capacity
YYYYYh
96 Kbytes
E8000h
128 Kbytes
E0000h
256 Kbytes
C0000h
YYYYYh
FFE00h
Special page vector
table
FFFD8h
Reserved (2)
FFFDBh
Fixed vector table
ID code write address
OFS1 address
OSF2 address
Internal ROM
(Program ROM 1)
FFFFFh
FFFFFh
The above assumes the following:
-The PM10 bit in the PM1 register is set to 1 (addresses from 0E000h to 0FFFFh are used as data flash)
-The PRG2C0 bit in the PRG2C register is set to 0 (program ROM 2 enabled)
Notes:
1. Do not access these reserved areas.
2. Do not change the data from FFh.
Figure 3.1
Memory Map
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M16C/5M Group, M16C/57 Group
4.
4. Special Function Registers (SFRs)
Special Function Registers (SFRs)
4.1
SFRs
An SFR is a control register for a peripheral function.
Table 4.1
Address
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
SFR Information (1) (1)
Register
Processor Mode Register 0
Processor Mode Register 1
System Clock Control Register 0
System Clock Control Register 1
Protect Register
Oscillation Stop Detection Register
Symbol
Reset Value
PM0
PM1
CM0
CM1
0000 1000b
0100 1000b
0010 0000b
PRCR
00h
CM2
00h
0X00 0010b (3)
Program 2 Area Control Register
PRG2C
XXXX XX00b
Peripheral Clock Select Register
PCLKR
0000 0011b
Clock Prescaler Reset Flag
CPSRF
0XXX XXXXb
0018h
Reset Source Determine Register
RSTFR
0019h
Voltage Detector 2 Flag Register
VCR1
001Ah
Voltage Detector Operation Enable Register
VCR2
000X 0000b (2, 5)
001X 0000b (2, 6)
PLL Control Register 0
PLC0
0X01 X010b
Processor Mode Register 2
PM2
XX00 0X01b
001Bh
001Ch
001Dh
001Eh
001Fh
XX0X 001Xb
(hardware reset) (4)
0000 1000b (2)
X: Undefined
Notes:
1.
The blank areas are reserved. No access is allowed.
2.
Software reset, watchdog timer reset, oscillator stop detect reset, and voltage monitor 2 reset do not affect the
following registers: the VCR1 register and the VCR2 register.
3.
Oscillator stop detect reset does not affect bits CM20, CM21, and CM27.
4.
The state of bits in the RSTFR register depends on the reset type.
5.
This is the reset value when the LVDAS bit of the OFS1 address is 1 during hardware reset.
6.
This is the reset value after voltage monitor 0 reset, power-on reset, or when the LVDAS bit of the OFS1 address is 0
during hardware reset.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 32 of 156
M16C/5M Group, M16C/57 Group
Table 4.2
Address
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
4. Special Function Registers (SFRs)
SFR Information (2) (1)
Register
Symbol
Reset Value
40 MHz On-Chip Oscillator Control Register 0
FRA0
XXXX XX00b
40 MHz On-Chip Oscillator Control Register 2
FRA2
0XX0 X000b
Voltage Monitor Function Select Register
VWCE
00h
Voltage Detector 2 Level Select Register
VD2LS
0000 0100b
Voltage Monitor 0 Control Register
VW0C
1100 1X10b (3, 4)
1100 1X11b (3, 5)
Voltage Monitor 2 Control Register
VW2C
1000 0X10b (3, 6)
(2)
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
X: Undefined
Notes:
1.
The blank areas are reserved. No access is allowed.
2.
Hardware reset, power-on reset, voltage monitor 0 reset, or voltage monitor 2 reset.
3.
Software reset, watchdog timer reset, oscillator stop detect reset, and voltage monitor 2 reset do not affect the
following registers or bit: the VW0C register, and bits VW2C2 and VW2C3 in the VW2C register.
4.
This is the reset value when the LVDAS bit of the OFS1 address is 1 during hardware reset
5.
This is the reset value after voltage monitor 0 reset, power-on reset, or when the LVDAS bit of the OFS1 address is 0
during hardware reset.
6.
This is the reset value after hardware reset, power-on reset, or voltage monitor 0 reset
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 33 of 156
M16C/5M Group, M16C/57 Group
Table 4.3
4. Special Function Registers (SFRs)
SFR Information (3) (1)
Address
0040h
Register
Symbol
Reset Value
0041h
E2dataFlash Interrupt Control Register
E2FIC
XXXX X000b
0042h
INT7 Interrupt Control Register
Serial Bus Interface 0 Interrupt Control Register
INT7IC
SS0IC
XX00 X000b
0043h
INT6 Interrupt Control Register
LIN0 Interrupt Control Register
INT6IC
LIN0IC
XX00 X000b
0044h
0045h
INT3 Interrupt Control Register
Timer B5 Interrupt Control Register
INT3IC
TB5IC
XX00 X000b
XXXX X000b
0046h
Timer B4 Interrupt Control Register
TB4IC
XXXX X000b
0047h
Timer B3 Interrupt Control Register
TB3IC
XXXX X000b
0048h
INT5 Interrupt Control Register
INT5IC
XX00 X000b
0049h
INT4IC
BCNIC
TMOSIC
DM0IC
XX00 X000b
XXXX X000b
004Bh
INT4 Interrupt Control Register
UART2 Bus Collision Detection Interrupt Control Register
Task Monitoring Timer Interrupt Control Register
DMA0 Interrupt Control Register
004Ch
DMA1 Interrupt Control Register
DM1IC
XXXX X000b
004Dh
Key Input Interrupt Control Register
KUPIC
XXXX X000b
004Eh
A/D Conversion Interrupt Control Register
ADIC
XXXX X000b
004Fh
UART2 Transmit Interrupt Control Register
S2TIC
XXXX X000b
0050h
S2RIC
S0TIC
L0WIC
S0RIC
XXXX X000b
XXXX X000b
0052h
UART2 Receive Interrupt Control Register
UART0 Transmit Interrupt Control Register
LIN0 Low Detection Interrupt Control Register
UART0 Receive Interrupt Control Register
0053h
UART1 Transmit Interrupt Control Register
S1TIC
XXXX X000b
0054h
UART1 Receive Interrupt Control Register
S1RIC
XXXX X000b
0055h
Timer A0 Interrupt Control Register
TA0IC
XXXX X000b
0056h
Timer A1 Interrupt Control Register
TA1IC
XXXX X000b
0057h
Timer A2 Interrupt Control Register
TA2IC
XXXX X000b
0058h
Timer A3 Interrupt Control Register
TA3IC
XXXX X000b
0059h
Timer A4 Interrupt Control Register
TA4IC
XXXX X000b
005Ah
Timer B0 Interrupt Control Register
TB0IC
XXXX X000b
004Ah
0051h
XXXX X000b
XXXX X000b
005Bh
Timer B1 Interrupt Control Register
TB1IC
XXXX X000b
005Ch
Timer B2 Interrupt Control Register
TB2IC
XXXX X000b
005Dh
INT0 Interrupt Control Register
INT0IC
XX00 X000b
005Eh
INT1 Interrupt Control Register
INT1IC
XX00 X000b
005Fh
INT2 Interrupt Control Register
INT2IC
XX00 X000b
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 34 of 156
M16C/5M Group, M16C/57 Group
Table 4.4
Address
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
Note:
1.
4. Special Function Registers (SFRs)
SFR Information (4) (1)
Register
DMA2 Interrupt Control Register
DMA3 Interrupt Control Register
CAN 1 Receive Completion Interrupt Control Register
CAN 1 Transmit Completion Interrupt Control Register
CAN 1 Receive FIFO Interrupt Control Register
CAN 1 Transmit FIFO Interrupt Control Register
UART4 Transmit Interrupt Control Register
Real-Time Clock Compare Interrupt Control Register
UART4 Receive Interrupt Control Register
CAN0 Wakeup Interrupt Control Register
UART3 Transmit Interrupt Control Register
CAN0 Error Interrupt Control Register
UART3 Receive Interrupt Control Register
CAN 1 Wakeup Interrupt Control Register
Real-Time Clock Cycle Interrupt Control Register
CAN 1 Error Interrupt Control Register
CAN0 Receive Completion Interrupt Control Register
CAN0 Transmit Completion Interrupt Control Register
CAN0 Receive FIFO Interrupt Control Register
CAN0 Transmit FIFO Interrupt Control Register
IC/OC Interrupt 0 Control Register
IC/OC Channel 0 Interrupt Control Register
IC/OC Interrupt 1 Control Register
I2C-bus Interface Interrupt Control Register
IC/OC Channel 1 Interrupt Control Register
SCL/SDA Interrupt Control Register
IC/OC Channel 2 Interrupt Control Register
IC/OC Channel 3 Interrupt Control Register
IC/OC Base Timer Interrupt Control Register
Symbol
Reset Value
DM2IC
DM3IC
C1RIC
C1TIC
C1FRIC
C1FTIC
S4TIC
RTCCIC
S4RIC
C0WIC
S3TIC
C0EIC
S3RIC
C1WIC
RTCTIC
C1EIC
C0RIC
C0TIC
C0FRIC
C0FTIC
ICOC0IC
ICOCH0IC
ICOC1IC
IICIC
ICOCH1IC
SCLDAIC
ICOCH2IC
ICOCH3IC
BTIC
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
X: Undefined
The blank areas are reserved. No access is allowed.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 35 of 156
M16C/5M Group, M16C/57 Group
Table 4.5
Address
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h
00A1h
00A2h
00A3h
00A4h
00A5h
00A6h
00A7h
00A8h
00A9h
00AAh
00ABh
00ACh
00ADh
00AEh
00AFh
00B0h to
015Fh
4. Special Function Registers (SFRs)
SFR Information (5) (1)
Register
E2dataFlash Address Register
E2dataFlash Command Register
Symbol
E2FA
E2FI
Reset Value
00h
00h
XXh
XXh
00h
XXh
E2dataFlash Data Register
E2FD
XXh
XXh
E2dataFlash Mode Register
E2FM
00h
E2dataFlash Control Register
E2FC
XXXX XXX0b
E2dataFlash Status Register 1
E2FS1
XXXX XXX0b
E2dataFlash Status Register 0
E2FS0
0X00 XXXXb
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 36 of 156
M16C/5M Group, M16C/57 Group
Table 4.6
Address
0160h
0161h
0162h
0163h
0164h
0165h
0166h
0167h
0168h
0169h
016Ah
016Bh
016Ch
016Dh
016Eh
016Fh
0170h
0171h
0172h
0173h
0174h
0175h
0176h
0177h
0178h
0179h
017Ah
017Bh
017Ch
017Dh
017Eh
017Fh
Note:
1.
4. Special Function Registers (SFRs)
SFR Information (6) (1)
Register
Symbol
Reset Value
LIN Wakeup Baud Rate Select Register
LIN Baud Rate Prescaler 0 Register
LIN Baud Rate Prescaler 1 Register
LIN Self-test Control Register
LIN Port Clock Control Register
LWBR
LBRP0
LBRP1
LSTC
LPC
00h
00h
00h
00h
00h
LIN0 Mode Register
LIN0 Break Field Setting Register
LIN0 Space Width Setting Register
LIN0 Wakeup Setting Register
LIN0 Interrupt Enable Register
LIN0 Error Detection Enable Register
LIN0 Control Register
L0MD
L0BRK
L0SPC
L0WUP
L0IE
L0EDE
L0C
00h
00h
00h
00h
00h
00h
00h
LIN0 Transmit Control Register
LIN0 Mode Status Register
LIN0 Status Register
LIN0 Error Status Register
LIN0 Response Field Setting Register
LIN0 ID Buffer Register
LIN0 Check Sum Buffer Register
L0TC
L0MST
L0ST
L0EST
L0RFC
L0IDB
L0CB
00h
00h
00h
00h
00h
XXh
XXh
LIN0 Data 1 Buffer Register
LIN0 Data 2 Buffer Register
LIN0 Data 3 Buffer Register
LIN0 Data 4 Buffer Register
LIN0 Data 5 Buffer Register
LIN0 Data 6 Buffer Register
LIN0 Data 7 Buffer Register
LIN0 Data 8 Buffer Register
L0DB1
L0DB2
L0DB3
L0DB4
L0DB5
L0DB6
L0DB7
L0DB8
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
X: Undefined
The blank areas are reserved. No access is allowed.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 37 of 156
M16C/5M Group, M16C/57 Group
Table 4.7
Address
0180h
0181h
0182h
0183h
0184h
0185h
0186h
0187h
0188h
0189h
018Ah
018Bh
018Ch
018Dh
018Eh
018Fh
0190h
0191h
0192h
0193h
0194h
0195h
0196h
0197h
0198h
0199h
019Ah
019Bh
019Ch
019Dh
019Eh
019Fh
01A0h
01A1h
01A2h
01A3h
01A4h
01A5h
01A6h
01A7h
01A8h
01A9h
01AAh
01ABh
01ACh
01ADh
01AEh
01AFh
4. Special Function Registers (SFRs)
SFR Information (7) (1)
Register
Symbol
Reset Value
XXh
XXh
0Xh
DMA0 Source Pointer
SAR0
DMA0 Destination Pointer
DAR0
XXh
XXh
0Xh
DMA0 Transfer Counter
TCR0
XXh
XXh
DMA0 Control Register
DM0CON
0000 0X00b
DMA1 Source Pointer
SAR1
XXh
XXh
0Xh
DMA1 Destination Pointer
DAR1
XXh
XXh
0Xh
DMA1 Transfer Counter
TCR1
XXh
XXh
DMA1 Control Register
DM1CON
0000 0X00b
DMA2 Source Pointer
SAR2
XXh
XXh
0Xh
DMA2 Destination Pointer
DAR2
XXh
XXh
0Xh
DMA2 Transfer Counter
TCR2
XXh
XXh
DMA2 Control Register
DM2CON
0000 0X00b
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 38 of 156
M16C/5M Group, M16C/57 Group
Table 4.8
Address
01B0h
01B1h
01B2h
01B3h
01B4h
01B5h
01B6h
01B7h
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01BFh
01C0h
01C1h
01C2h
01C3h
01C4h
01C5h
01C6h
01C7h
01C8h
01C9h
01CAh
01CBh
01CCh
01CDh
01CEh
01CFh
01D0h
01D1h
01D2h
01D3h
01D4h
01D5h
01D6h
01D7h
01D8h
01D9h
01DAh
01DBh
01DCh
01DDh
01DEh
01DFh
4. Special Function Registers (SFRs)
SFR Information (8) (1)
Register
Symbol
Reset Value
XXh
XXh
0Xh
DMA3 Source Pointer
SAR3
DMA3 Destination Pointer
DAR3
XXh
XXh
0Xh
DMA3 Transfer Counter
TCR3
XXh
XXh
DMA3 Control Register
DM3CON
0000 0X00b
Timer B0-1 Register
TB01
Timer B1-1 Register
TB11
Timer B2-1 Register
TB21
Pulse Period/Pulse Width Measurement Mode Function Select
Register 1
XXh
XXh
XXh
XXh
XXh
XXh
PPWFS1
XXXX X000b
TBCS0
TBCS1
00h
X0h
TCKDIVC0
0000 X000b
TACS0
TACS1
TACS2
00h
00h
X0h
PWMFS
TAPOFS
0XX0 X00Xb
XXX0 0000b
Timer A Output Waveform Change Enable Register
TAOW
XXX0 X00Xb
Three-Phase Protect Control Register
TPRC
00h
Timer B Count Source Select Register 0
Timer B Count Source Select Register 1
Timer AB Division Control Register 0
Timer A Count Source Select Register 0
Timer A Count Source Select Register 1
Timer A Count Source Select Register 2
16-bit Pulse Width Modulation Mode Function Select Register
Timer A Waveform Output Function Select Register
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 39 of 156
M16C/5M Group, M16C/57 Group
Table 4.9
SFR Information (9) (1)
Address
01E0h
01E1h
01E2h
01E3h
01E4h
01E5h
01E6h
01E7h
01E8h
01E9h
01EAh
01EBh
01ECh
01EDh
01EEh
01EFh
01F0h
01F1h
01F2h
01F3h
01F4h
01F5h
01F6h
01F7h
01F8h
01F9h
01FAh
01FBh
01FCh
01FDh
01FEh
01FFh
0200h
0201h
0202h
0203h
0204h
0205h
0206h
0207h
0208h
0209h
020Ah
020Bh
020Ch
020Dh
020Eh
020Fh
Note:
1.
4. Special Function Registers (SFRs)
Register
Symbol
Timer B3-1 Register
TB31
Timer B4-1 Register
TB41
Timer B5-1 Register
TB51
Pulse Period/Pulse Width Measurement Mode Function Select Register 2
Reset Value
XXh
XXh
XXh
XXh
XXh
XXh
PPWFS2
XXXX X000b
Timer B Count Source Select Register 2
Timer B Count Source Select Register 3
TBCS2
TBCS3
00h
X0h
Task Monitor Timer Register
TMOS
Task Monitor Timer Count Start Flag
Task Monitor Timer Count Source Select Register
Task Monitor Timer Protect Register
Interrupt Source Select Register 4
Interrupt Source Select Register 3
Interrupt Source Select Register 2
Interrupt Source Select Register
Address Match Interrupt Enable Register
Address Match Interrupt Enable Register 2
TMOSSR
TMOSCS
TMOSPR
XXh
XXh
XXXX XXX0b
XXXX 0000b
00h
IFSR4A
IFSR3A
IFSR2A
IFSR
00h
00h
00h
00h
AIER
AIER2
XXXX XX00b
XXXX XX00b
X: Undefined
The blank areas are reserved. No access is allowed.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 40 of 156
M16C/5M Group, M16C/57 Group
Table 4.10
SFR Information (10) (1)
Address
0210h
0211h
0212h
0213h
0214h
0215h
0216h
0217h
0218h
0219h
021Ah
021Bh
021Ch
021Dh
021Eh
021Fh
4. Special Function Registers (SFRs)
Register
Symbol
Reset Value
00h
00h
X0h
Address Match Interrupt Register 0
RMAD0
Address Match Interrupt Register 1
RMAD1
00h
00h
X0h
Address Match Interrupt Register 2
RMAD2
00h
00h
X0h
Address Match Interrupt Register 3
RMAD3
00h
00h
X0h
0220h
Flash Memory Control Register 0
FMR0
0221h
0222h
0223h
0224h
0225h
0226h
0227h
0228h
0229h
022Ah
022Bh
022Ch
022Dh
022Eh
022Fh
0230h
0231h
0232h
0233h
0234h
0235h
0236h
0237h
0238h
0239h
023Ah
023Bh
023Ch
023Dh
023Eh
023Fh
Flash Memory Control Register 1
Flash Memory Control Register 2
Flash Memory Control Register 3
FMR1
FMR2
FMR3
0000 0001b
(Other than user boot mode)
0010 0001b
(User boot mode)
00X0 XX0Xb
XXXX 0000b
XXXX 0000b
Flash Memory Control Register 6
FMR6
XX0X XX00b
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 41 of 156
M16C/5M Group, M16C/57 Group
Table 4.11
SFR Information (11) (1)
Address
0240h
0241h
0242h
0243h
0244h
0245h
0246h
0247h
0248h
0249h
024Ah
024Bh
024Ch
024Dh
024Eh
024Fh
0250h
0251h
0252h
0253h
0254h
0255h
0256h
0257h
0258h
0259h
025Ah
025Bh
025Ch
025Dh
025Eh
025Fh
0260h
0261h
0262h
0263h
0264h
0265h
0266h
0267h
0268h
0269h
026Ah
026Bh
026Ch
026Dh
026Eh
026Fh
4. Special Function Registers (SFRs)
Register
UART0 Transmit/Receive Mode Register
UART0 Bit Rate Register
Symbol
Reset Value
U0MR
U0BRG
00h
XXh
XXh
XXh
0000 1000b
0000 0010b
XXh
XXh
UART0 Transmit Buffer Register
U0TB
UART0 Transmit/Receive Control Register 0
UART0 Transmit/Receive Control Register 1
U0C0
U0C1
UART0 Receive Buffer Register
U0RB
UART Clock Select Register
UART1 Transmit/Receive Mode Register
UART1 Bit Rate Register
UCLKSEL0
X0h
U1MR
U1BRG
00h
XXh
XXh
XXh
0000 1000b
0000 0010b
XXh
XXh
UART1 Transmit Buffer Register
U1TB
UART1 Transmit/Receive Control Register 0
UART1 Transmit/Receive Control Register 1
U1C0
U1C1
UART1 Receive Buffer Register
U1RB
UART2 Special Mode Register 4
UART2 Special Mode Register 3
UART2 Special Mode Register 2
UART2 Special Mode Register
UART2 Transmit/Receive Mode Register
UART2 Bit Rate Register
U2SMR4
U2SMR3
U2SMR2
U2SMR
U2MR
U2BRG
UART2 Transmit Buffer Register
U2TB
UART2 Transmit/Receive Control Register 0
UART2 Transmit/Receive Control Register 1
U2C0
U2C1
UART2 Receive Buffer Register
U2RB
00h
000X 0X0Xb
X000 0000b
X000 0000b
00h
XXh
XXh
XXh
0000 1000b
0000 0010b
XXh
XXh
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 42 of 156
M16C/5M Group, M16C/57 Group
Table 4.12
SFR Information (12) (1)
Address
0270h
0271h
0272h
0273h
0274h
0275h
0276h
0277h
0278h
0279h
027Ah
027Bh
027Ch
027Dh
027Eh
027Fh
0280h
0281h
0282h
0283h
0284h
0285h
0286h
0287h
0288h
0289h
028Ah
028Bh
028Ch
028Dh
028Eh
028Fh
0290h
0291h
0292h
0293h
0294h
0295h
0296h
0297h
0298h
0299h
029Ah
029Bh
029Ch
029Dh
029Eh
029Fh
Note:
1.
4. Special Function Registers (SFRs)
Register
UART4 Transmit/Receive Mode Register
UART4 Bit Rate Register
Symbol
Reset Value
U4MR
U4BRG
00h
XXh
XXh
XXh
0000 1000b
0000 0010b
XXh
XXh
X: Undefined
UART4 Transmit Buffer Register
U4TB
UART4 Transmit/Receive Control Register 0
UART4 Transmit/Receive Control Register 1
U4C0
U4C1
UART4 Receive Buffer Register
U4RB
The blank areas are reserved. No access is allowed.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 43 of 156
M16C/5M Group, M16C/57 Group
Table 4.13
SFR Information (13) (1)
Address
02A0h
02A1h
02A2h
02A3h
02A4h
02A5h
02A6h
02A7h
02A8h
02A9h
02AAh
02ABh
02ACh
02ADh
02AEh
02AFh
02B0h
02B1h
02B2h
02B3h
02B4h
02B5h
02B6h
02B7h
02B8h
02B9h
02BAh
02BBh
02BCh
02BDh
02BEh
02BFh
02C0h
02C1h
02C2h
02C3h
02C4h
02C5h
02C6h
02C7h
02C8h
02C9h
02CAh
02CBh
02CCh
02CDh
02CEh
02CFh
Note:
1.
4. Special Function Registers (SFRs)
Register
UART3 Transmit/Receive Mode Register
UART3 Bit Rate Register
Symbol
Reset Value
U3MR
U3BRG
S00
00h
XXh
XXh
XXh
0000 1000b
0000 0010b
XXh
XXh
XXh
S0D0
S1D0
S20
S2D0
S3D0
S4D0
S10
S11
S0D1
S0D2
0000 000Xb
00h
00h
0001 1010b
0011 0000b
00h
0001 000Xb
XXXX X000b
0000 000Xb
0000 000Xb
UART3 Transmit Buffer Register
U3TB
UART3 Transmit/Receive Control Register 0
UART3 Transmit/Receive Control Register 1
U3C0
U3C1
UART3 Receive Buffer Register
U3RB
I2C0 Data Shift Register
I2C0 Address Register 0
I2C0 Control Register 0
I2C0 Clock Control Register
I2C0 Start/Stop Condition Control Register
I2C0 Control Register 1
I2C0 Control Register 2
I2C0 Status Register 0
I2C0 Status Register 1
I2C0 Address Register 1
I2C0 Address Register 2
Time Measurement Register 0
Waveform Generation Register 0
Time Measurement Register 1
Waveform Generation Register 1
Time Measurement Register 2
Waveform Generation Register 2
Time Measurement Register 3
Waveform Generation Register 3
Time Measurement Register 4
Waveform Generation Register 4
Time Measurement Register 5
Waveform Generation Register 5
Time Measurement Register 6
Waveform Generation Register 6
Time Measurement Register 7
Waveform Generation Register 7
G1TM0
G1PO0
G1TM1
G1PO1
G1TM2
G1PO2
G1TM3
G1PO3
G1TM4
G1PO4
G1TM5
G1PO5
G1TM6
G1PO6
G1TM7
G1PO7
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
X: Undefined
The blank areas are reserved. No access is allowed.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 44 of 156
M16C/5M Group, M16C/57 Group
Table 4.14
Address
02D0h
02D1h
02D2h
02D3h
02D4h
02D5h
02D6h
02D7h
02D8h
02D9h
02DAh
02DBh
02DCh
02DDh
02DEh
02DFh
02E0h
02E1h
02E2h
02E3h
02E4h
02E5h
02E6h
02E7h
02E8h
02E9h
02EAh
02EBh
02ECh
02EDh
02EEh
02EFh
02F0h
02F1h
02F2h
02F3h
02F4h
02F5h
02F6h
02F7h
02F8h
02F9h
02FAh
02FBh
02FCh
02FDh
02FEh
02FFh
Note:
1.
4. Special Function Registers (SFRs)
SFR Information (14) (1)
Register
Waveform Generation Control Register 0
Waveform Generation Control Register 1
Waveform Generation Control Register 2
Waveform Generation Control Register 3
Waveform Generation Control Register 4
Waveform Generation Control Register 5
Waveform Generation Control Register 6
Waveform Generation Control Register 7
Time Measurement Control Register 0
Time Measurement Control Register 1
Time Measurement Control Register 2
Time Measurement Control Register 3
Time Measurement Control Register 4
Time Measurement Control Register 5
Time Measurement Control Register 6
Time Measurement Control Register 7
G1DV
Reset Value
0X00 XX00b
0X00 XX00b
0X00 XX00b
0X00 XX00b
0X00 XX00b
0X00 XX00b
0X00 XX00b
0X00 XX00b
00h
00h
00h
00h
00h
00h
00h
00h
XXh
XXh
00h
00h
00h
00h
00h
00h
XXh
XXh
00h
Waveform Output Master Enable Register
G1OER
00h
Timer S I/O Control Register 0
Timer S I/O Control Register 1
Interrupt Request Register
Interrupt Enable Register 0
Interrupt Enable Register 1
G1IOR0
G1IOR1
G1IR
G1IE0
G1IE1
00h
00h
XXh
00h
00h
NMI Digital Debounce Register
P1_7 Digital Debounce Register
NDDR
P17DDR
FFh
FFh
X: Undefined
Base Timer Register
Symbol
G1POCR0
G1POCR1
G1POCR2
G1POCR3
G1POCR4
G1POCR5
G1POCR6
G1POCR7
G1TMCR0
G1TMCR1
G1TMCR2
G1TMCR3
G1TMCR4
G1TMCR5
G1TMCR6
G1TMCR7
G1BT
Base Timer Control Register 0
Base Timer Control Register 1
Time Measurement Prescaler Register 6
Time Measurement Prescaler Register 7
Function Enable Register
Function Select Register
G1BCR0
G1BCR1
G1TPR6
G1TPR7
G1FE
G1FS
Base Timer Reset Register
G1BTRR
Count Source Divide Register
The blank areas are reserved. No access is allowed.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 45 of 156
M16C/5M Group, M16C/57 Group
Table 4.15
Address
0300h
0301h
0302h
0303h
0304h
0305h
0306h
0307h
0308h
0309h
030Ah
030Bh
030Ch
030Dh
030Eh
030Fh
0310h
0311h
0312h
0313h
0314h
0315h
0316h
0317h
0318h
0319h
031Ah
031Bh
031Ch
031Dh
031Eh
031Fh
0320h
0321h
0322h
0323h
0324h
0325h
0326h
0327h
0328h
0329h
032Ah
032Bh
032Ch
032Dh
032Eh
032Fh
Note:
1.
4. Special Function Registers (SFRs)
SFR Information (15) (1)
Register
Timer B3/B4/B5 Count Start Flag
Symbol
TBSR
Timer A1-1 Register
TA11
Timer A2-1 Register
TA21
Timer A4-1 Register
TA41
Three-Phase PWM Control Register 0
Three-Phase PWM Control Register 1
Three-Phase Output Buffer Register 0
Three-Phase Output Buffer Register 1
Dead Time Timer
Timer B2 Interrupt Generation Frequency Set Counter
Position-Data-Retain Function Control Register
INVC0
INVC1
IDB0
IDB1
DTT
ICTB2
PDRF
Timer B3 Register
TB3
Timer B4 Register
TB4
Timer B5 Register
TB5
Port Function Control Register
Reset Value
000X XXXXb
XXh
XXh
XXh
XXh
XXh
XXh
00h
00h
XX11 1111b
XX11 1111b
XXh
XXh
XXXX 0000b
XXh
XXh
XXh
XXh
XXh
XXh
PFCR
0011 1111b
Timer B3 Mode Register
Timer B4 Mode Register
Timer B5 Mode Register
TB3MR
TB4MR
TB5MR
00XX 0000b
00XX 0000b
00XX 0000b
Count Start Flag
TABSR
00h
One-Shot Start Flag
Trigger Select Register
Increment/Decrement Flag
ONSF
TRGSR
UDF
00h
00h
00h
Timer A0 Register
TA0
Timer A1 Register
TA1
Timer A2 Register
TA2
Timer A3 Register
TA3
Timer A4 Register
TA4
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
X: Undefined
The blank areas are reserved. No access is allowed.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 46 of 156
M16C/5M Group, M16C/57 Group
Table 4.16
SFR Information (16) (1)
Address
0330h
0331h
0332h
0333h
0334h
0335h
0336h
0337h
0338h
0339h
033Ah
033Bh
033Ch
033Dh
033Eh
033Fh
0340h
0341h
0342h
0343h
0344h
0345h
0346h
0347h
0348h
0349h
034Ah
034Bh
034Ch
034Dh
034Eh
034Fh
0350h
0351h
0352h
0353h
0354h
0355h
0356h
0357h
0358h
0359h
035Ah
035Bh
035Ch
035Dh
035Eh
035Fh
4. Special Function Registers (SFRs)
Register
TA0MR
TA1MR
TA2MR
TA3MR
TA4MR
TB0MR
TB1MR
TB2MR
TB2SC
Reset Value
XXh
XXh
XXh
XXh
XXh
XXh
00h
00h
00h
00h
00h
00XX 0000b
00XX 0000b
00XX 0000b
X000 0000b
RTCSEC
RTCMIN
RTCHR
RTCWK
RTCCR1
RTCCR2
RTCCSR
00h
X000 0000b
XX00 0000b
XXXX X000b
0000 X00Xb
X000 0000b
XXX0 0000b
RTCCSEC
RTCCMIN
RTCCHR
X000 0000b
X000 0000b
X000 0000b
SS0BR
1111 1000b
FFh
FFh
FFh
FFh
00h
0111 1101b
0001 0000b
00h
00h
00h
Symbol
Timer B0 Register
TB0
Timer B1 Register
TB1
Timer B2 Register
TB2
Timer A0 Mode Register
Timer A1 Mode Register
Timer A2 Mode Register
Timer A3 Mode Register
Timer A4 Mode Register
Timer B0 Mode Register
Timer B1 Mode Register
Timer B2 Mode Register
Timer B2 Special Mode Register
Real-Time Clock Second Data Register
Real-Time Clock Minute Data Register
Real-Time Clock Hour Data Register
Real-Time Clock Day Data Register
Real-Time Clock Control Register 1
Real-Time Clock Control Register 2
Real-Time Clock Count Source Select Register
Real-Time Clock Second Compare Data Register
Real-Time Clock Minute Compare Data Register
Real-Time Clock Hour Compare Data Register
SS0 Bit Counter Register
SS0 Transmit Data Register
SS0TDR
SS0 Receive Data Register
SS0RDR
SS0 Control Register H
SS0 Control Register L
SS0 Mode Register
SS0 Enable Register
SS0 Status Register
SS0 Mode Register 2
SS0CRH
SS0CRL
SS0MR
SS0ER
SS0SR
SS0MR2
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 47 of 156
M16C/5M Group, M16C/57 Group
Table 4.17
Address
0360h
0361h
0362h
0363h
0364h
0365h
0366h
0367h
0368h
0369h
036Ah
036Bh
036Ch
036Dh
036Eh
036Fh
0370h
0371h
0372h
0373h
0374h
0375h
0376h
0377h
0378h
0379h
037Ah
037Bh
037Ch
037Dh
037Eh
037Fh
0380h
0381h
0382h
0383h
0384h
0385h
0386h
0387h
0388h
0389h
038Ah
038Bh
038Ch
038Dh
038Eh
038Fh
4. Special Function Registers (SFRs)
SFR Information (17) (1)
Register
Symbol
PUR0
PUR1
PUR2
Reset Value
00h
00h
00h
Port Control Register
PCR
0XX0 0XX0b
Input Threshold Select Register 0
Input Threshold Select Register 1
Input Threshold Select Register 2
VLT0
VLT1
VLT2
00h
00h
XX00 0000b
Pin Assignment Control Register
PACR
0XXX X000b
Count Source Protection Mode Register
Watchdog Timer Refresh Register
Watchdog Timer Start Register
Watchdog Timer Control Register
CSPR
WDTR
WDTS
WDC
00h (2)
XXh
XXh
00XX XXXXb
Pull-Up Control Register 0
Pull-Up Control Register 1
Pull-Up Control Register 2
X: Undefined
Notes:
1.
The blank areas are reserved. No access is allowed.
2.
When the CSPROINI bit in the OFS1 address is 0, the reset value is 10000000b.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 48 of 156
M16C/5M Group, M16C/57 Group
Table 4.18
Address
0390h
0391h
0392h
0393h
0394h
0395h
0396h
0397h
0398h
0399h
039Ah
039Bh
039Ch
039Dh
039Eh
039Fh
03A0h
03A1h
03A2h
03A3h
03A4h
03A5h
03A6h
03A7h
03A8h
03A9h
03AAh
03ABh
03ACh
03ADh
03AEh
03AFh
03B0h
03B1h
03B2h
03B3h
03B4h
03B5h
03B6h
03B7h
03B8h
03B9h
03BAh
03BBh
03BCh
03BDh
03BEh
03BFh
4. Special Function Registers (SFRs)
SFR Information (18) (1)
Register
DMA2 Source Select Register
Symbol
DM2SL
Reset Value
00h
DMA3 Source Select Register
DM3SL
00h
DMA0 Source Select Register
DM0SL
00h
DMA1 Source Select Register
DM1SL
00h
Open-Circuit Detection Assist Function Register
AINRST
XX00 XXXXb
SFR Snoop Address Register
CRCSAR
CRC Mode Register
CRCMR
CRC Data Register
CRCD
CRC Input Register
CRCIN
XXXX XXXXb
00XX XXXXb
0XXX XXX0b
XXh
XXh
XXh
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 49 of 156
M16C/5M Group, M16C/57 Group
Table 4.19
Address
03C0h
03C1h
03C2h
03C3h
03C4h
03C5h
03C6h
03C7h
03C8h
03C9h
03CAh
03CBh
03CCh
03CDh
03CEh
03CFh
03D0h
03D1h
03D2h
03D3h
03D4h
03D5h
03D6h
03D7h
03D8h
03D9h
03DAh
03DBh
03DCh
03DDh
03DEh
03DFh
03E0h
03E1h
03E2h
03E3h
03E4h
03E5h
03E6h
03E7h
03E8h
03E9h
03EAh
03EBh
03ECh
03EDh
03EEh
03EFh
Note:
1.
4. Special Function Registers (SFRs)
SFR Information (19) (1)
Register
Symbol
A/D Register 0
AD0
A/D Register 1
AD1
A/D Register 2
AD2
A/D Register 3
AD3
A/D Register 4
AD4
A/D Register 5
AD5
A/D Register 6
AD6
A/D Register 7
AD7
Reset Value
XXXX XXXXb
0000 00XXb
XXXX XXXXb
0000 00XXb
XXXX XXXXb
0000 00XXb
XXXX XXXXb
0000 00XXb
XXXX XXXXb
0000 00XXb
XXXX XXXXb
0000 00XXb
XXXX XXXXb
0000 00XXb
XXXX XXXXb
0000 00XXb
A/D Control Register 2
ADCON2
0000 X00Xb
A/D Control Register 0
A/D Control Register 1
D/A0 Register
ADCON0
ADCON1
DA0
0000 0XXXb
0000 X000b
00h
D/A Control Register
DACON
00h
Port P0 Register
Port P1 Register
Port P0 Direction Register
Port P1 Direction Register
Port P2 Register
Port P3 Register
Port P2 Direction Register
Port P3 Direction Register
Port P4 Register
Port P5 Register
Port P4 Direction Register
Port P5 Direction Register
Port P6 Register
Port P7 Register
Port P6 Direction Register
Port P7 Direction Register
P0
P1
PD0
PD1
P2
P3
PD2
PD3
P4
P5
PD4
PD5
P6
P7
PD6
PD7
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
XXh
00h
00h
X: Undefined
The blank areas are reserved. No access is allowed.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 50 of 156
M16C/5M Group, M16C/57 Group
Table 4.20
Address
03F0h
03F1h
03F2h
03F3h
03F4h
03F5h
03F6h
03F7h
03F8h
03F9h
03FAh
03FBh
03FCh
03FDh
03FEh
03FFh
4. Special Function Registers (SFRs)
SFR Information (20) (1)
Port P8 Register
Port P9 Register
Port P8 Direction Register
Port P9 Direction Register
Port P10 Register
Register
Symbol
P8
P9
PD8
PD9
P10
Reset Value
XXh
XXh
00h
00h
XXh
Port P10 Direction Register
PD10
00h
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 51 of 156
M16C/5M Group, M16C/57 Group
Table 4.21
Address
D1F0h
D1F1h
D1F2h
D1F3h
D1F4h
D1F5h
D1F6h
D1F7h
D1F8h
D1F9h
D1FAh
D1FBh
D1FCh
D1FDh
D1FEh
D1FFh
D200h
D201h
D202h
D203h
D204h
D205h
D206h
D207h
D208h
D209h
D20Ah
D20Bh
D20Ch
D20Dh
D20Eh
D20Fh
D210h
D211h
D212h
D213h
D214h
D215h
D216h
D217h
D218h
D219h
D21Ah
D21Bh
D21Ch
D21Dh
D21Eh
D21Fh
Note:
1.
4. Special Function Registers (SFRs)
SFR Information (21) (1)
Register
Symbol
XXh
XXh
XXh
XXh
CAN1 Mailbox 0: Message Identifier
CAN1 Mailbox 0: Data Length
C1MB0
CAN1 Mailbox 0: Data Field
CAN1 Mailbox 0: Time Stamp
CAN1 Message Identifier
CAN1 Mailbox 1: Data Length
C1MB1
CAN1 Mailbox 1: Data Field
CAN1 Mailbox 1: Time Stamp
Reset Value
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
X: Undefined
The blank areas are reserved. No access is allowed.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 52 of 156
M16C/5M Group, M16C/57 Group
Table 4.22
Address
D220h
D221h
D222h
D223h
D224h
D225h
D226h
D227h
D228h
D229h
D22Ah
D22Bh
D22Ch
D22Dh
D22Eh
D22Fh
D230h
D231h
D232h
D233h
D234h
D235h
D236h
D237h
D238h
D239h
D23Ah
D23Bh
D23Ch
D23Dh
D23Eh
D23Fh
D240h
D241h
D242h
D243h
D244h
D245h
D246h
D247h
D248h
D249h
D24Ah
D24Bh
D24Ch
D24Dh
D24Eh
D24Fh
Note:
1.
4. Special Function Registers (SFRs)
SFR Information (22) (1)
Register
Symbol
CAN1 Mailbox 2: Message Identifier
CAN1 Mailbox 2: Data Length
C1MB2
CAN1 Mailbox 2: Data Field
CAN1 Mailbox 2: Time Stamp
CAN1 Mailbox 3: Message Identifier
CAN1 Mailbox 3: Data Length
C1MB3
CAN1 Mailbox 3: Data Field
CAN1 Mailbox 3: Time Stamp
CAN1 Mailbox 4: Message Identifier
CAN1 Mailbox 4: Data Length
C1MB4
CAN1 Mailbox 4: Data Field
CAN1 Mailbox 4: Time Stamp
Reset Value
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
X: Undefined
The blank areas are reserved. No access is allowed.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 53 of 156
M16C/5M Group, M16C/57 Group
Table 4.23
Address
D250h
D251h
D252h
D253h
D254h
D255h
D256h
D257h
D258h
D259h
D25Ah
D25Bh
D25Ch
D25Dh
D25Eh
D25Fh
D260h
D261h
D262h
D263h
D264h
D265h
D266h
D267h
D268h
D269h
D26Ah
D26Bh
D26Ch
D26Dh
D26Eh
D26Fh
D270h
D271h
D272h
D273h
D274h
D275h
D276h
D277h
D278h
D279h
D27Ah
D27Bh
D27Ch
D27Dh
D27Eh
D27Fh
Note:
1.
4. Special Function Registers (SFRs)
SFR Information (23) (1)
Register
Symbol
CAN1 Mailbox 5: Message Identifier
CAN1 Mailbox 5: Data Length
C1MB5
CAN1 Mailbox 5: Data Field
CAN1 Mailbox 5: Time Stamp
CAN1 Mailbox 6: Message Identifier
CAN1 Mailbox 6: Data Length
C1MB6
CAN1 Mailbox 6: Data Field
CAN1 Mailbox 6: Time Stamp
CAN1 Mailbox 7: Message Identifier
CAN1 Mailbox 7: Data Length
C1MB7
CAN1 Mailbox 7: Data Field
CAN1 Mailbox 7: Time Stamp
Reset Value
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
X: Undefined
The blank areas are reserved. No access is allowed.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 54 of 156
M16C/5M Group, M16C/57 Group
Table 4.24
Address
D280h
D281h
D282h
D283h
D284h
D285h
D286h
D287h
D288h
D289h
D28Ah
D28Bh
D28Ch
D28Dh
D28Eh
D28Fh
D290h
D291h
D292h
D293h
D294h
D295h
D296h
D297h
D298h
D299h
D29Ah
D29Bh
D29Ch
D29Dh
D29Eh
D29Fh
D2A0h
D2A1h
D2A2h
D2A3h
D2A4h
D2A5h
D2A6h
D2A7h
D2A8h
D2A9h
D2AAh
D2ABh
D2ACh
D2ADh
D2AEh
D2AFh
Note:
1.
4. Special Function Registers (SFRs)
SFR Information (24) (1)
Register
Symbol
CAN1 Mailbox 8: Message Identifier
CAN1 Mailbox 8: Data Length
C1MB8
CAN1 Mailbox 8: Data Field
CAN1 Mailbox 8: Time Stamp
CAN1 Mailbox 9: Message Identifier
CAN1 Mailbox 9: Data Length
C1MB9
CAN1 Mailbox 9: Data Field
CAN1 Mailbox 9: Time Stamp
CAN1 Mailbox 10: Message Identifier
CAN1 Mailbox 10: Data Length
C1MB10
CAN1 Mailbox 10: Data Field
CAN1 Mailbox 10: Time Stamp
Reset Value
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
X: Undefined
The blank areas are reserved. No access is allowed.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 55 of 156
M16C/5M Group, M16C/57 Group
Table 4.25
Address
D2B0h
D2B1h
D2B2h
D2B3h
D2B4h
D2B5h
D2B6h
D2B7h
D2B8h
D2B9h
D2BAh
D2BBh
D2BCh
D2BDh
D2BEh
D2BFh
D2C0h
D2C1h
D2C2h
D2C3h
D2C4h
D2C5h
D2C6h
D2C7h
D2C8h
D2C9h
D2CAh
D2CBh
D2CCh
D2CDh
D2CEh
D2CFh
D2D0h
D2D1h
D2D2h
D2D3h
D2D4h
D2D5h
D2D6h
D2D7h
D2D8h
D2D9h
D2DAh
D2DBh
D2DCh
D2DDh
D2DEh
D2DFh
Note:
1.
4. Special Function Registers (SFRs)
SFR Information (25) (1)
Register
Symbol
CAN1 Mailbox 11: Message Identifier
CAN1 Mailbox 11: Data Length
C1MB11
CAN1 Mailbox 11: Data Field
CAN1 Mailbox 11: Time Stamp
CAN1 Mailbox 12: Message Identifier
CAN1 Mailbox 12: Data Length
C1MB12
CAN1 Mailbox 12: Data Field
CAN1 Mailbox 12: Time Stamp
CAN1 Mailbox 13: Message Identifier
CAN1 Mailbox 13: Data Length
C1MB13
CAN1 Mailbox 13: Data Field
CAN1 Mailbox 13: Time Stamp
Reset Value
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
X: Undefined
The blank areas are reserved. No access is allowed.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 56 of 156
M16C/5M Group, M16C/57 Group
Table 4.26
Address
D2E0h
D2E1h
D2E2h
D2E3h
D2E4h
D2E5h
D2E6h
D2E7h
D2E8h
D2E9h
D2EAh
D2EBh
D2ECh
D2EDh
D2EEh
D2EFh
D2F0h
D2F1h
D2F2h
D2F3h
D2F4h
D2F5h
D2F6h
D2F7h
D2F8h
D2F9h
D2FAh
D2FBh
D2FCh
D2FDh
D2FEh
D2FFh
D300h
D301h
D302h
D303h
D304h
D305h
D306h
D307h
D308h
D309h
D30Ah
D30Bh
D30Ch
D30Dh
D30Eh
D30Fh
Note:
1.
4. Special Function Registers (SFRs)
SFR Information (26) (1)
Register
Symbol
CAN1 Mailbox 14: Message Identifier
CAN1 Mailbox 14: Data Length
C1MB14
CAN1 Mailbox 14: Data Field
CAN1 Mailbox 14: Time Stamp
CAN1 Mailbox 15: Message Identifier
CAN1 Mailbox 15: Data Length
C1MB15
CAN1 Mailbox 15: Data Field
CAN1 Mailbox 15: Time Stamp
CAN1 Mailbox16: Message Identifier
CAN1 Mailbox 16: Data Length
C1MB16
CAN1 Mailbox 16: Data Field
CAN1 Mailbox 16: Time Stamp
Reset Value
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
X: Undefined
The blank areas are reserved. No access is allowed.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 57 of 156
M16C/5M Group, M16C/57 Group
Table 4.27
Address
D310h
D311h
D312h
D313h
D314h
D315h
D316h
D317h
D318h
D319h
D31Ah
D31Bh
D31Ch
D31Dh
D31Eh
D31Fh
D320h
D321h
D322h
D323h
D324h
D325h
D326h
D327h
D328h
D329h
D32Ah
D32Bh
D32Ch
D32Dh
D32Eh
D32Fh
D330h
D331h
D332h
D333h
D334h
D335h
D336h
D337h
D338h
D339h
D33Ah
D33Bh
D33Ch
D33Dh
D33Eh
D33Fh
Note:
1.
4. Special Function Registers (SFRs)
SFR Information (27) (1)
Register
Symbol
CAN1 Mailbox 17: Message Identifier
CAN1 Mailbox 17: Data Length
C1MB17
CAN1 Mailbox 17: Data Field
CAN1 Mailbox 17: Time Stamp
CAN1 Mailbox 18: Message Identifier
CAN1 Mailbox 18: Data Length
C1MB18
CAN1 Mailbox 18: Data Field
CAN1 Mailbox 18: Time Stamp
CAN1 Mailbox 19: Message Identifier
CAN1 Mailbox 19: Data Length
C1MB19
CAN1 Mailbox 19: Data Field
CAN1 Mailbox 19: Time Stamp
Reset Value
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
X: Undefined
The blank areas are reserved. No access is allowed.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 58 of 156
M16C/5M Group, M16C/57 Group
Table 4.28
Address
D340h
D341h
D342h
D343h
D344h
D345h
D346h
D347h
D348h
D349h
D34Ah
D34Bh
D34Ch
D34Dh
D34Eh
D34Fh
D350h
D351h
D352h
D353h
D354h
D355h
D356h
D357h
D358h
D359h
D35Ah
D35Bh
D35Ch
D35Dh
D35Eh
D35Fh
D360h
D361h
D362h
D363h
D364h
D365h
D366h
D367h
D368h
D369h
D36Ah
D36Bh
D36Ch
D36Dh
D36Eh
D36Fh
Note:
1.
4. Special Function Registers (SFRs)
SFR Information (28) (1)
Register
Symbol
CAN1 Mailbox 20: Message Identifier
CAN1 Mailbox 20: Data Length
C1MB20
CAN1 Mailbox 20: Data Field
CAN1 Mailbox 20: Time Stamp
CAN1 Mailbox 21: Message Identifier
CAN1 Mailbox 21: Data Length
C1MB21
CAN1 Mailbox 21: Data Field
CAN1 Mailbox 21: Time Stamp
CAN1 Mailbox 22: Message Identifier
CAN1 Mailbox 22: Data Length
C1MB22
CAN1 Mailbox 22: Data Field
CAN1 Mailbox 22: Time Stamp
Reset Value
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
X: Undefined
The blank areas are reserved. No access is allowed.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 59 of 156
M16C/5M Group, M16C/57 Group
Table 4.29
Address
D370h
D371h
D372h
D373h
D374h
D375h
D376h
D377h
D378h
D379h
D37Ah
D37Bh
D37Ch
D37Dh
D37Eh
D37Fh
D380h
D381h
D382h
D383h
D384h
D385h
D386h
D387h
D388h
D389h
D38Ah
D38Bh
D38Ch
D38Dh
D38Eh
D38Fh
D390h
D391h
D392h
D393h
D394h
D395h
D396h
D397h
D398h
D399h
D39Ah
D39Bh
D39Ch
D39Dh
D39Eh
D39Fh
Note:
1.
4. Special Function Registers (SFRs)
SFR Information (29) (1)
Register
Symbol
CAN1 Mailbox 23: Message Identifier
CAN1 Mailbox 23: Data Length
C1MB23
CAN1 Mailbox 23: Data Field
CAN1 Mailbox 23: Time Stamp
CAN1 Mailbox 24: Message Identifier
CAN1 Mailbox 24: Data Length
C1MB24
CAN1 Mailbox 24: Data Field
CAN1 Mailbox 24: Time Stamp
CAN1 Mailbox 25: Message Identifier
CAN1 Mailbox 25: Data Length
C1MB25
CAN1 Mailbox 25: Data Field
CAN1 Mailbox 25: Time Stamp
Reset Value
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
X: Undefined
The blank areas are reserved. No access is allowed.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 60 of 156
M16C/5M Group, M16C/57 Group
Table 4.30
Address
D3A0h
D3A1h
D3A2h
D3A3h
D3A4h
D3A5h
D3A6h
D3A7h
D3A8h
D3A9h
D3AAh
D3ABh
D3ACh
D3ADh
D3AEh
D3AFh
D3B0h
D3B1h
D3B2h
D3B3h
D3B4h
D3B5h
D3B6h
D3B7h
D3B8h
D3B9h
D3BAh
D3BBh
D3BCh
D3BDh
D3BEh
D3BFh
D3C0h
D3C1h
D3C2h
D3C3h
D3C4h
D3C5h
D3C6h
D3C7h
D3C8h
D3C9h
D3CAh
D3CBh
D3CCh
D3CDh
D3CEh
D3CFh
Note:
1.
4. Special Function Registers (SFRs)
SFR Information (30) (1)
Register
Symbol
CAN1 Mailbox 26: Message Identifier
CAN1 Mailbox 26: Data Length
C1MB26
CAN1 Mailbox 26: Data Field
CAN1 Mailbox 26: Time Stamp
CAN1 Mailbox 27: Message Identifier
CAN1 Mailbox 27: Data Length
C1MB27
CAN1 Mailbox 27: Data Field
CAN1 Mailbox 27: Time Stamp
CAN1 Mailbox 28: Message Identifier
CAN1 Mailbox 28: Data Length
C1MB28
CAN1 Mailbox 28: Data Field
CAN1 Mailbox 28: Time Stamp
Reset Value
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
X: Undefined
The blank areas are reserved. No access is allowed.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 61 of 156
M16C/5M Group, M16C/57 Group
Table 4.31
Address
D3D0h
D3D1h
D3D2h
D3D3h
D3D4h
D3D5h
D3D6h
D3D7h
D3D8h
D3D9h
D3DAh
D3DBh
D3DCh
D3DDh
D3DEh
D3DFh
D3E0h
D3E1h
D3E2h
D3E3h
D3E4h
D3E5h
D3E6h
D3E7h
D3E8h
D3E9h
D3EAh
D3EBh
D3ECh
D3EDh
D3EEh
D3EFh
D3F0h
D3F1h
D3F2h
D3F3h
D3F4h
D3F5h
D3F6h
D3F7h
D3F8h
D3F9h
D3FAh
D3FBh
D3FCh
D3FDh
D3FEh
D3FFh
Note:
1.
4. Special Function Registers (SFRs)
SFR Information (31) (1)
Register
Symbol
CAN1 Mailbox 29: Message Identifier
CAN1 Mailbox 29: Data Length
C1MB29
CAN1 Mailbox 29: Data Field
CAN1 Mailbox 29: Time Stamp
CAN1 Mailbox 30: Message Identifier
CAN1 Mailbox 30: Data Length
C1MB30
CAN1 Mailbox 30: Data Field
CAN1 Mailbox 30: Time Stamp
CAN1 Mailbox 31: Message Identifier
CAN1 Mailbox 31: Data Length
C1MB31
CAN1 Mailbox 31: Data Field
CAN1 Mailbox 31: Time Stamp
Reset Value
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
X: Undefined
The blank areas are reserved. No access is allowed.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 62 of 156
M16C/5M Group, M16C/57 Group
Table 4.32
Address
D400h
D401h
D402h
D403h
D404h
D405h
D406h
D407h
D408h
D409h
D40Ah
D40Bh
D40Ch
D40Dh
D40Eh
D40Fh
D410h
D411h
D412h
D413h
D414h
D415h
D416h
D417h
D418h
D419h
D41Ah
D41Bh
D41Ch
D41Dh
D41Eh
D41Fh
D420h
D421h
D422h
D423h
D424h
D425h
D426h
D427h
D428h
D429h
D42Ah
D42Bh
D42Ch
D42Dh
D42Eh
D42Fh
D430h to
D49Fh
4. Special Function Registers (SFRs)
SFR Information (32) (1)
Register
Symbol
CAN1 Mask Register 0
C1MKR0
CAN1 Mask Register 1
C1MKR1
CAN1 Mask Register 2
C1MKR2
CAN1 Mask Register 3
C1MKR3
CAN1 Mask Register 4
C1MKR4
CAN1 Mask Register 5
C1MKR5
CAN1 Mask Register 6
C1MKR6
CAN1 Mask Register 7
C1MKR7
CAN1FIFO Receive ID Compare Register 0
C1FIDCR0
CAN1FIFO Receive ID Compare Register 1
C1FIDCR1
CAN1 Mask Invalid Register
C1MKIVLR
CAN1 Mailbox Interrupt Enable Register
C1MIER
Reset Value
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 63 of 156
M16C/5M Group, M16C/57 Group
Table 4.33
4. Special Function Registers (SFRs)
SFR Information (33) (1)
Address
D4A0h
Register
CAN1 Message Control Register 0
Symbol
C1MCTL0
Reset Value
00h
D4A1h
CAN1 Message Control Register 1
C1MCTL1
00h
D4A2h
CAN1 Message Control Register 2
C1MCTL2
00h
D4A3h
CAN1 Message Control Register 3
C1MCTL3
00h
D4A4h
CAN1 Message Control Register 4
C1MCTL4
00h
D4A5h
CAN1 Message Control Register 5
C1MCTL5
00h
D4A6h
CAN1 Message Control Register 6
C1MCTL6
00h
D4A7h
CAN1 Message Control Register 7
C1MCTL7
00h
D4A8h
CAN1 Message Control Register 8
C1MCTL8
00h
D4A9h
CAN1 Message Control Register 9
C1MCTL9
00h
D4AAh
CAN1 Message Control Register 10
C1MCTL10
00h
D4ABh
CAN1 Message Control Register 11
C1MCTL11
00h
D4ACh
CAN1 Message Control Register 12
C1MCTL12
00h
D4ADh
CAN1 Message Control Register 13
C1MCTL13
00h
D4AEh
CAN1 Message Control Register 14
C1MCTL14
00h
D4AFh
CAN1 Message Control Register 15
C1MCTL15
D4B0h
CAN1 Message Control Register 16
C1MCTL16
00h
00h
00h
D4B1h
CAN1 Message Control Register 17
C1MCTL17
D4B2h
CAN1 Message Control Register 18
C1MCTL18
00h
D4B3h
CAN1 Message Control Register 19
C1MCTL19
00h
D4B4h
CAN1 Message Control Register 20
C1MCTL20
00h
D4B5h
CAN1 Message Control Register 21
C1MCTL21
00h
00h
D4B6h
CAN1 Message Control Register 22
C1MCTL22
D4B7h
CAN1 Message Control Register 23
C1MCTL23
00h
D4B8h
CAN1 Message Control Register 24
C1MCTL24
00h
D4B9h
CAN1 Message Control Register 25
C1MCTL25
00h
D4BAh
CAN1 Message Control Register 26
C1MCTL26
00h
D4BBh
CAN1 Message Control Register 27
C1MCTL27
00h
D4BCh
CAN1 Message Control Register 28
C1MCTL28
00h
D4BDh
CAN1 Message Control Register 29
C1MCTL29
00h
D4BEh
CAN1 Message Control Register 30
C1MCTL30
00h
D4BFh
CAN1 Message Control Register 31
C1MCTL31
00h
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 64 of 156
M16C/5M Group, M16C/57 Group
Table 4.34
Address
D4C0h
D4C1h
D4C2h
D4C3h
4. Special Function Registers (SFRs)
SFR Information (34) (1)
Register
CAN1 Control Register
CAN1 Status Register
Symbol
C1CTLR
C1STR
D4C4h
D4C5h
Reset Value
0000 0101b
00h
0000 0101b
00h
00h
CAN1 Bit Configuration Register
C1BCR
D4C7h
CAN1 Clock Select Register
C1CLKR
00h
D4C8h
CAN1 Receive FIFO Control Register
C1RFCR
10000000b
D4C9h
CAN1 Receive FIFO Pointer Control Register
C1RFPCR
XXh
D4CAh
CAN1 Transmit FIFO Control Register
D4CBh
CAN1 Transmit FIFO Pointer Control Register
D4CCh
D4C6h
00h
00h
C1TFCR
1000 0000b
C1TFPCR
XXh
CAN1 Error Interrupt Enable Register
C1EIER
00h
D4CDh
CAN1 Error Interrupt Source Judge Register
C1EIFR
00h
D4CEh
CAN1 Receive Error Count Register
C1RECR
00h
D4CFh
CAN1 Transmit Error Count Register
C1TECR
00h
D4D0h
CAN1 Error Code Store Register
C1ECSR
00h
D4D1h
CAN1 Channel Search Support Register
C1CSSR
XXh
D4D2h
CAN1 Mailbox Search Status Register
C1MSSR
1000 0000b
D4D3h
CAN1 Mailbox Search Mode Register
C1MSMR
XXXX XX00b
D4D4h
D4D5h
D4D6h
D4D7h
D4D8h
CAN1 Time Stamp Register
CAN1 Acceptance Filter Support Register
CAN1 Test Control Register
C1TSR
C1AFSR
C1TCR
00h
00h
XXh
XXh
00h
D4D9h
D4DAh
D4DBh
D4DCh
D4DDh
D4DEh
D4DFh
D4E0h to
D4FFh
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 65 of 156
M16C/5M Group, M16C/57 Group
Table 4.35
Address
D500h
D501h
D502h
D503h
D504h
D505h
D506h
D507h
D508h
D509h
D50Ah
D50Bh
D50Ch
D50Dh
D50Eh
D50Fh
D510h
D511h
D512h
D513h
D514h
D515h
D516h
D517h
D518h
D519h
D51Ah
D51Bh
D51Ch
D51Dh
D51Eh
D51Fh
D520h
D521h
D522h
D523h
D524h
D525h
D526h
D527h
D528h
D529h
D52Ah
D52Bh
D52Ch
D52Dh
D52Eh
D52Fh
Note:
1.
4. Special Function Registers (SFRs)
SFR Information (35) (1)
Register
Symbol
CAN0 Mailbox 0: Message Identifier
CAN0 Mailbox 0: Data Length
C0MB0
CAN0 Mailbox 0: Data Field
CAN0 Mailbox 0: Time Stamp
CAN0 Mailbox 1: Message Identifier
CAN0 Mailbox 1: Data Length
C0MB1
CAN0 Mailbox 1: Data Field
CAN0 Mailbox 1: Time Stamp
CAN0 Mailbox 2: Message Identifier
CAN0 Mailbox 2: Data Length
C0MB2
CAN0 Mailbox 2: Data Field
CAN0 Mailbox 2: Time Stamp
Reset Value
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
X: Undefined
The blank areas are reserved. No access is allowed.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 66 of 156
M16C/5M Group, M16C/57 Group
Table 4.36
Address
D530h
D531h
D532h
D533h
D534h
D535h
D536h
D537h
D538h
D539h
D53Ah
D53Bh
D53Ch
D53Dh
D53Eh
D53Fh
D540h
D541h
D542h
D543h
D544h
D545h
D546h
D547h
D548h
D549h
D54Ah
D54Bh
D54Ch
D54Dh
D54Eh
D54Fh
D550h
D551h
D552h
D553h
D554h
D555h
D556h
D557h
D558h
D559h
D55Ah
D55Bh
D55Ch
D55Dh
D55Eh
D55Fh
Note:
1.
4. Special Function Registers (SFRs)
SFR Information (36) (1)
Register
Symbol
CAN0 Mailbox 3: Message Identifier
CAN0 Mailbox 3: Data Length
C0MB3
CAN0 Mailbox 3: Data Field
CAN0 Mailbox 3: Time Stamp
CAN0 Mailbox 4: Message Identifier
CAN0 Mailbox 4: Data Length
C0MB4
CAN0 Mailbox 4: Data Field
CAN0 Mailbox 4: Time Stamp
CAN0 Mailbox 5: Message Identifier
CAN0 Mailbox 5: Data Length
C0MB5
CAN0 Mailbox 5: Data Field
CAN0 Mailbox 5: Time Stamp
Reset Value
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
X: Undefined
The blank areas are reserved. No access is allowed.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 67 of 156
M16C/5M Group, M16C/57 Group
Table 4.37
Address
D560h
D561h
D562h
D563h
D564h
D565h
D566h
D567h
D568h
D569h
D56Ah
D56Bh
D56Ch
D56Dh
D56Eh
D56Fh
D570h
D571h
D572h
D573h
D574h
D575h
D576h
D577h
D578h
D579h
D57Ah
D57Bh
D57Ch
D57Dh
D57Eh
D57Fh
D580h
D581h
D582h
D583h
D584h
D585h
D586h
D587h
D588h
D589h
D58Ah
D58Bh
D58Ch
D58Dh
D58Eh
D58Fh
Note:
1.
4. Special Function Registers (SFRs)
SFR Information (37) (1)
Register
Symbol
CAN0 Mailbox 6: Message Identifier
CAN0 Mailbox 6: Data Length
C0MB6
CAN0 Mailbox 6: Data Field
CAN0 Mailbox 6: Time Stamp
CAN0 Mailbox 7: Message Identifier
CAN0 Mailbox 7: Data Length
C0MB7
CAN0 Mailbox 7: Data Field
CAN0 Mailbox 7: Time Stamp
CAN0 Mailbox 8: Message Identifier
CAN0 Mailbox 8: Data Length
C0MB8
CAN0 Mailbox 8: Data Field
CAN0 Mailbox 8: Time Stamp
Reset Value
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
X: Undefined
The blank areas are reserved. No access is allowed.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 68 of 156
M16C/5M Group, M16C/57 Group
Table 4.38
Address
D590h
D591h
D592h
D593h
D594h
D595h
D596h
D597h
D598h
D599h
D59Ah
D59Bh
D59Ch
D59Dh
D59Eh
D59Fh
D5A0h
D5A1h
D5A2h
D5A3h
D5A4h
D5A5h
D5A6h
D5A7h
D5A8h
D5A9h
D5AAh
D5ABh
D5ACh
D5ADh
D5AEh
D5AFh
D5B0h
D5B1h
D5B2h
D5B3h
D5B4h
D5B5h
D5B6h
D5B7h
D5B8h
D5B9h
D5BAh
D5BBh
D5BCh
D5BDh
D5BEh
D5BFh
Note:
1.
4. Special Function Registers (SFRs)
SFR Information (38) (1)
Register
Symbol
CAN0 Mailbox 9: Message Identifier
CAN0 Mailbox 9: Data Length
C0MB9
CAN0 Mailbox 9: Data Field
CAN0 Mailbox 9: Time Stamp
CAN0 Mailbox 10: Message Identifier
CAN0 Mailbox 10: Data Length
C0MB10
CAN0 Mailbox 10: Data Field
CAN0 Mailbox 10: Time Stamp
CAN0 Mailbox 11: Message Identifier
CAN0 Mailbox 11: Data Length
C0MB11
CAN0 Mailbox 11: Data Field
CAN0 Mailbox 11: Time Stamp
Reset Value
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
X: Undefined
The blank areas are reserved. No access is allowed.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 69 of 156
M16C/5M Group, M16C/57 Group
Table 4.39
Address
D5C0h
D5C1h
D5C2h
D5C3h
D5C4h
D5C5h
D5C6h
D5C7h
D5C8h
D5C9h
D5CAh
D5CBh
D5CCh
D5CDh
D5CEh
D5CFh
D5D0h
D5D1h
D5D2h
D5D3h
D5D4h
D5D5h
D5D6h
D5D7h
D5D8h
D5D9h
D5DAh
D5DBh
D5DCh
D5DDh
D5DEh
D5DFh
D5E0h
D5E1h
D5E2h
D5E3h
D5E4h
D5E5h
D5E6h
D5E7h
D5E8h
D5E9h
D5EAh
D5EBh
D5ECh
D5EDh
D5EEh
D5EFh
Note:
1.
4. Special Function Registers (SFRs)
SFR Information (39) (1)
Register
Symbol
CAN0 Mailbox 12: Message Identifier
CAN0 Mailbox 12: Data Length
C0MB12
CAN0 Mailbox 12: Data Field
CAN0 Mailbox 12: Time Stamp
CAN0 Mailbox 13: Message Identifier
CAN0 Mailbox 13: Data Length
C0MB13
CAN0 Mailbox 13: Data Field
CAN0 Mailbox 13: Time Stamp
CAN0 Mailbox 14: Message Identifier
CAN0 Mailbox 14: Data Length
C0MB14
CAN0 Mailbox 14: Data Field
CAN0 Mailbox 14: Time Stamp
Reset Value
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
X: Undefined
The blank areas are reserved. No access is allowed.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 70 of 156
M16C/5M Group, M16C/57 Group
Table 4.40
Address
D5F0h
D5F1h
D5F2h
D5F3h
D5F4h
D5F5h
D5F6h
D5F7h
D5F8h
D5F9h
D5FAh
D5FBh
D5FCh
D5FDh
D5FEh
D5FFh
D600h
D601h
D602h
D603h
D604h
D605h
D606h
D607h
D608h
D609h
D60Ah
D60Bh
D60Ch
D60Dh
D60Eh
D60Fh
D610h
D611h
D612h
D613h
D614h
D615h
D616h
D617h
D618h
D619h
D61Ah
D61Bh
D61Ch
D61Dh
D61Eh
D61Fh
Note:
1.
4. Special Function Registers (SFRs)
SFR Information (40) (1)
Register
Symbol
CAN0 Mailbox 15: Message Identifier
CAN0 Mailbox 15: Data Length
C0MB15
CAN0 Mailbox 15: Data Field
CAN0 Mailbox 15: Time Stamp
CAN0 Mailbox 16: Message Identifier
CAN0 Mailbox 16: Data Length
C0MB16
CAN0 Mailbox 16: Data Field
CAN0 Mailbox 16: Time Stamp
CAN0 Mailbox 17: Message Identifier
CAN0 Mailbox 17: Data Length
C0MB17
CAN0 Mailbox 17: Data Field
CAN0 Mailbox 17: Time Stamp
Reset Value
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
X: Undefined
The blank areas are reserved. No access is allowed.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 71 of 156
M16C/5M Group, M16C/57 Group
Table 4.41
Address
D620h
D621h
D622h
D623h
D624h
D625h
D626h
D627h
D628h
D629h
D62Ah
D62Bh
D62Ch
D62Dh
D62Eh
D62Fh
D630h
D631h
D632h
D633h
D634h
D635h
D636h
D637h
D638h
D639h
D63Ah
D63Bh
D63Ch
D63Dh
D63Eh
D63Fh
D640h
D641h
D642h
D643h
D644h
D645h
D646h
D647h
D648h
D649h
D64Ah
D64Bh
D64Ch
D64Dh
D64Eh
D64Fh
Note:
1.
4. Special Function Registers (SFRs)
SFR Information (41) (1)
Register
Symbol
CAN0 Mailbox 18: Message Identifier
CAN0 Mailbox 18: Data Length
C0MB18
CAN0 Mailbox 18: Data Field
CAN0 Mailbox 18: Time Stamp
CAN0 Mailbox 19: Message Identifier
CAN0 Mailbox 19: Data Length
C0MB19
CAN0 Mailbox 19: Data Field
CAN0 Mailbox 19: Time Stamp
CAN0 Mailbox 20: Message Identifier
CAN0 Mailbox 20: Data Length
C0MB20
CAN0 Mailbox 20: Data Field
CAN0 Mailbox 20: Time Stamp
Reset Value
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
X: Undefined
The blank areas are reserved. No access is allowed.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 72 of 156
M16C/5M Group, M16C/57 Group
Table 4.42
Address
D650h
D651h
D652h
D653h
D654h
D655h
D656h
D657h
D658h
D659h
D65Ah
D65Bh
D65Ch
D65Dh
D65Eh
D65Fh
D660h
D661h
D662h
D663h
D664h
D665h
D666h
D667h
D668h
D669h
D66Ah
D66Bh
D66Ch
D66Dh
D66Eh
D66Fh
D670h
D671h
D672h
D673h
D674h
D675h
D676h
D677h
D678h
D679h
D67Ah
D67Bh
D67Ch
D67Dh
D67Eh
D67Fh
Note:
1.
4. Special Function Registers (SFRs)
SFR Information (42) (1)
Register
Symbol
CAN0 Mailbox 21: Message Identifier
CAN0 Mailbox 21: Data Length
C0MB21
CAN0 Mailbox 21: Data Field
CAN0 Mailbox 21: Time Stamp
CAN0 Mailbox 22: Message Identifier
CAN0 Mailbox 22: Data Length
C0MB22
CAN0 Mailbox 22: Data Field
CAN0 Mailbox 22: Time Stamp
CAN0 Mailbox 23: Message Identifier
CAN0 Mailbox 23: Data Length
C0MB23
CAN0 Mailbox 23: Data Field
CAN0 Mailbox 23: Time Stamp
Reset Value
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
X: Undefined
The blank areas are reserved. No access is allowed.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 73 of 156
M16C/5M Group, M16C/57 Group
Table 4.43
Address
D680h
D681h
D682h
D683h
D684h
D685h
D686h
D687h
D688h
D689h
D68Ah
D68Bh
D68Ch
D68Dh
D68Eh
D68Fh
D690h
D691h
D692h
D693h
D694h
D695h
D696h
D697h
D698h
D699h
D69Ah
D69Bh
D69Ch
D69Dh
D69Eh
D69Fh
D6A0h
D6A1h
D6A2h
D6A3h
D6A4h
D6A5h
D6A6h
D6A7h
D6A8h
D6A9h
D6AAh
D6ABh
D6ACh
D6ADh
D6AEh
D6AFh
Note:
1.
4. Special Function Registers (SFRs)
SFR Information (43) (1)
Register
Symbol
CAN0 Mailbox 24: Message Identifier
CAN0 Mailbox 24: Data Length
C0MB24
CAN0 Mailbox 24: Data Field
CAN0 Mailbox 24: Time Stamp
CAN0 Mailbox 25: Message Identifier
CAN0 Mailbox 25: Data Length
C0MB25
CAN0 Mailbox 25: Data Field
CAN0 Mailbox 25: Time Stamp
CAN0 Mailbox 26: Message Identifier
CAN0 Mailbox 26: Data Length
C0MB26
CAN0 Mailbox 26: Data Field
CAN0 Mailbox 26: Time Stamp
Reset Value
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
X: Undefined
The blank areas are reserved. No access is allowed.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 74 of 156
M16C/5M Group, M16C/57 Group
Table 4.44
Address
D6B0h
D6B1h
D6B2h
D6B3h
D6B4h
D6B5h
D6B6h
D6B7h
D6B8h
D6B9h
D6BAh
D6BBh
D6BCh
D6BDh
D6BEh
D6BFh
D6C0h
D6C1h
D6C2h
D6C3h
D6C4h
D6C5h
D6C6h
D6C7h
D6C8h
D6C9h
D6CAh
D6CBh
D6CCh
D6CDh
D6CEh
D6CFh
D6D0h
D6D1h
D6D2h
D6D3h
D6D4h
D6D5h
D6D6h
D6D7h
D6D8h
D6D9h
D6DAh
D6DBh
D6DCh
D6DDh
D6DEh
D6DFh
Note:
1.
4. Special Function Registers (SFRs)
SFR Information (44) (1)
Register
Symbol
CAN0 Mailbox 27: Message Identifier
CAN0 Mailbox 27: Data Length
C0MB27
CAN0 Mailbox 27: Data Field
CAN0 Mailbox 27: Time Stamp
CAN0 Mailbox 28: Message Identifier
CAN0 Mailbox 28: Data Length
C0MB28
CAN0 Mailbox 28: Data Field
CAN0 Mailbox 28: Time Stamp
CAN0 Mailbox 29: Message Identifier
CAN0 Mailbox 29: Data Length
C0MB29
CAN0 Mailbox 29: Data Field
CAN0 Mailbox 29: Time Stamp
Reset Value
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
X: Undefined
The blank areas are reserved. No access is allowed.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 75 of 156
M16C/5M Group, M16C/57 Group
Table 4.45
Address
D6E0h
D6E1h
D6E2h
D6E3h
D6E4h
D6E5h
D6E6h
D6E7h
D6E8h
D6E9h
D6EAh
D6EBh
D6ECh
D6EDh
D6EEh
D6EFh
D6F0h
D6F1h
D6F2h
D6F3h
D6F4h
D6F5h
D6F6h
D6F7h
D6F8h
D6F9h
D6FAh
D6FBh
D6FCh
D6FDh
D6FEh
D6FFh
D700h
D701h
D702h
D703h
D704h
D705h
D706h
D707h
D708h
D709h
D70Ah
D70Bh
D70Ch
D70Dh
D70Eh
D70Fh
Note:
1.
4. Special Function Registers (SFRs)
SFR Information (45) (1)
Register
Symbol
CAN0 Mailbox 30: Message Identifier
CAN0 Mailbox 30: Data Length
C0MB30
CAN0 Mailbox 30: Data Field
CAN0 Mailbox 30: Time Stamp
CAN0 Mailbox 31: Message Identifier
CAN0 Mailbox 31: Data Length
C0MB31
CAN0 Mailbox 31: Data Field
CAN0 Mailbox 31: Time Stamp
CAN0 Mask Register 0
C0MKR0
CAN0 Mask Register 1
C0MKR1
CAN0 Mask Register 2
C0MKR2
CAN0 Mask Register 3
C0MKR3
Reset Value
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
X: Undefined
The blank areas are reserved. No access is allowed.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 76 of 156
M16C/5M Group, M16C/57 Group
Table 4.46
Address
D710h
D711h
D712h
D713h
D714h
D715h
D716h
D717h
D718h
D719h
D71Ah
D71Bh
D71Ch
D71Dh
D71Eh
D71Fh
D720h
D721h
D722h
D723h
D724h
D725h
D726h
D727h
D728h
D729h
D72Ah
D72Bh
D72Ch
D72Dh
D72Eh
D72Fh
D730h to
D79Fh
D7A0h
D7A1h
D7A2h
D7A3h
D7A4h
D7A5h
D7A6h
D7A7h
D7A8h
D7A9h
D7AAh
D7ABh
D7ACh
D7ADh
D7AEh
D7AFh
Note:
1.
4. Special Function Registers (SFRs)
SFR Information (46) (1)
Register
Symbol
CAN0 Mask Register 4
C0MKR4
CAN0 Mask Register 5
C0MKR5
CAN0 Mask Register 6
C0MKR6
CAN0 Mask Register 7
C0MKR7
CAN0 FIFO Receive ID Compare Register 0
C0FIDCR0
CAN0 FIFO Receive ID Compare Register 1
C0FIDCR1
CAN0 Mask Invalid Register
C0MKIVLR
CAN0 Mailbox Interrupt Enable Register
CAN0 Message Control Register 0
CAN0 Message Control Register 1
CAN0 Message Control Register 2
CAN0 Message Control Register 3
CAN0 Message Control Register 4
CAN0 Message Control Register 5
CAN0 Message Control Register 6
CAN0 Message Control Register 7
CAN0 Message Control Register 8
CAN0 Message Control Register 9
CAN0 Message Control Register 10
CAN0 Message Control Register 11
CAN0 Message Control Register 12
CAN0 Message Control Register 13
CAN0 Message Control Register 14
CAN0 Message Control Register 15
C0MIER
C0MCTL0
C0MCTL1
C0MCTL2
C0MCTL3
C0MCTL4
C0MCTL5
C0MCTL6
C0MCTL7
C0MCTL8
C0MCTL9
C0MCTL10
C0MCTL11
C0MCTL12
C0MCTL13
C0MCTL14
C0MCTL15
Reset Value
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
X: Undefined
The blank areas are reserved. No access is allowed.
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Rev.1.01
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M16C/5M Group, M16C/57 Group
Table 4.47
Address
D7B0h
D7B1h
D7B2h
D7B3h
D7B4h
D7B5h
D7B6h
D7B7h
D7B8h
D7B9h
D7BAh
D7BBh
D7BCh
D7BDh
D7BEh
D7BFh
D7C0h
D7C1h
D7C2h
D7C3h
D7C4h
D7C5h
D7C6h
D7C7h
D7C8h
D7C9h
D7CAh
D7CBh
D7CCh
D7CDh
D7CEh
D7CFh
D7D0h
D7D1h
D7D2h
D7D3h
D7D4h
D7D5h
D7D6h
D7D7h
D7D8h
D7D9h
D7DAh
D7DBh
D7DCh
D7DDh
D7DEh
D7DFh
4. Special Function Registers (SFRs)
SFR Information (47) (1)
Register
CAN0 Message Control Register 16
CAN0 Message Control Register 17
CAN0 Message Control Register 18
CAN0 Message Control Register 19
CAN0 Message Control Register 20
CAN0 Message Control Register 21
CAN0 Message Control Register 22
CAN0 Message Control Register 23
CAN0 Message Control Register 24
CAN0 Message Control Register 25
CAN0 Message Control Register 26
CAN0 Message Control Register 27
CAN0 Message Control Register 28
CAN0 Message Control Register 29
CAN0 Message Control Register 30
CAN0 Message Control Register 31
Symbol
C0MCTL16
C0MCTL17
C0MCTL18
C0MCTL19
C0MCTL20
C0MCTL21
C0MCTL22
C0MCTL23
C0MCTL24
C0MCTL25
C0MCTL26
C0MCTL27
C0MCTL28
C0MCTL29
C0MCTL30
C0MCTL31
CAN0 Control Register
C0CTLR
CAN0 Status Register
C0STR
CAN0 Bit Configuration Register
C0BCR
CAN0 Clock Select Register
CAN0 Receive FIFO Control Register
CAN0 Receive FIFO Pointer Control Register
CAN0 Transmit FIFO Control Register
CAN0 Transmit FIFO pointer Control Register
CAN0 Error Interrupt Enable Register
CAN0 Error Interrupt Source Judge Register
CAN0 Receive Error Count Register
CAN0 Transmit Error Count Register
CAN0 Error Code Store Register
CAN0 Channel Search Support Register
CAN0 Mailbox Search Status Register
CAN0 Mailbox Search Mode Register
CAN0 Time Stamp Register
CAN0 Acceptance Filter Support Register
CAN0 Test Control Register
C0CLKR
C0RFCR
C0RFPCR
C0TFCR
C0TFPCR
C0EIER
C0EIFR
C0RECR
C0TECR
C0ECSR
C0CSSR
C0MSSR
C0MSMR
C0TSR
C0AFSR
C0TCR
Reset Value
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
0000 0101b
00h
0000 0101b
00h
00h
00h
00h
00h
1000 0000b
XXh
1000 0000b
XXh
00h
00h
00h
00h
00h
XXh
1000 0000b
0000 0000b
00h
00h
XXh
XXh
00h
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101
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Rev.1.01
Page 78 of 156
M16C/5M Group, M16C/57 Group
4.2
4. Special Function Registers (SFRs)
Notes on SFRs
4.2.1
Register Settings
Table 4.48 lists Registers with Write-Only Bits and registers whose function differs between reading and
writing. Set these registers with immediate values. Do not use read-modify-write instructions. When
establishing the next value by altering the existing value, write the existing value to the RAM as well as
to the register. Transfer the next value to the register after making changes in the RAM.
Read-modify-write instructions can be used when writing to the no register bits.
Table 4.48
Registers with Write-Only Bits
Address
Register
0249h
UART0 Bit Rate Register
024Bh to 024Ah
0259h
UART0 Transmit Buffer Register
UART1 Bit Rate Register
025Bh to 025Ah
0269h
UART1 Transmit Buffer Register
UART2 Bit Rate Register
026Bh to 026Ah
0299h
UART2 Transmit Buffer Register
UART4 Bit Rate Register
029Bh to 029Ah
02A9h
UART4 Transmit Buffer Register
UART3 Bit Rate Register
02ABh to 02AAh
02B6h
02B8h
Symbol
U0BRG
U0TB
U1BRG
U1TB
U2BRG
U2TB
U4BRG
U4TB
U3BRG
UART3 Transmit Buffer Register
U3TB
I2C0 Control Register 1
S3D0
I2C0 Status Register 0
S10
0303h to 0302h
Timer A1-1 Register
TA11
0305h to 0304h
Timer A2-1 Register
TA21
0307h to 0306h
Timer A4-1 Register
TA41
030Ah
Three-Phase Output Buffer Register 0
IDB0
030Bh
Three-Phase Output Buffer Register 1
IDB1
030Ch
Dead Time Timer
DTT
030Dh
Timer B2 Interrupt Generation Frequency Set Counter
ICTB2
0327h to 0326h
Timer A0 Register
TA0
0329h to 0328h
Timer A1 Register
TA1
032Bh to 032Ah
Timer A2 Register
TA2
032Dh to 032Ch
Timer A3 Register
TA3
032Fh to 032Eh
Timer A4 Register
TA4
037Dh
Watchdog Timer Refresh Register
WDTR
037Eh
Watchdog Timer Start Register
WDTS
D4C9h
CAN1 Receive FIFO Pointer Control Register
C1RFPCR
D4CBh
CAN1 Transmit FIFO Pointer Control Register
C1TFPCR
D7C9h
CAN0 Receive FIFO Pointer Control Register
C0RFPCR
D7CBh
CAN0 Transmit FIFO pointer Control Register
C0TFPCR
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 79 of 156
M16C/5M Group, M16C/57 Group
Table 4.49
4. Special Function Registers (SFRs)
Read-Modify-Write Instructions
Function
Transfer
Bit processing
Shifting
Mnemonic
Arithmetic operation
Decimal operation
Logical operation
Jump
REJ03B0267-0101
Jul 23, 2010
MOVDir
BCLR, BMCnd, BNOT, BSET, BTSTC, and BTSTS
ROLC, RORC, ROT, SHA, and SHL
ABS, ADC, ADCF, ADD, DEC, DIV, DIVU, DIVX, EXTS, INC, MUL, MULU, NEG,
SBB, and SUB
DADC, DADD, DSBB, and DSUB
AND, NOT, OR, and XOR
ADJNZ, SBJNZ
Rev.1.01
Page 80 of 156
M16C/5M Group, M16C/57 Group
5.
5. Electrical Characteristics
Electrical Characteristics
J-Version
5.1
Electrical Characteristics (J-Version, Common to 3 V and 5 V)
5.1.1
Table 5.1
Absolute Maximum Rating
Absolute Maximum Ratings
Symbol
Characteristic
Condition
Value
Unit
VCC
Supply voltage
VCC = AVCC
-0.3 to 6.5
V
AVCC
Analog supply voltage
VCC = AVCC
-0.3 to 6.5
V
VREF
Analog reference voltage
−0.3 to VCC + 0.1 (1)
V
VI
P0_0 to P0_7, P1_0 to
P1_7, P2_0 to P2_7, P3_0
to P3_7, P4_0 to P4_7,
P5_0 to P5_7, P6_0 to
Input voltage
P6_7, P7_0 to P7_7, P8_0
to P8_7, P9_0 toP9_7,
P10_0 to P10_7
XIN, RESET, CNVSS,
VREF
-0.3 to VCC + 0.3
V
P0_0 to P0_7, P1_0 to
P1_7, P2_0 to P2_7, P3_0
to P3_7, P4_0 to P4_7,
P5_0 to P5_7, P6_0 to
P6_7, P7_0 to P7_7, P8_0
to P8_7, P9_0 to P9_7,
P10_0 to P10_7
XOUT
-0.3 to VCC + 0.3
V
300
mW
VO
Output
voltage
Pd
Power
consumption
Topr
While CPU operation
Operating
temperature While flash memory
program and erase
range
operation
Tstg
Storage temperature range
-40°C ≤ Topr ≤ 85°C
-40 to 85
Programming area
0 to 60
Data area
-40 to 85
-65 to 150
°C
°C
Note:
1. Maximum value is 6.5 V.
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Jul 23, 2010
Rev.1.01
Page 81 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version
5.1.2
Recommended Operating Conditions
Table 5.2
Operating Conditions (1)
VCC = 3.0 V to 5.5 V, Topr = -40°C to 85°C unless otherwise specified.
Symbol
VCC
Min.
Supply voltage
Analog supply voltage
VSS
Ground voltage
AVSS
Analog ground voltage
High level
input voltage
P0_0 to P0_7, P1_0 to P1_7, Input level 0.50 VCC
P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_7, P9_0 to P9_7, Input level 0.70 VCC
P10_0 to P10_7
XIN, RESET, CNVSS
SDAMM, SCLMM
VIL
Typ.
3.0
AVCC
VIH
Value
Characteristic
When
I2C-bus
input level selected
When SMBUS input level selected
P0_0 to P0_7, P1_0 to P1_7, Input level 0.50 VCC
P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, Input level 0.70 VCC
Low level input P8_0 to P8_7, P9_0 to P9_7,
P10_0 to P10_7
voltage
XIN, RESET, CNVSS
SDAMM, SCLMM
Max.
5.5
Unit
V
VCC
V
0
V
0
V
0.7 VCC
VCC
V
0.85VCC
VCC
V
0.8 VCC
VCC
0.7 VCC
VCC
V
2.1
VCC
V
0
0.3 VCC
V
0
0.45VCC
V
0
0.2 VCC
V
When I2C-bus input level selected
0
0.3 VCC
V
When SMBUS input level selected
0
0.8
V
Sum of IOH(peak) at P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
IOH(sum) High peak
to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
output current
P8_0 to P8_4, P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7
-80.0
mA
High level
IOH(peak) peak output
current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to
P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7
-10.0
mA
IOH(avg)
High level
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to
average output P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7
current (1)
-5.0
mA
IOL(sum)
Sum of IOL(peak) at P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
Low peak
to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
output current
P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7
80.0
mA
IOL(peak)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to
Low level peak
P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
output current
P9_0 to P9_7, P10_0 to P10_7
10.0
mA
IOL(avg)
Low level
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to
average output P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7
current (1)
5.0
mA
f(XIN)
Main clock input oscillation frequency (2)
20
MHz
f(XCIN)
Sub clock oscillation oscillator frequency
50
kHz
f(PLL)
PLL clock oscillation frequency (2)
10
32
MHz
f(BCLK)
CPU operation frequency
0
32
MHz
tsu(PLL)
Wait time to stabilize PLL frequency synthesizer
1
ms
0
32.768
Notes:
1.
The mean output current is the mean value within 100ms.
2.
Refer to Figure 5.1 “Main clock input oscillation frequency, PLL clock oscillation frequency” for the relationship between main
clock oscillation frequency/PLL clock oscillation frequency and supply voltage.
REJ03B0267-0101
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Rev.1.01
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5. Electrical Characteristics
J-Version
Main clock input oscillation frequency
PLL clock oscillation frequency
20.0 MHz
20.0
10.0
0.0
3.0
5.5
Vcc [V] (main clock: no division)
f(XIN) maximum operating frequency [MHz]
f(XIN) maximum operating frequency [MHz]
32.0
32.0 MHz
10.0
0.0
3.0
5.5
Vcc [V] (PLL clock oscillation)
Figure 5.1
Main clock input oscillation frequency, PLL clock oscillation frequency
Table 5.3
Recommended Operating Conditions (2/2) (1)
VCC = 3.0 to 5.5 V, VSS = 0 V, and Topr = -40°C to 85°C unless otherwise specified.
The ripple voltage must not exceed Vr(VCC) and/or dVr(VCC)/dt.
Symbol
Standard
Parameter
Vr(VCC)
Allowable ripple voltage
dVr(VCC)/dt
Ripple voltage falling gradient
Min.
Typ.
Max.
Unit
VCC = 5.0 V
0.5
Vp-p
VCC = 3.0 V
0.3
Vp-p
VCC = 5.0 V
0.3
V/ms
VCC = 3.0 V
0.3
V/ms
Note:
1. The device is operationally guaranteed under these operating conditions.
VCC
Figure 5.2
Vr( VCC )
Ripple Waveform
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 83 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version
5.1.3
A/D Conversion Characteristics
Table 5.4
A/D Conversion Characteristics (1)
VCC = AVCC = VREF = 3.0 to 5.5 V, VSS = AVSS = 0 V at Topr = -40°C to 85°C unless otherwise specified.
Symbol
Parameter
Standard
Min.
Typ.
VREF = VCC
—–
Resolution
INL
Integral Non-Linearity Error
—–
Absolute Accuracy
φAD
Measuring Condition
Unit
10
Bits
VREF = VCC = 5.0 V (2)
±3
LSB
(2)
±5
LSB
VREF = VCC = 5.0 V (2)
±3
LSB
VREF = VCC = 3.3 V (2)
±5
LSB
VREF = VCC = 3.3 V
A/D operating clock frequency
Max.
4.0 V ≤ VCC ≤ 5.5 V
2
25
MHz
3.2 V ≤ VCC ≤ 4.0 V
2
16
MHz
3.0 V ≤ VCC ≤ 3.2 V
2
10
MHz
—–
Tolerance Level Impedance
DNL
Differential Non-Linearity Error
(2)
±1
LSB
—–
Offset Error
(2)
±3
LSB
—–
Gain Error
(2)
±3
LSB
10-bit Conversion Time
VREF = VCC = 5V,
φAD = 25 MHz
tCONV
tSAMP
VREF
VIA
3
Sampling time
kΩ
μs
1.60
μs
0.6
Reference Voltage
Analog Input Voltage
(3)
3.0
VCC
V
0
VREF
V
Notes:
1. Use when AVCC = VCC
2. Flash memory rewrite disabled. Except for the analog input pin, set the pins to be measured as input
ports and connect them to VSS. See Figure 5.3 “A/D Accuracy Measure Circuit”.
3. When analog input voltage is over reference voltage, the result of A/D conversion is 3FFh.
AN
Analog input
P0 to P10
Figure 5.3
AN: One of the analog input pin
P0 to P10: I/O pins other than AN
A/D Accuracy Measure Circuit
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 84 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version
5.1.4
D/A Conversion Characteristics
Table 5.5
D/A Conversion Characteristics
VCC = AVCC = VREF = 3.0 to 5.5 V, VSS = AVSS = 0 V at Topr = -40°C to 85°C unless otherwise specified.
Symbol
Parameter
-
Resolution
-
Absolute Accuracy
tSU
Setup Time
RO
Output Resistance
IVREF
Reference Power Supply Input Current
Measuring Condition
Standard
Min.
5
See Notes 1 and 2
Typ.
6
Max.
Unit
8
Bits
2.5
LSB
3
μs
8.2
kΩ
1.5
mA
Notes:
1. This applies when using one D/A converter, with the D/A register for the unused D/A converter set to 00h.
2. The current consumption of the A/D converter is not included. Also, the IVREF of the D/A converter will flow even
if the ADSTBY bit in the ADCON1 register is 0 (A/D operation stopped (standby)).
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 85 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version
5.1.5
Flash Memory Electrical Characteristics
Table 5.6
CPU Clock When Operating Flash Memory (f(BCLK))
VCC = 3.0 to 5.5 V at Topr = -40°C to 85°C, unless otherwise specified.
Symbol
Parameter
-
CPU rewrite mode
f(SLOW_R)
Slow read mode
-
Low current consumption read mode
Data flash read
Conditions
Standard
Min.
Typ.
Max.
16 (1)
(3)
fC
5
35
20
(2)
Unit
MHz
MHz
kHz
MHz
Notes:
1. Set the PM17 bit in the PM1 register to 1 (one wait).
2. When the frequency is over this value, set the FMR17 bit in the FMR1 register to 0 (one wait) or the PM17 bit in
the PM1 register to 1 (one wait)
3. Set the PM17 bit in the PM1 register to 1 (one wait). When using the 125 kHz on-chip oscillator clock or sub
clock as the CPU clock source, a wait is not necessary.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 86 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version
Table 5.7
Flash Memory (Program ROM 1, 2) Electrical Characteristics
VCC = 3.0 to 5.5 V at Topr = 0°C to 60°C, unless otherwise specified.
Symbol
Parameter
Conditions
Standard
Unit
Typ.
Max.
VCC = 3.3 V, Topr = 25°C
150
4000
μs
Lock bit program time
VCC = 3.3 V, Topr = 25°C
70
3000
μs
-
Block erase time
VCC = 3.3 V, Topr = 25°C
0.2
3.0
s
td(SR-SUS)
Time delay from suspend request
until suspend
3 5 + --------------f ( BCLK )
ms
-
Program/erase cycles (1, 3, 4)
Two words program time
VCC = 3.3 V, Topr = 25°C
Min.
-
Interval from erase start/restart
until following suspend request
0
-
Suspend interval necessary for
auto-erasure to complete (7)
20
-
Time from suspend until erase
restart
-
Program, erase voltage
-
Read voltage
Topr = -40°C to 85°C
-
Program, erase temperature
tPS
Flash Memory Circuit Stabilization Wait Time
-
Data hold time (6)
μs
ms
1 30 + --------------f ( BCLK )
μs
3.0
5.5
V
3.0
5.5
V
0
Ambient temperature = 55°C
times
1,000 (2)
20
60
°C
50
μs
year
Notes:
1. Definition of program and erase cycles:
The program and erase cycles refer to the number of per-block erasures. If the program and erase cycles are n
(n = 1,000), each block can be erased n times. For example, if a 64 Kbyte block is erased after writing two word
data 16,384 times, each to a different address, this counts as one program and erase cycles. Data cannot be
written to the same address more than once without erasing the block (rewrite prohibited).
2. Cycles to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
3. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing
to sequential addresses in turn so that as much of the block as possible is used up before performing an erase
operation. It is advisable to retain data on the erasure cycles of each block and limit the number of erase
operations to a certain number.
4. If an error occurs during block erase, attempt to execute the clear status register command, then execute the
block erase command at least three times until the erase error does not occur.
5. Customers desiring program/erase failure rate information should contact a Renesas Electronics sales office.
6. The data hold time includes time that the power supply is off or the clock is not supplied.
7. After an erase start or erase restart, if an interval of at least 20 ms is not set before the next suspend request, the
erase sequence cannot be completed.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 87 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version
Table 5.8
Flash Memory (Data Flash) Electrical Characteristics
VCC = 3.0 to 5.5 V at Topr = -40°C to 85°C, unless otherwise specified.
Symbol
Parameter
Conditions
Standard
Min.
Typ.
Max.
Unit
-
Program/erase cycles (1, 3, 4)
VCC = 3.3 V, Topr = 25°C
-
Two words program time
VCC = 3.3 V, Topr = 25°C
300
4000
μs
-
Lock bit program time
VCC = 3.3 V, Topr = 25°C
140
3000
μs
-
Block erase time
VCC = 3.3 V, Topr = 25°C
0.2
3.0
s
3 5 + --------------f ( BCLK )
ms
td(SR-SUS)
10,000 (2)
Time delay from suspend request
until suspend
-
Interval from erase start/restart until
following suspend request
0
-
Suspend interval necessary for
auto-erasure to complete (7)
20
-
Time from suspend until erase
restart
-
Program, erase voltage
times
μs
ms
1 30 + --------------f ( BCLK )
μs
3.0
5.5
V
-
Read voltage
3.0
5.5
V
-
Program, erase temperature
−40
85
°C
tPS
Flash memory circuit stabilization wait time
50
μs
-
Data hold time (6)
1.
2.
3.
4.
5.
6.
7.
Ambient temperature = 55°C
20
year
Definition of program and erase cycles
The program and erase cycles refer to the number of per-block erasures.
If the program and erase cycles are n (n = 10,000), each block can be erased n times.
For example, if a 4 Kbyte block is erased after writing two word data 1,024 times, each to a different address, this
counts as one program and erase cycles. Data cannot be written to the same address more than once without
erasing the block (rewrite prohibited).
Cycles to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
In a system that executes multiple programming operations, the actual erasure count can be reduced by writing
to sequential addresses in turn so that as much of the block as possible is used up before performing an erase
operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be
minimized by programming up to 256 groups before erasing them all in one operation. In addition, averaging the
erasure cycles between blocks A and B can further reduce the actual erasure cycles. It is also advisable to retain
data on the erasure cycles of each block and limit the number of erase operations to a certain number.
If an error occurs during block erase, attempt to execute the clear status register command, then execute the
block erase command at least three times until the erase error does not occur.
Customers desiring program/erase failure rate information should contact a Renesas Electronics sales office.
The data hold time includes time that the power supply is off or the clock is not supplied.
After an erase start or erase restart, if an interval of at least 20 ms is not set before the next suspend request,
the erase sequence cannot be completed.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 88 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version
5.1.6
E2PROM Emulation Data Flash
Table 5.9
E2PROM Emulation Data Flash Electrical Characteristics
VCC = 3.0 to 5.5 V, VSS = 0 V, and Topr = -40°C to 85°C unless otherwise specified.
Symbol
Characteristic
—
Program/erase cycles (1)
—
Word program time (2-byte program)
—
Read time (2-byte read)
Value
Min.
Typ.
Max.
100000
—
Block erase time (32-byte block)
tPS
Flash memory circuit stabilization wait time
(sleep mode to normal mode)
—
Data hold time (2)
Ambient temperature = 55°C (3, 4)
times
100
15
20
Unit
2000
µs
1
µs
200
ms
50
µs
years
Notes:
1. Definition of program/erase cycles definition
This value represents the number of erasure per block.
If the flash memory is programmed/erased n times, each block can be erased n times.
i.e. If a word write is performed in different 16 addresses in a block and then the block is erased, it
is considered the programming/erasure is performed just once. However a write in the same
address more than once for one erasure is disabled. (overwrite disabled).
2. The data hold time includes the periods when the supply voltage is not applied and no clock is
provided.
3. This data hold time includes (7000) hours in Ambient temperature = 85°C.
4. Please contact a Renesas Electronics sales office regarding data retention time other than the
above.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 89 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version
5.1.7
Voltage Detector and Power Supply Circuit Electrical Characteristics
Table 5.10
Voltage Detector 0 Electrical Characteristics
The measurement condition is VCC = 3.0 to 5.5 V, Topr = -40°C to 85°C, unless otherwise specified.
Symbol
Parameter
Condition
Vdet0
Voltage detection level Vdet0
When VCC is falling.
td(E-A)
Waiting time until voltage detector operation
starts (1)
VCC = 3.0 to 5.0 V
Standard
Unit
Min.
Typ.
Max.
2.70
2.85
3.00
V
100
μs
Note:
1.
Necessary time until the voltage detector operates when setting to 1 again after setting the VC25 bit in the VCR2
register to 0.
Table 5.11
Voltage Detector 2 Electrical Characteristics
The measurement condition is VCC = 3.0 to 5.5 V, Topr = -40°C to 85°C, unless otherwise specified.
Symbol
Vdet2_0
Parameter
Condition
Standard
Min.
Voltage detection level Vdet2_0
Typ.
Max.
Unit
3.21
V
Vdet2_1
Voltage detection level Vdet2_1
3.36
V
Vdet2_2
Voltage detection level Vdet2_2
3.51
V
Vdet2_3
Voltage detection level Vdet2_3
Vdet2_4
Voltage detection level Vdet2_4
Vdet2_5
Voltage detection level Vdet2_5
3.96
V
Vdet2_6
Voltage detection level Vdet2_6
4.10
V
Vdet2_7
Voltage detection level Vdet2_7
4.25
V
-
Hysteresis width at the rising of VCC in voltage
detector 2
0.15
V
td(E-A)
Waiting time until voltage detector operation starts (1) VCC = 3.0 to 5.0 V
When VCC is falling
3.66
3.51
3.81
V
4.11
100
V
μs
Note:
1.
Necessary time until the voltage detector operates after setting to 1 again after setting the VC27 bit in the VCR2
register to 0.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 90 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version
Table 5.12
Power-On Reset Circuit
The measurement condition is Topr = -40°C to 85°C, unless otherwise specified.
Symbol
Parameter
trth
External power VCC rise gradient
tfth
External power VCC fall gradient
Condition
Standard
Min.
Typ.
2.0
Max.
Unit
50000 mV/ms
50000 mV/ms
Vpor
Voltage at which power-on reset enabled
tw(por)
Hold time at which power-on reset enabled
(1)
0.1
V
1.0
ms
Note:
1. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS1 address
to 0.
Vdet0
External Power VCC
Vdet0
t rth
t rth
t fth
Vpor
tw(por)
Internal
reset signal
1
1
× 128
Figure 5.4
Power-On Reset Circuit Electrical Characteristics
Table 5.13
Power Supply Circuit Timing Characteristics
Symbol
Parameter
td(P-R)
Time for Internal Power Supply Stabilization
During Powering-On
td(R-S)
STOP Release Time
td(W-S)
Low Power Mode Wait Mode Release Time
× 128
fOCO-S
fOCO-S
Measuring Condition
VCC = 3.0 V to 5.5V
Standard
Min.
Typ.
Max.
Unit
5
ms
300
μs
300
μs
Note:
1. When VCC = 5 V.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 91 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version
Recommended
operating
voltage
t d(P-R)
VCC
Time to stabilize internal supply
voltage during powering-on
td(P-R)
CPU clock
(a) Interrupt to exit from stop mode
(b) Interrupt to exit from wait mode
t d(R-S)
STOP release time
t d(W-S)
Low power consumption
mode wait mode exit time
CPU clock
(a)
(b)
t d(E-A)
Voltage detection circuit
operation start time
td(R-S)
td(W-S)
VC25, VC27
Voltage detection circuit
Stop
Operate
td(E-A)
Figure 5.5
5.1.8
Power Supply Circuit Timing Diagram
Oscillation Circuit Electrical Characteristics
Table 5.14
On-chip Oscillator Oscillation Circuit Electrical Characteristics
VCC = 3.0 to 5.5 V, Topr = −40°C to 85°C, unless otherwise specified
Symbol
Characteristic
Value
Unit
Min.
Typ.
Max.
fOCO-S
125 kHz on-chip oscillator oscillation frequency
100
125
150
kHz
fOCO40M
40 MHz on-chip oscillator oscillation frequency
32
40
48
MHz
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 92 of 156
M16C/5M Group, M16C/57 Group
5.2
5. Electrical Characteristics
Electrical Characteristics (J-Version, VCC = 5 V)
5.2.1
Electrical Characteristics
J-Version, VCC = 5 V
Table 5.15
Electrical Characteristics (1)
VCC = 4.2 to 5.5 V, VSS = 0 V at Topr = -40°C to 85°C, f(BCLK) = 32 MHz unless otherwise specified.
Symbol
Parameter
Measuring Condition
Standard
Min.
Typ.
Max.
Unit
VOH
HIGH Output Voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7
IOH=−5 mA
VCC−2.0
VCC
V
VOH
HIGH Output Voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6 to P8_7,P9_0 to P9_7, P10_0 to P10_7
IOH = −200 μA
VCC−−0.3
VCC
V
HIGH Output Voltage
VOH
HIGH Output Voltage
VOL
VOL
HIGH POWER
IOH = −1 mA
VCC−−2.0
VCC
LOW POWER
IOH = −0.5 mA
VCC−−2.0
VCC
XOUT
XCOUT
HIGH POWER
With no load applied
2.5
LOW POWER
With no load applied
1.6
V
V
LOW Output Voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7
IOL = 5 mA
2.0
V
LOW Output Voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7
IOL = 200 μA
0.45
V
HIGH POWER
IOL = 1 mA
2.0
LOW POWER
IOL = 0.5 mA
2.0
LOW Output Voltage
XOUT
VOL
LOW Output Voltage
XCOUT
V
HIGH POWER
With no load applied
0
LOW POWER
With no load applied
0
VT+-VT-
Hysteresis
TA0IN to TA4IN, TB0IN to TB5IN, INT0 to INT7,
NMI, ADTRG, CTS0 to CTS3, SCL2, SDA2,
CLK0 to CLK4, TA0OUT to TA4OUT,
KI0 to KI3, RXD0 to RXD4, ZP, IDU, IDW, IDV,
SD, INPC1_0 to INPC1_7, SSI0, SSCK0, SCS0,
LIN0IN, CRX0, CRX1
V
0.2
0.4VCC
V
VT+-VT-
Hysteresis
RESET
0.2
2.5
V
VT+-VT-
Hysteresis
XIN
0.2
0.8
V
IIH
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
HIGH Input Current P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7
XIN, RESET, CNVSS
VI = 5 V
5.0
μA
IIL
LOW Input Current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7
XIN, RESET, CNVSS
VI = 0 V
−5.0
μA
RPULLUP
Pull-Up
Resistance
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7
VI = 0 V
170
kΩ
RfXIN
Feedback Resistance XIN
1.5
MΩ
RfXCIN
Feedback Resistance XCIN
15
MΩ
VRAM
RAM Retention Voltage
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
At stop mode
30
2.0
50
V
Page 93 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version, VCC = 5 V
Table 5.16
Electrical Characteristics (2)
Topr = −40°C to 85°C unless otherwise specified.
Symbol
Parameter
Measuring Condition
High speed mode
ICC
Wait mode
Stop mode
Unit
Typ.
Max.
f(BCLK) = 32 MHz,
XIN = 8 MHz (square wave), PLL multiply-by-8
125 kHz on-chip oscillator operates
25
45
mA
f(BCLK) = 20 MHz,
XIN = 20 MHz (square wave),
125 kHz on-chip oscillator operates
21
39
mA
f(BCLK) = 16 MHz,
XIN = 16 MHz (square wave),
125 kHz on-chip oscillator operates
17
Main clock stops
40 MHz on-chip oscillator operates
125 kHz on-chip oscillator operates
40 MHz on-chip oscillator No division
mode
Main clock stops
40 MHz on-chip oscillator operates
125 kHz on-chip oscillator operates
Divide-by-8
Power Supply
Current
(VCC = 4.2V to 5.5 125 kHz on-chip oscillator
mode
V)
In single-chip
mode, the output
pins are open and
other pins are
Low power mode
VSS
Standard
Main clock stops
40 MHz on-chip oscillator stops
125 kHz on-chip oscillator operates
Divide-by-8
FMR22 = FMR23 = 1 (Low-current
consumption read mode)
Min.
mA
21
39
6
mA
mA
190
580
μA
f(BCLK) = 32 kHz
On Flash memory (2)
FMR22 = FMR23 = 1 (Low-current
consumption read mode)
200
μA
Main clock stops
40 MHz on-chip oscillator stops
125 kHz on-chip oscillator operates
Peripheral clock operates
Topr = 25°C
25
μA
Main clock stops
40 MHz on-chip oscillator stops
125 kHz on-chip oscillator operates
Peripheral clock operates
Topr = 85°C
55
μA
Topr = 25°C
3
Topr = 85°C
30
μA
15
μA
During flash memory
program
f(BCLK) = 10 MHz, PM17 = 1 (one wait)
VCC = 5.0 V
20.0
mA
During flash memory
erase
f(BCLK) = 10 MHz, PM17 = 1 (one wait)
VCC = 5.0 V
30.0
mA
Idet2
Low Voltage Detection Dissipation Current
3
μA
Idet0
Reset Area Detection Dissipation Current
6
μA
Note:
1.
This indicates the memory in which the program to be executed exists.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 94 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version, VCC = 5 V
5.2.2
Timing Requirements (Peripheral Functions and Others)
(VCC = 5 V, VSS = 0 V, at Topr = -40°C to 85°C unless otherwise specified)
5.2.2.1
Reset Input (RESET Input)
Table 5.17
Reset Input (RESET Input)
Symbol
Standard
Parameter
Min.
RESET input low pulse width
tw(RSTL)
Max.
10
Unit
μs
RESET input
t w(RTSL)
Figure 5.6
5.2.2.2
Table 5.18
Reset Input (RESET Input)
External Clock Input
External Clock Input (XIN Input) (1)
Symbol
tc
tw(H)
tw(L)
tr
tf
Standard
Min.
Max.
50
20
20
9
9
Parameter
External clock input cycle time
External clock input high pulse width
External clock input low pulse width
External clock rise time
External clock fall time
Unit
ns
ns
ns
ns
ns
Note:
1. The condition is VCC = 5.0V.
XIN input
tr
t w(H)
tf
t w(L)
tc
Figure 5.7
External Clock Input (XIN Input)
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 95 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version, VCC = 5 V
Timing Requirements
(VCC = 5 V, VSS = 0 V, at Topr = −40°C to 85°C unless otherwise specified)
5.2.2.3
Table 5.19
Timer A Input
Timer A Input (Counter Input in Event Counter Mode)
Symbol
Standard
Min.
Max.
Parameter
Unit
tc(TA)
TAiIN input cycle time
100
ns
tw(TAH)
TAiIN input high pulse width
40
ns
tw(TAL)
TAiIN input low pulse width
40
ns
Table 5.20
Timer A Input (Gating Input in Timer Mode)
Symbol
Standard
Min.
Max.
Parameter
Unit
tc(TA)
TAiIN input cycle time
400
ns
tw(TAH)
TAiIN input high pulse width
200
ns
tw(TAL)
TAiIN input low pulse width
200
ns
Table 5.21
Timer A Input (External Trigger Input in One-shot Timer Mode)
Symbol
Standard
Min.
Max.
Parameter
Unit
tc(TA)
TAiIN input cycle time
200
ns
tw(TAH)
TAiIN input high pulse width
100
ns
tw(TAL)
TAiIN input low pulse width
100
ns
Table 5.22
Timer A Input (External Trigger Input in PWM Mode, Programmable Output Mode)
Symbol
Standard
Min.
Max.
Parameter
Unit
tw(TAH)
TAiIN input high pulse width
100
ns
tw(TAL)
TAiIN input low pulse width
100
ns
tc(TA)
t w(TAH)
TAiIN input
t w(TAL)
tc(UP)
t w(UPH)
TAiOUT input
t w(UPL)
Figure 5.8
Timer A Input
REJ03B0267-0101
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Rev.1.01
Page 96 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version, VCC = 5 V
Timing Requirements
(VCC = 5 V, VSS = 0 V, at Topr = −40°C to 85°C unless otherwise specified)
Table 5.23
Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Symbol
Standard
Min.
Max.
Parameter
Unit
tc(TA)
TAiIN input cycle time
800
ns
tsu(TAIN-TAOUT)
TAiOUT input setup time
200
ns
tsu(TAOUT-TAIN)
TAiIN input setup time
200
ns
Two-phase pulse input in event counter mode
tc(TA)
TAiIN input
tsu(TAIN-TAOUT)
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
TAiOUT input
tsu(TAOUT-TAIN)
Figure 5.9
Timer A Input (Two-Phase Pulse Input in Event Counter Mode)
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 97 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version, VCC = 5 V
Timing Requirements
(VCC = 5 V, VSS = 0 V, at Topr = −40°C to 85°C unless otherwise specified)
5.2.2.4
Table 5.24
Timer B Input
Timer B Input (Counter Input in Event Counter Mode)
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time (counted on one edge)
100
ns
tw(TBH)
TBiIN input high pulse width (counted on one edge)
40
ns
tw(TBL)
TBiIN input low pulse width (counted on one edge)
40
ns
tc(TB)
TBiIN input cycle time (counted on both edges)
200
ns
tw(TBH)
TBiIN input high pulse width (counted on both edges)
80
ns
tw(TBL)
TBiIN Input low pulse width (counted on both edges)
80
ns
Table 5.25
Timer B Input (Pulse Period Measurement Mode)
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time
400
ns
tw(TBH)
TBiIN input high pulse width
200
ns
tw(TBL)
TBiIN input low pulse width
200
ns
Table 5.26
Timer B Input (Pulse Width Measurement Mode)
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time
400
ns
tw(TBH)
TBiIN input high pulse width
200
ns
tw(TBL)
TBiIN input low pulse width
200
ns
tc(TB)
t w(TBH)
TBiIN input
t w(TBL)
Figure 5.10
Timer B Input
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 98 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version, VCC = 5 V
Timing Requirements
(VCC = 5 V, VSS = 0 V, at Topr = −40°C to 85°C unless otherwise specified)
5.2.2.5
Table 5.27
Timer S Input
Timer S Input (Two-phase Pulse Input in Two-phase Pulse Signal Processing Mode)
Symbol
Standard
Min.
Max.
Parameter
Unit
tw(TSH)
TSUDA, TSUDB input high pulse width
2
μs
tw(TSL)
TSUDA, TSUDB input low pulse width
2
μs
tsu(TSUDA-TSUDB)
TSUDB input setup time
1
μs
tsu(TSUDB-TSUDA)
TSUDA input setup time
1
μs
Two-phase pulse input in two-phase pulse signal processing mode
tw(TSH)
tw(TSL)
TSUDA input
tsu(TSUDA-TSUDB)
tsu(TSUDA-TSUDB)
tw(TSH)
tsu(TSUDB-TSUDA)
tw(TSL)
TSUDB input
tsu(TSUDB-TSUDA)
Note:
1. When the TSUDA and TSUDB phases are interchanged, tsu(TSUDA-TSUDB) and tsu(TSUDB-TSUDA)
are also interchanged.
Figure 5.11
Timer S Input (Two-phase Pulse Input in Two-phase Pulse Signal Processing Mode)
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 99 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version, VCC = 5 V
Timing Requirements
(VCC = 5 V, VSS = 0 V, at Topr = −40°C to 85°C unless otherwise specified)
5.2.2.6
Table 5.28
Serial Interface
Serial Interface
Symbol
Standard
Parameter
Min.
Unit
Max.
tc(CK)
CLKi input cycle time
200
ns
tw(CKH)
CLKi input high pulse width
100
ns
tw(CKL)
CLKi input low pulse width
100
ns
td(C-Q)
TXDi output delay time
th(C-Q)
TXDi hold time
0
ns
tsu(D-C)
RXDi input setup time
70
ns
th(C-D)
RXDi input hold time
90
ns
80
ns
tc(CK)
t w(CKH)
CLKi
t w(CKL)
th(C-Q)
TXDi
td(C-Q)
tsu(D-C)
th(C-D)
RXDi
Figure 5.12
5.2.2.7
Table 5.29
Serial Interface
External Interrupt INTi Input
External Interrupt INTi Input
Symbol
Standard
Parameter
Min.
Max.
Unit
tw(INH)
INTi input high pulse width
250
ns
tw(INL)
INTi input low pulse width
250
ns
t w(INL)
INTi input
t w(INH)
Figure 5.13
External Interrupt INTi Input
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 100 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version, VCC = 5 V
Timing Requirements
(VCC = 5 V, VSS = 0 V, at Topr = −40°C to 85°C unless otherwise specified)
Multi-master I2C-bus
5.2.2.8
Table 5.30
Multi-master I2C-bus
Symbol
Standard Clock Mode
Parameter
Min.
High-speed Clock Mode
Max.
Min.
Max.
Unit
tBUF
Bus free time
4.7
1.3
μs
tHD;STA
Hold time in start condition
4.0
0.6
μs
tLOW
Hold time in SCL clock 0 status
4.7
1.3
μs
tR
SCL, SDA signals’ rising time
tHD;DAT
Data hold time
tHIGH
Hold time in SCL clock 1 status
1000
20 + 0.1 Cb
300
ns
0
0
0.9
μs
4.0
0.6
μs
fF
SCL, SDA signals’ falling time
tsu;DAT
Data setup time
250
100
ns
tsu;STA
Setup time in restart condition
4.7
0.6
μs
tsu;STO
Stop condition setup time
4.0
0.6
μs
300
20 + 0.1 Cb
300
ns
SDA
t HD;STA
t BUF
SCL
p
t LOW
t HD;STA
Figure 5.14
tR
tF
Sr
s
t HD;DTA
t HIGH
t su;DTA
t su;STO
p
t su;STA
Multi-master I2C-bus
REJ03B0267-0101
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Rev.1.01
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M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version, VCC = 5 V
Timing Requirements
(VCC = 5 V, VSS = 0 V, at Topr = −40°C to 85°C unless otherwise specified)
5.2.2.9
Table 5.31
Serial bus interface
Serial Bus Interface
Symbol
tc(SSCK)
Measurement
condition
Characteristic
Value
Min.
Typ.
Max.
Unit
SSCK clock cycle time
250
tw(SSCKH)
SSCK clock high pulse width
0.4
0.6
tc(SSCK)
tw(SSCKL)
SSCK clock low pulse width
0.4
0.6
tc(SSCK)
Master
1
tCYC (1)
Slave
1
μs
Master
1
tCYC (1)
Slave
1
μs
tr(SSCK)
SSCK clock rising time
tf(SSCK)
SSCK clock falling time
tsu(SSIO-SSCK) SSO, SSI data input setup time
th(SSCK-SSIO)
100
ns
1
tCYC (1)
Slave
1 tCYC + 50 (1)
ns
Slave
1 tCYC + 50 (1)
ns
SSO, SSI data input hold time
tsu(SCS-SSCK) SCS setup time
ns
th(SSCK-SCS)
SCS hold time
td(SSCK-SSIO)
SS0, SSI data output delay time
1
tCYC (1)
ten(SCS-SSI)
SSI output enable time
3.0 V ≤ VCC ≤ 5.5 V
1.5 tCYC + 100 (1)
ns
tdis(SCS-SSI)
SSI output disable time
3.0 V ≤ VCC ≤ 5.5 V
1.5 tCYC + 100 (1)
ns
Note:
1.
1 tCYC is 1/f1 (s).
REJ03B0267-0101
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M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version, VCC = 5 V
4-Wire Bus Communication Mode, Master, CPHS = 1
VIH or VOH
SCS (output)
VIL or VOL
t w(SSCKH)
t f(SSCK)
t r(SSCK)
SSCK (output)
(CPOS = 1)
t w(SSCKL)
t w(SSCKH)
SSCK (output)
(CPOS = 0)
t c(SSCK)
t w(SSCKL)
SSO (output)
t d(SSCK-SSIO)
SSI (input)
t su(SSIO-SSCK)
t h(SSCK-SSIO)
4-Wire Bus Communication Mode, Master, CPHS = 0
VIH or VOH
SCS (output)
VIL or VOL
t w(SSCKH)
t f(SSCK)
t r(SSCK)
SSCK (output)
(CPOS = 1)
t w(SSCKL)
t w(SSCKH)
SSCK (output)
(CPOS =0)
t w(SSCKL)
t c(SSCK)
SSO (output)
t d(SSCK-SSIO)
SSI (input)
t su(SSIO-SSCK)
t h(SSCK-SSIO)
CPHS, CPOS: Bits in the SSMR register
Figure 5.15
I/O Timing of Serial Bus Interface (Master)
REJ03B0267-0101
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Rev.1.01
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M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version, VCC = 5 V
4-Wire Bus Communication Mode, Slave, CPHS = 1
VIH or VOH
SCS (input)
VIL or VOL
t r(SSCK)
t f(SSCK)
t su(SCS-SSCK) t w(SSCKH)
t h(SSCK-SCS)
SSCK (input)
(CPOS = 1)
t w(SSCKL)
t w(SSCKH)
SSCK (input)
(CPOS = 0)
t c(SSCK)
t w(SSCKL)
SSO (input)
t su(SSIO-SSCK)
t h(SSCK-SSIO)
SSI (output)
t d(SSCK-SSIO)
t en(SCS-SSI)
t dis(SCS-SSI)
4-Wire Bus Communication Mode, Slave, CPHS = 0
SCS (input)
VIH or VOH
VIL or VOL
t su(SCS-SSCK) t w(SSCKH)
t f(SSCK)
t r(SSCK)
t h(SSCK-SCS)
SSCK (input)
(CPOS = 1)
t w(SSCKL)
t w(SSCKH)
SSCK (input)
(CPOS = 0)
t c(SSCK)
t w(SSCKL)
SSO (input)
t su(SSIO-SSCK)
t h(SSCK-SSIO)
SSI (output)
t en(SCS-SSI)
t d(SSCK-SSIO)
t dis(SCS-SSI)
CPHS, CPOS: Bits in the SSMR register
Figure 5.16
I/O Timing of Serial Bus Interface (Slave)
REJ03B0267-0101
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Rev.1.01
Page 104 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version, VCC = 5 V
t w(SSCKH)
VIH or VOH
SSCK
VIL or VOL
t c(SSCK)
t w(SSCKL)
SSO (output)
t d(SSCK-SSIO)
SSI (input)
t su(SSIO-SSCK)
Figure 5.17
t h(SSCK-SSIO)
I/O Timing of Serial Bus Interface (Synchronous Communication Mode)
MCU
Pin to be
measured
Figure 5.18
30 pF
Switching Characteristic Measurement Circuit
REJ03B0267-0101
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Rev.1.01
Page 105 of 156
M16C/5M Group, M16C/57 Group
5.3
5. Electrical Characteristics
Electrical Characteristics (J-Version, VCC = 3 V)
5.3.1
Electrical Characteristics
J-Version, VCC = 3 V
Table 5.32
Electrical Characteristics (1)
VCC = 3.0 to 3.6 V, VSS = 0 V at Topr = −40°C to 85°C, f(BCLK)= 32 MHz unless otherwise specified.
Symbol
VOH
Parameter
P0_0 to P0_7, P1_0 to P1_7, P2_0 to
P2_7, P3_0 to P3_7, P4_0 to P4_7,
P5_0 to P5_7, P6_0 to P6_7, P7_0 to
P7_7, P8_0 to P8_4, P8_6 to P8_7,
P9_0 to P9_7, P10_0 to P10_7
HIGH
Output
Voltage
HIGH Output Voltage
XOUT
HIGH Output Voltage
XCOUT
VOH
VOL
Measuring Condition
LOW Output Voltage
XOUT
LOW Output Voltage
XCOUT
VOL
Typ.
Max.
IOH = −1 mA
VCC−0.5
VCC
HIGH POWER
IOH = −0.1 mA
VCC−0.5
VCC
LOW POWER
IOH = −50 μA
VCC−0.5
VCC
HIGH POWER
With no load applied
2.5
LOW POWER
With no load applied
1.6
P0_0 to P0_7, P1_0 to P1_7, P2_0 to
P2_7, P3_0 to P3_7, P4_0 to P4_7,
P5_0 to P5_7, P6_0 to P6_7, P7_0 to
P7_7, P8_0 to P8_7, P9_0 to P9_7,
P10_0 to P10_7
LOW
Output
Voltage
Standard
Min.
0.5
HIGH POWER
IOL = 0.1mA
0.5
LOW POWER
IOL = 50μA
0.5
With no load applied
0
LOW POWER
With no load applied
0
VT+-VT-
Hysteresis
TA0IN to TA4IN, TB0IN to TB5IN, INT0
to INT7, NMI, ADTRG, CTS0 to CTS3,
SCL2, SDA2, CLK0 to CLK4, TA0OUT
to TA4OUT, KI0 to KI3, RXD0 to RXD4,
ZP, IDU, IDW, IDV, SD, INPC1_0 to
INPC1_7, SSI0, SSCK0, SCS0, LIN0IN,
CRX0, CRX1
VT+-VT-
Hysteresis
VT+-VT-
V
V
V
IOL = 1mA
HIGH POWER
Unit
V
V
V
0.4VCC
V
RESET
1.8
V
Hysteresis
XIN
0.8
V
HIGH Input
Current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to
P2_7, P3_0 to P3_7, P4_0 to P4_7,
P5_0 to P5_7, P6_0 to P6_7, P7_0 to
P7_7, P8_0 to P8_7, P9_0 to P9_7,
P10_0 to P10_7
XIN, RESET, CNVSS
VI = 3V
4.0
μA
IIL
LOW Input
Current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to
P2_7, P3_0 to P3_7, P4_0 to P4_7,
P5_0 to P5_7, P6_0 to P6_7, P7_0 to
P7_7, P8_0 to P8_7, P9_0 to P9_7,
P10_0 to P10_7
XIN, RESET, CNVSS
VI = 0V
−4.0
μA
RPULLUP
Pull-Up
Resistance
P0_0 to P0_7, P1_0 to P1_7, P2_0 to
P2_7, P3_0 to P3_7, P4_0 to P4_7,
P5_0 to P5_7, P6_0 to P6_7, P7_0 to
P7_7, P8_0 to P8_4, P8_6 to P8_7,
P9_0 to P9_7, P10_0 to P10_7
VI = 0V
500
kΩ
RfXIN
Feedback Resistance XIN
RfXCIN
Feedback Resistance XCIN
VRAM
RAM Retention Voltage
IIH
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
At stop mode
50
2.0
100
3.0
MΩ
25
MΩ
V
Page 106 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version, VCC = 3 V
Table 5.33
Electrical Characteristics (2)
Topr = −40°C to 85°C unless otherwise specified.
Symbol
Parameter
Measuring Condition
High speed mode
Max.
f(BCLK) = 32 MHz,
XIN = 8 MHz (square wave), PLL multiply-by-8
125 kHz on-chip oscillator operates
23
43
mA
f(BCLK) = 20 MHz,
XIN = 20 MHz (square wave),
125 kHz on-chip oscillator operates
20
38
mA
f(BCLK) = 16 MHz,
XIN = 16 MHz (square wave),
125 kHz on-chip oscillator operates
16
ICC
Wait mode
Stop mode
Main clock stops
40 MHz on-chip oscillator stops
125 kHz on-chip oscillator operates
Divide-by-8
FMR22 = FMR23 = 1 (Low-current
consumption read mode)
Min.
Unit
Typ.
Main clock stops
40 MHz on-chip oscillator operates
125 kHz on-chip oscillator operates
40 MHz on-chip oscillator No division
mode
Main clock stops
40 MHz on-chip oscillator operates
125 kHz on-chip oscillator operates
Divide-by-8
Power Supply
Current
125 kHz on-chip oscillator
(VCC = 3.0 V to 3.6 mode
V)
In single-chip
mode, the output
pins are open and
other pins are
Low power mode
VSS
Standard
20
mA
38
6
190
mA
mA
580
μA
f(BCLK) = 32 kHz
On Flash memory (1)
FMR22 = FMR23 = 1 (Low-current
consumption read mode)
200
μA
Main clock stops
40 MHz on-chip oscillator stops
125 kHz on-chip oscillator operates
Peripheral clock operates
Topr = 25°C
25
μA
Main clock stops
40 MHz on-chip oscillator stops
125 kHz on-chip oscillator operates
Peripheral clock operates
Topr = 85°C
55
μA
Topr = 25°C
2
Topr = 85°C
30
μA
12
μA
During flash memory
program
f(BCLK) = 10 MHz, PM17 = 1 (one wait)
VCC = 3.0 V
20.0
mA
During flash memory
erase
f(BCLK) = 10 MHz, PM17 = 1 (one wait)
VCC = 3.0 V
30.0
mA
Idet2
Low Voltage Detection Dissipation Current
3
μA
Idet0
Reset Area Detection Dissipation Current
6
μA
Note:
1.
This indicates the memory in which the program to be executed exists.
REJ03B0267-0101
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M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version, VCC = 3 V
5.3.2
Timing Requirements (Peripheral Functions and Others)
(VCC = 3 V, VSS = 0 V, at Topr = −40°C to 85°C unless otherwise specified)
5.3.2.1
Reset Input (RESET Input)
Table 5.34
Reset Input (RESET Input)
Symbol
Standard
Parameter
Min.
RESET input low pulse width
tw(RSTL)
Max.
10
Unit
μs
RESET input
t w(RTSL)
Figure 5.19
5.3.2.2
Table 5.35
Reset Input (RESET Input)
External Clock Input
External Clock Input (XIN input) (1)
Symbol
tc
tw(H)
tw(L)
tr
tf
Standard
Min.
Max.
50
20
20
9
9
Parameter
External clock input cycle time
External clock input high pulse width
External clock input low pulse width
External clock rise time
External clock fall time
Unit
ns
ns
ns
ns
ns
Note:
1. The condition is VCC = 3.0V.
XIN input
tr
t w(H)
tf
t w(L)
tc
Figure 5.20
External Clock Input (XIN Input)
REJ03B0267-0101
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M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version, VCC = 3 V
Timing Requirements
(VCC = 3 V, VSS = 0 V, at Topr = −40°C to 85°C unless otherwise specified)
5.3.2.3
Table 5.36
Timer A Input
Timer A Input (Counter Input in Event Counter Mode)
Symbol
Standard
Min.
Max.
Parameter
Unit
tc(TA)
TAiIN input cycle time
150
ns
tw(TAH)
TAiIN input high pulse width
60
ns
tw(TAL)
TAiIN input low pulse width
60
ns
Table 5.37
Timer A Input (Gating Input in Timer Mode)
Symbol
Standard
Min.
Max.
Parameter
Unit
tc(TA)
TAiIN input cycle time
600
ns
tw(TAH)
TAiIN input high pulse width
300
ns
tw(TAL)
TAiIN input low pulse width
300
ns
Table 5.38
Timer A Input (External Trigger Input in One-shot Timer Mode)
Symbol
Standard
Min.
Max.
Parameter
Unit
tc(TA)
TAiIN input cycle time
300
ns
tw(TAH)
TAiIN input high pulse width
150
ns
tw(TAL)
TAiIN input low pulse width
150
ns
Table 5.39
Timer A Input (External Trigger Input in PWM Mode, Programmable Output Mode)
Symbol
Standard
Min.
Max.
Parameter
Unit
tw(TAH)
TAiIN input high pulse width
150
ns
tw(TAL)
TAiIN input low pulse width
150
ns
tc(TA)
t w(TAH)
TAiIN input
t w(TAL)
tc(UP)
t w(UPH)
TAiOUT input
t w(UPL)
Figure 5.21
Timer A Input
REJ03B0267-0101
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M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version, VCC = 3 V
Timing Requirements
(VCC = 3 V, VSS = 0 V, at Topr = −40°C to 85°C unless otherwise specified)
Table 5.40
Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Symbol
Standard
Min.
Max.
Parameter
Unit
tc(TA)
TAiIN input cycle time
2
μs
tsu(TAIN-TAOUT)
TAiOUT input setup time
500
ns
tsu(TAOUT-TAIN)
TAiIN input setup time
500
ns
Two-phase pulse input in event counter mode
tc(TA)
TAiIN input
tsu(TAIN-TAOUT)
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
TAiOUT input
tsu(TAOUT-TAIN)
Figure 5.22
Timer A Input (Two-Phase Pulse Input in Event Counter Mode)
REJ03B0267-0101
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M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version, VCC = 3 V
Timing Requirements
(VCC = 3 V, VSS = 0 V, at Topr = −40°C to 85°C unless otherwise specified)
5.3.2.4
Table 5.41
Timer B Input
Timer B Input (Counter Input in Event Counter Mode)
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time (counted on one edge)
150
ns
tw(TBH)
TBiIN input high pulse width (counted on one edge)
60
ns
tw(TBL)
TBiIN input low pulse width (counted on one edge)
60
ns
tc(TB)
TBiIN input cycle time (counted on both edges)
300
ns
tw(TBH)
TBiIN input high pulse width (counted on both edges)
120
ns
tw(TBL)
TBiIN Input low pulse width (counted on both edges)
120
ns
Table 5.42
Timer B Input (Pulse Period Measurement Mode)
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time
600
ns
tw(TBH)
TBiIN input high pulse width
300
ns
tw(TBL)
TBiIN input low pulse width
300
ns
Table 5.43
Timer B Input (Pulse Width Measurement Mode)
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time
600
ns
tw(TBH)
TBiIN input high pulse width
300
ns
tw(TBL)
TBiIN input low pulse width
300
ns
tc(TB)
t w(TBH)
TBiIN input
t w(TBL)
Figure 5.23
Timer B Input
REJ03B0267-0101
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M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version, VCC = 3 V
Timing Requirements
(VCC = 3 V, VSS = 0 V, at Topr = −40°C to 85°C unless otherwise specified)
5.3.2.5
Table 5.44
Timer S Input
Timer S Input (Two-phase Pulse Input in Two-phase Pulse Signal Processing Mode)
Symbol
Standard
Min.
Max.
Parameter
Unit
tw(TSH)
TSUDA, TSUDB input high pulse width
2
μs
tw(TSL)
TSUDA, TSUDB input low pulse width
2
μs
tsu(TSUDA-TSUDB)
TSUDB input setup time
1
μs
tsu(TSUDB-TSUDA)
TSUDA input setup time
1
μs
Two-phase pulse input in two-phase pulse signal processing mode
tw(TSH)
tw(TSL)
TSUDA input
tsu(TSUDA-TSUDB)
tsu(TSUDA-TSUDB)
tw(TSH)
tsu(TSUDB-TSUDA)
tw(TSL)
TSUDB input
tsu(TSUDB-TSUDA)
Note:
1. When the TSUDA and TSUDB phases are interchanged, tsu(TSUDA-TSUDB) and tsu(TSUDB-TSUDA)
are also interchanged.
Figure 5.24
Timer S Input (Two-phase Pulse Input in Two-phase Pulse Signal Processing Mode)
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M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version, VCC = 3 V
Timing Requirements
(VCC = 3 V, VSS = 0 V, at Topr = −40°C to 85°C unless otherwise specified)
5.3.2.6
Table 5.45
Serial Interface
Serial Interface
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(CK)
CLKi input cycle time
300
ns
tw(CKH)
CLKi input high pulse width
150
ns
tw(CKL)
CLKi input low pulse width
150
ns
td(C-Q)
TXDi output delay time
th(C-Q)
TXDi hold time
tsu(D-C)
th(C-D)
160
ns
0
ns
RXDi input setup time
100
ns
RXDi input hold time
90
ns
tc(CK)
t w(CKH)
CLKi
t w(CKL)
th(C-Q)
TXDi
td(C-Q)
tsu(D-C)
th(C-D)
RXDi
Figure 5.25
5.3.2.7
Table 5.46
Serial Interface
External Interrupt INTi Input
External Interrupt INTi Input
Symbol
Standard
Parameter
Min.
Max.
Unit
tw(INH)
INTi Input HIGH Pulse Width
380
ns
tw(INL)
INTi Input LOW Pulse Width
380
ns
t w(INL)
INTi input
t w(INH)
Figure 5.26
External Interrupt INTi Input
REJ03B0267-0101
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Page 113 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version, VCC = 3 V
Timing Requirements
(VCC = 3 V, VSS = 0 V, at Topr = −40°C to 85°C unless otherwise specified)
Multi-master I2C-bus
5.3.2.8
Table 5.47
Multi-master I2C-bus
Symbol
Standard Clock Mode
Parameter
Min.
High-speed Clock Mode
Max.
Min.
Max.
Unit
tBUF
Bus free time
4.7
1.3
μs
tHD;STA
Hold time in start condition
4.0
0.6
μs
tLOW
Hold time in SCL clock 0 status
4.7
1.3
μs
tR
SCL, SDA signals’ rising time
tHD;DAT
Data hold time
tHIGH
Hold time in SCL clock 1 status
fF
SCL, SDA signals’ falling time
tsu;DAT
Data setup time
250
100
ns
tsu;STA
Setup time in restart condition
4.7
0.6
μs
tsu;STO
Stop condition setup time
4.0
0.6
μs
1000
20 + 0.1 Cb
300
ns
0
0
0.9
μs
4.0
0.6
300
20 + 0.1 Cb
μs
300
ns
SDA
t HD;STA
t BUF
SCL
p
t LOW
t HD;STA
Figure 5.27
tR
tF
Sr
s
t HD;DTA
t HIGH
t su;DTA
t su;STO
p
t su;STA
Multi-master I2C-bus
REJ03B0267-0101
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Page 114 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version, VCC = 3 V
Timing Requirements
(VCC = 3 V, VSS = 0 V, at Topr = −40°C to 85°C unless otherwise specified)
5.3.2.9
Table 5.48
Serial bus interface
Serial Bus Interface
Symbol
tc(SSCK)
Measurement
condition
Characteristic
Value
Min.
Typ.
Unit
Max.
SSCK clock cycle time
250
tw(SSCKH)
SSCK clock high pulse width
0.4
0.6
tc(SSCK)
tw(SSCKL)
SSCK clock low pulse width
0.4
0.6
tc(SSCK)
Master
1
tCYC (1)
Slave
1
μs
Master
1
tCYC (1)
Slave
1
μs
tr(SSCK)
SSCK clock rising time
tf(SSCK)
SSCK clock falling time
tsu(SSIO-SSCK) SSO, SSI data input setup time
th(SSCK-SSIO)
100
ns
1
tCYC (1)
Slave
1 tCYC + 50 (1)
ns
Slave
1 tCYC + 50 (1)
ns
SSO, SSI data input hold time
tsu(SCS-SSCK) SCS setup time
ns
th(SSCK-SCS)
SCS hold time
td(SSCK-SSIO)
SS0, SSI data output delay time
1
tCYC (1)
ten(SCS-SSI)
SSI output enable time
3.0 V ≤ VCC ≤ 5.5 V
1.5 tCYC + 100 (1)
ns
tdis(SCS-SSI)
SSI output disable time
3.0 V ≤ VCC ≤ 5.5 V
1.5 tCYC + 100 (1)
ns
Note:
1.
1 tCYC is 1/f1 (s).
REJ03B0267-0101
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Rev.1.01
Page 115 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version, VCC = 3 V
4-Wire Bus Communication Mode, Master, CPHS = 1
VIH or VOH
SCS (output)
VIL or VOL
t w(SSCKH)
t f(SSCK)
t r(SSCK)
SSCK (output)
(CPOS = 1)
t w(SSCKL)
t w(SSCKH)
SSCK (output)
(CPOS = 0)
t c(SSCK)
t w(SSCKL)
SSO (output)
t d(SSCK-SSIO)
SSI (input)
t su(SSIO-SSCK)
t h(SSCK-SSIO)
4-Wire Bus Communication Mode, Master, CPHS = 0
VIH or VOH
SCS (output)
VIL or VOL
t w(SSCKH)
t f(SSCK)
t r(SSCK)
SSCK (output)
(CPOS = 1)
t w(SSCKL)
t w(SSCKH)
SSCK (output)
(CPOS =0)
t w(SSCKL)
t c(SSCK)
SSO (output)
t d(SSCK-SSIO)
SSI (input)
t su(SSIO-SSCK)
t h(SSCK-SSIO)
CPHS, CPOS: Bits in the SSMR register
Figure 5.28
I/O Timing of Serial Bus Interface (Master)
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5. Electrical Characteristics
J-Version, VCC = 3 V
4-Wire Bus Communication Mode, Slave, CPHS = 1
VIH or VOH
SCS (input)
VIL or VOL
t r(SSCK)
t f(SSCK)
t su(SCS-SSCK) t w(SSCKH)
t h(SSCK-SCS)
SSCK (input)
(CPOS = 1)
t w(SSCKL)
t w(SSCKH)
SSCK (input)
(CPOS = 0)
t c(SSCK)
t w(SSCKL)
SSO (input)
t su(SSIO-SSCK)
t h(SSCK-SSIO)
SSI (output)
t d(SSCK-SSIO)
t en(SCS-SSI)
t dis(SCS-SSI)
4-Wire Bus Communication Mode, Slave, CPHS = 0
SCS (input)
VIH or VOH
VIL or VOL
t su(SCS-SSCK) t w(SSCKH)
t f(SSCK)
t r(SSCK)
t h(SSCK-SCS)
SSCK (input)
(CPOS = 1)
t w(SSCKL)
t w(SSCKH)
SSCK (input)
(CPOS = 0)
t c(SSCK)
t w(SSCKL)
SSO (input)
t su(SSIO-SSCK)
t h(SSCK-SSIO)
SSI (output)
t en(SCS-SSI)
t d(SSCK-SSIO)
t dis(SCS-SSI)
CPHS, CPOS: Bits in the SSMR register
Figure 5.29
I/O Timing of Serial Bus Interface (Slave)
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5. Electrical Characteristics
J-Version, VCC = 3 V
t w(SSCKH)
VIH or VOH
SSCK
VIL or VOL
t c(SSCK)
t w(SSCKL)
SSO (output)
t d(SSCK-SSIO)
SSI (input)
t su(SSIO-SSCK)
Figure 5.30
t h(SSCK-SSIO)
I/O Timing of Serial Bus Interface (Synchronous Communication Mode)
MCU
Pin to be
measured
Figure 5.31
30 pF
Switching Characteristic Measurement Circuit
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Rev.1.01
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M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version
5.4
Electrical Characteristics (K-Version, Common to 3 V and 5 V)
5.4.1
Absolute Maximum Rating
Table 5.49
Absolute Maximum Ratings
Symbol
Characteristic
Condition
Value
Unit
VCC
Supply voltage
VCC = AVCC
-0.3 to 6.5
V
AVCC
Analog supply voltage
VCC = AVCC
-0.3 to 6.5
V
VREF
Analog reference voltage
−0.3 to VCC + 0.1 (1)
V
VI
Input voltage P0_0 to P0_7, P1_0 to
P1_7, P2_0 to P2_7, P3_0
to P3_7, P4_0 to P4_7,
P5_0 to P5_7, P6_0 to
P6_7, P7_0 to P7_7, P8_0
to P8_7, P9_0 to P9_7,
P10_0 to P10_7
XIN, RESET, CNVSS,
VREF
-0.3 to VCC + 0.3
V
-0.3 to VCC + 0.3
V
-40°C ≤ Topr ≤ 85°C
300
mW
85°C < Topr ≤ 125°C
250
mW
VO
Pd
Topr
Tstg
Output
voltage
P0_0 to P0_7, P1_0 to
P1_7, P2_0 to P2_7, P3_0
to P3_7, P4_0 to P4_7,
P5_0 to P5_7, P6_0 to
P6_7, P7_0 to P7_7, P8_0
to P8_7, P9_0 to P9_7,
P10_0 to P10_7
XOUT
Power consumption
Operating
While CPU operation
temperature
range
While flash memory
program and erase
operation
Storage temperature range
-40 to 125
°C
Programming area
0 to 60
Data area
-40 to 125
-65 to 150
°C
Note:
1.
Maximum value is 6.5 V.
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5. Electrical Characteristics
K-Version
5.4.2
Recommended Operating Conditions
Table 5.50
Operating Conditions (1)
VCC = 3.0 V to 5.5 V, Topr = -40 °C to 125 °C unless otherwise specified.
Symbol
VCC
Supply voltage
AVCC
Analog supply voltage
VSS
AVSS
VIH
Value
Characteristic
Min.
3.0
Max.
5.5
Unit
V
VCC
V
Ground voltage
0
V
Analog ground voltage
0
V
P0_0 to P0_7, P1_0 to P1_7, Input level 0.50 VCC
P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7,
Input level 0.70 VCC
High level input P8_0 to P8_7, P9_0 to P9_7,
P10_0
to
P10_7
voltage
XIN, RESET, CNVSS
SDAMM, SCLMM
VIL
Typ.
output current
V
0.85VCC
VCC
V
0.8 VCC
VCC
VCC
V
2.1
VCC
V
0
0.3 VCC
V
0
0.45VCC
V
0
0.2 VCC
V
When I2C-bus input level selected
0
0.3 VCC
V
When SMBUS input level selected
0
0.8
V
-80.0
mA
When
input level selected
When SMBUS input level selected
XIN, RESET, CNVSS
IOH(sum) High peak
VCC
0.7 VCC
I2C-bus
P0_0 to P0_7, P1_0 to P1_7, Input level 0.50 VCC
P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, Input level 0.70 VCC
Low level input P8_0 to P8_7, P9_0 to P9_7,
P10_0 to P10_7
voltage
SDAMM, SCLMM
0.7 VCC
Sum of IOH(peak) at P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_4, P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7
IOH(peak)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to
High level peak
P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
output current
P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7
-10.0
mA
IOH(avg)
High level
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to
average output P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7
current (2)
-5.0
mA
IOL(sum)
Low peak
output current
80.0
mA
IOL(peak)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to
Low level peak
P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
output current
P9_0 to P9_7, P10_0 to P10_7
10.0
mA
IOL(avg)
Low level
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to
average output P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7
current (2)
5.0
mA
f(XIN)
Main clock input oscillation frequency (2)
f(XCIN)
Sub clock oscillation oscillator frequency
Sum of IOL(peak) at P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7
f(PLL)
PLL clock oscillation frequency
f(BCLK)
CPU operation frequency
tsu(PLL)
Wait time to stabilize PLL frequency synthesizer
(2)
0
20
MHz
50
kHz
10
32
MHz
0
32
MHz
1
ms
32.768
Notes:
1.
The mean output current is the mean value within 100ms.
2.
Refer to “Figure 5.1 “Main clock input oscillation frequency, PLL clock oscillation frequency”” for the relationship between main
clock oscillation frequency/PLL clock oscillation frequency and supply voltage.
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5. Electrical Characteristics
K-Version
Main clock input oscillation frequency
PLL clock oscillation frequency
20.0 MHz
20.0
10.0
0.0
3.0
5.5
Vcc [V] (main clock: no division)
f(XIN) maximum operating frequency [MHz]
f(XIN) maximum operating frequency [MHz]
32.0
32.0 MHz
10.0
0.0
3.0
5.5
Vcc [V] (PLL clock oscillation)
Figure 5.32
Main Clock Input Oscillation Frequency, PLL Clock Oscillation Frequency
Table 5.51
Recommended Operating Conditions (2/2) (1)
VCC = 3.0 to 5.5 V, VSS = 0 V, and Topr = -40°C to 125°C unless otherwise specified.
The ripple voltage must not exceed Vr(VCC) and/or dVr(VCC)/dt.
Symbol
Standard
Parameter
Vr(VCC)
Allowable ripple voltage
dVr(VCC)/dt
Ripple voltage falling gradient
Min.
Typ.
Max.
Unit
VCC = 5.0 V
0.5
Vp-p
VCC = 3.0 V
0.3
Vp-p
VCC = 5.0 V
0.3
V/ms
VCC = 3.0 V
0.3
V/ms
Note:
1. The device is operationally guaranteed under these operating conditions.
VCC
Figure 5.33
V r( VCC )
Ripple Waveform
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5. Electrical Characteristics
K-Version
5.4.3
A/D Conversion Characteristics
Table 5.52
A/D Conversion Characteristics (1)
VCC = AVCC = VREF = 3.0 to 5.5 V, VSS = AVSS = 0 V at Topr = -40°C to 125°C unless otherwise specified.
Symbol
Parameter
—–
Resolution
INL
Integral Non-Linearity Error
—–
Absolute Accuracy
φAD
A/D operating clock frequency
Measuring Condition
Standard
Min.
Typ.
Max.
Unit
VREF = VCC
10
Bits
VREF = VCC = 5.0 V (2)
±3
LSB
VREF = VCC = 3.3 V (2)
±5
LSB
VREF = VCC = 5.0 V (2)
±3
LSB
VREF = VCC = 3.3 V (2)
±5
LSB
4.0 V ≤ VCC ≤ 5.5 V
2
25
MHz
3.2 V ≤ VCC ≤ 4.0 V
2
16
MHz
3.0 V ≤ VCC ≤ 3.2 V
2
10
MHz
—–
Tolerance Level Impedance
DNL
Differential Non-Linearity Error
(2)
3
±1
LSB
—–
Offset Error (4)
(2)
±3
LSB
—–
Gain Error (4)
(2)
±3
LSB
tCONV
10-bit Conversion Time
tsamp
VREF = VCC = 5V,
φAD = 25 MHz
kΩ
1.60
μs
Sampling time
0.6
μs
VREF
Reference Voltage
3.0
VCC
V
VIA
Analog Input Voltage (3)
0
VREF
V
Notes:
1. Use when AVCC = VCC
2. Flash memory rewrite disabled. Except for the analog input pin, set the pins to be measured as input
ports and connect them to VSS. See Figure 5.34 “A/D Accuracy Measure Circuit”.
3. When analog input voltage is over reference voltage, the result of A/D conversion is 3FFh.
AN
Analog input
P0 to P10
Figure 5.34
AN: One of the analog input pin
P0 to P10: I/O pins other than AN
A/D Accuracy Measure Circuit
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M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version
5.4.4
D/A Conversion Characteristics
Table 5.53
D/A Conversion Characteristics
VCC = AVCC = VREF = 3.0 to 5.5 V, VSS = AVSS = 0 V at Topr = -40°C to 125°C unless otherwise specified.
Symbol
Parameter
-
Resolution
-
Absolute Accuracy
tSU
Setup Time
RO
Output Resistance
IVREF
Reference Power Supply Input Current
Measuring Condition
Standard
Min.
5
1
See Notes and
2
Typ.
6
Max.
Unit
8
Bits
2.5
LSB
3
μs
8.2
kΩ
1.5
mA
Notes:
1. This applies when using one D/A converter, with the D/A register for the unused D/A converter set to 00h.
2. The current consumption of the A/D converter is not included. Also, the IVREF of the D/A converter will flow even
if the ADSTBY bit in the ADCON1 register is 0 (A/D operation stopped (standby)).
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5. Electrical Characteristics
K-Version
5.4.5
Flash Memory Electrical Characteristics
Table 5.54
CPU Clock When Operating Flash Memory (f(BCLK))
VCC = 3.0 to 5.5 V at Topr = -40°C to 125°C, unless otherwise specified.
Symbol
Parameter
-
CPU rewrite mode
f(SLOW_R)
Slow read mode
-
Low current consumption read mode
-
Data flash read
Conditions
Standard
Min.
Typ.
fC
Max.
Unit
16 (1)
MHz
(3)
MHz
(2)
MHz
5
35
20
kHz
Notes:
1. Set the PM17 bit in the PM1 register to 1 (one wait).
2. When the frequency is over this value, set the FMR17 bit in the FMR1 register to 0 (one wait) or the PM17 bit in
the PM1 register to 1 (one wait)
3. Set the PM17 bit in the PM1 register to 1 (one wait). No wait states are required if the 125 kHz on-chip oscillator
clock or sub clock is used as the clock source of the CPU clock.
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5. Electrical Characteristics
K-Version
Table 5.55
Flash Memory (Program ROM 1, 2) Electrical Characteristics
VCC = 3.0 to 5.5 V at Topr = 0°C to 60°C, unless otherwise specified.
Symbol
-
Parameter
Conditions
VCC = 3.3 V, Topr = 25°C
Standard
Min.
Unit
Typ.
Max.
150
4000
μs
times
-
Program/erase cycles (1, 3, 4)
Two words program time
1,000 (2)
Lock bit program time
VCC = 3.3 V, Topr = 25°C
70
3000
μs
-
Block erase time
VCC = 3.3 V, Topr = 25°C
0.2
3.0
s
td(SR-SUS)
Time delay from suspend request
until suspend
3 5 + --------------f ( BCLK )
ms
VCC = 3.3 V, Topr = 25°C
-
Interval from erase start/restart
until following suspend request
0
-
Suspend interval necessary for
auto-erasure to complete (7)
20
-
Time from suspend until erase
restart
-
Program, erase voltage
-
Read voltage
Topr = -40°C to 125°C
-
Program, erase temperature
tPS
Flash Memory Circuit Stabilization Wait Time
-
Data hold time (6)
ms
1 30 + --------------f ( BCLK )
μs
3.0
5.5
V
3.0
5.5
V
0
Ambient temperature = 55°C
μs
20
60
°C
50
μs
year
Notes:
1. Definition of program and erase cycles:
The program and erase cycles refer to the number of per-block erasures. If the program and erase cycles are n
(n = 1,000), each block can be erased n times. For example, if a 64 Kbyte block is erased after writing two word
data 16,384 times, each to a different address, this counts as one program and erase cycles. Data cannot be
written to the same address more than once without erasing the block (rewrite prohibited).
2. Cycles to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
3. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing
to sequential addresses in turn so that as much of the block as possible is used up before performing an erase
operation. It is advisable to retain data on the erasure cycles of each block and limit the number of erase
operations to a certain number.
4. If an error occurs during block erase, attempt to execute the clear status register command, then execute the
block erase command at least three times until the erase error does not occur.
5. Customers desiring program/erase failure rate information should contact a Renesas Electronics sales office.
6. The data hold time includes time that the power supply is off or the clock is not supplied.
7. After an erase start or erase restart, if an interval of at least 20 ms is not set before the next suspend request, the
erase sequence cannot be completed.
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5. Electrical Characteristics
K-Version
Table 5.56
Flash Memory (Data Flash) Electrical Characteristics
VCC = 3.0 to 5.5 V at Topr = -40°C to 125°C, unless otherwise specified.
Symbol
-
Parameter
Program/erase cycles (1, 3, 4)
Conditions
VCC = 3.3 V, Topr = 25°C
Standard
Min.
Typ.
Max.
10,000 (2)
Unit
times
-
Two words program time
VCC = 3.3 V, Topr = 25°C
300
4000
μs
-
Lock bit program time
VCC = 3.3 V, Topr = 25°C
140
3000
μs
-
Block erase time
VCC = 3.3 V, Topr = 25°C
0.2
3.0
s
3 5 + --------------f ( BCLK )
ms
td(SR-SUS) Time delay from suspend request
until suspend
-
Interval from erase start/restart until
following suspend request
0
-
Suspend interval necessary for
auto-erasure to complete (7)
20
-
Time from suspend until erase
restart
-
Program, erase voltage
3.0
μs
ms
1 30 + --------------f ( BCLK )
μs
5.5
V
-
Read voltage
3.0
5.5
V
-
Program, erase temperature
−40
125
°C
tPS
Flash Memory Circuit Stabilization Wait Time
50
μs
-
Data hold
time (6)
Ambient temperature = 55 °C
20
year
Notes:
1. Definition of program and erase cycles
The program and erase cycles refer to the number of per-block erasures.
If the program and erase cycles are n (n = 10,000), each block can be erased n times.
For example, if a 4 Kbyte block is erased after writing two word data 1,024 times, each to a different address, this
counts as one program and erase cycles. Data cannot be written to the same address more than once without
erasing the block (rewrite prohibited).
2. Cycles to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
3. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing
to sequential addresses in turn so that as much of the block as possible is used up before performing an erase
operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be
minimized by programming up to 256 groups before erasing them all in one operation. In addition, averaging the
erasure cycles between blocks A and B can further reduce the actual erasure cycles. It is also advisable to retain
data on the erasure cycles of each block and limit the number of erase operations to a certain number.
4. If an error occurs during block erase, attempt to execute the clear status register command, then execute the
block erase command at least three times until the erase error does not occur.
5. Customers desiring program/erase failure rate information should contact a Renesas Electronics sales office.
6. The data hold time includes time that the power supply is off or the clock is not supplied.
7.
After an erase start or erase restart, if an interval of at least 20 ms is not set before the next suspend request,
the erase sequence cannot be completed.
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M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version
5.4.6
E2PROM Emulation Data Flash
Table 5.57
E2PROM Emulation Data Flash Electrical Characteristics
VCC = 3.0 to 5.5 V at Topr = -40°C to 125°C, unless otherwise specified.
Symbol
Characteristic
—
Program/erase cycles (1)
—
Word program time (2-byte program)
—
Read time (2-byte read)
—
Block erase time (32-byte block)
tPS
Flash memory circuit stabilization wait time
(sleep mode to normal mode)
—
Data hold time (2)
Value
Min.
Typ.
Max.
100000
Ambient temperature = 55°C (3, 4)
times
100
20
Unit
2000
µs
1
µs
15
200
ms
35
50
µs
years
Notes:
1. Definition of program/erase cycles definition
This value represents the number of erasure per block.
If the flash memory is programmed/erased n times, each block can be erased n times.
i.e. If a word write is performed in different 16 addresses in a block and then the block is erased, it
is considered the programming/erasure is performed just once. However a write in the same
address more than once for one erasure is disabled. (overwrite disabled).
2. The data hold time includes the periods when the supply voltage is not applied and no clock is
provided.
3. This data hold time includes (3000) hours in Ambient temperature = 125°C.
4. Please contact a Renesas Electronics sales office regarding data retention time other than the
above.
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M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version
5.4.7
Voltage Detector and Power Supply Circuit Electrical Characteristics
Table 5.58
Voltage Detector 0 Electrical Characteristics
The measurement condition is VCC = 3.0 to 5.5 V, Topr = -40°C to 125°C, unless otherwise specified.
Symbol
Parameter
Condition
Vdet0
Voltage detection level Vdet0
When VCC is falling.
td(E-A)
Waiting time until voltage detector operation
starts (1)
VCC = 3.0 to 5.0 V
Standard
Unit
Min.
Typ.
Max.
2.70
2.85
3.00
V
100
μs
Note:
1.
Necessary time until the voltage detector operates when setting to 1 again after setting the VC25 bit in the VCR2
register to 0.
Table 5.59
Voltage Detector 2 Electrical Characteristics
The measurement condition is VCC = 3.0 to 5.5 V, Topr = -40°C to 125°C, unless otherwise specified.
Symbol
Parameter
Condition
Standard
Min.
Typ.
Max.
Unit
Vdet2_0
Voltage detection level Vdet2_0
3.21
V
Vdet2_1
Voltage detection level Vdet2_1
3.36
V
Vdet2_2
Voltage detection level Vdet2_2
3.51
V
Vdet2_3
Voltage detection level Vdet2_3
3.66
V
Vdet2_4
Voltage detection level Vdet2_4
Vdet2_5
Voltage detection level Vdet2_5
3.96
V
Vdet2_6
Voltage detection level Vdet2_6
4.10
V
Vdet2_7
Voltage detection level Vdet2_7
4.25
V
-
Hysteresis width at the rising of VCC in voltage
detector 2
0.15
V
td(E-A)
Waiting time until voltage detector operation starts (1) VCC = 3.0 to 5.0 V
When VCC is falling
3.51
3.81
4.11
100
V
μs
Note:
1.
Necessary time until the voltage detector operates after setting to 1 again after setting the VC27 bit in the VCR2
register to 0.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 128 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version
Table 5.60
Power-On Reset Circuit
The measurement condition is Topr = -40°C to 125°C, unless otherwise specified.
Symbol
Parameter
trth
External power VCC rise gradient
tfth
External power VCC fall gradient
Condition
Standard
Min.
Typ.
2.0
Max.
Unit
50000 mV/ms
50000 mV/ms
Vpor
Voltage at which power-on reset enabled
tw(por)
Hold time at which power-on reset enabled
(1)
0.1
V
1.0
ms
Note:
1.
To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS1 address
to 0.
Vdet0
External Power VCC
Vdet0
t rth
t rth
t fth
Vpor
tw(por)
Internal
reset signal
1
1
× 128
fOCO-S
Figure 5.35
Power-On Reset Circuit Electrical Characteristics
Table 5.61
Power Supply Circuit Timing Characteristics
Symbol
Parameter
× 128
fOCO-S
Measuring Condition
td(P-R)
Time for Internal Power Supply Stabilization VCC = 3.0 V to 5.5V
During Powering-On
td(R-S)
td(W-S)
Standard
Min.
Typ.
Max.
Unit
5
ms
STOP Release Time
300
μs
Low Power Mode Wait Mode Release Time
300
μs
Note:
1. When VCC = 5 V.
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 129 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version
Recommended
operating
voltage
t d(P-R)
Time to stabilize internal supply
voltage during powering-on
VCC
td(P-R)
CPU clock
(a) Interrupt to exit from stop mode
(b) Interrupt to exit from wait mode
t d(R-S)
STOP release time
t d(W-S)
Low power consumption
mode wait mode exit time
CPU clock
(a)
(b)
t d(E-A)
Voltage detection circuit
operation start time
td(R-S)
td(W-S)
VC25, VC27
Voltage detection circuit
Stop
Operate
td(E-A)
Figure 5.36
5.4.8
Power Supply Circuit Timing Diagram
Oscillation Circuit Electrical Characteristics
Table 5.62
On-chip Oscillator Oscillation Circuit Electrical Characteristics
VCC = 3.0 to 5.5 V, Topr = −40°C to 125°C, unless otherwise specified
Symbol
Characteristic
Value
Unit
Min.
Typ.
Max.
fOCO-S
125 kHz on-chip oscillator oscillation frequency
100
125
150
kHz
fOCO40M
40 kHz on-chip oscillator oscillation frequency
32
40
48
MHz
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 130 of 156
M16C/5M Group, M16C/57 Group
5.5
5. Electrical Characteristics
Electrical Characteristics (K-Version, VCC = 5 V)
5.5.1
Electrical Characteristics
K-Version, VCC = 5 V
Table 5.63
Electrical Characteristics (1)
VCC = 4.2 to 5.5 V, VSS = 0 V at Topr = −40°C to 125°C, f(BCLK) = 32 MHz unless otherwise specified.
Symbol
Parameter
Measuring Condition
Standard
Min.
Typ.
Max.
Unit
VOH
HIGH Output Voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7
IOH=−5 mA
VCC−2.0
VCC
V
VOH
HIGH Output Voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7
IOH = −200 μA
VCC−−0.3
VCC
V
HIGH Output Voltage
VOH
VOL
VOL
XOUT
HIGH Output Voltage
XCOUT
HIGH POWER
IOH = −1 mA
VCC−−2.0
VCC
LOW POWER
IOH = −0.5 mA
VCC−−2.0
VCC
HIGH POWER
With no load applied
2.5
LOW POWER
With no load applied
1.6
V
V
LOW Output Voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7
IOL = 5 mA
2.0
V
LOW Output Voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7
IOL = 200 μA
0.45
V
LOW Output Voltage
XOUT
VOL
LOW Output Voltage
XCOUT
HIGH POWER
IOL = 1 mA
2.0
LOW POWER
IOL = 0.5 mA
2.0
HIGH POWER
With no load applied
0
LOW POWER
With no load applied
0
V
V
VT+-VT-
Hysteresis
TA0IN to TA4IN, TB0IN to TB5IN, INT0 to INT7,
NMI, ADTRG, CTS0 to CTS3, SCL2, SDA2,
CLK0 to CLK4, TA0OUT to TA4OUT,
KI0 to KI3, RXD0 to RXD4, ZP, IDU, IDW, IDV,
SD, INPC1_0 to INPC1_7, SSI0, SSCK0, SCS0,
LIN0IN, CRX0, CRX1
VT+-VT-
Hysteresis
RESET
0.2
2.5
V
VT+-VT-
Hysteresis
XIN
0.2
0.8
V
HIGH Input Current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7
XIN, RESET, CNVSS
VI = 5 V
5.0
μA
IIL
LOW Input Current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 toP9_7, P10_0 to P10_7
XIN, RESET, CNVSS
VI = 0 V
−5.0
μA
RPULLUP
Pull-Up
Resistance
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7
VI = 0 V
170
kΩ
RfXIN
Feedback Resistance XIN
1.5
MΩ
RfXCIN
Feedback Resistance XCIN
15
MΩ
VRAM
RAM Retention Voltage
IIH
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
At stop mode
0.2
0.4VCC
V
30
2.0
50
V
Page 131 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 5 V
Table 5.64
Electrical Characteristics (2)
Topr = −40°C to 125°C unless otherwise specified.
Symbol
Parameter
Measuring Condition
f(BCLK) = 32 MHz,
XIN = 8 MHz (square wave), PLL multiply-by-8
125 kHz on-chip oscillator operates
f(BCLK) = 20 MHz,
High speed mode
XIN = 20 MHz (square wave),
125 kHz on-chip oscillator operates
f(BCLK) = 16 MHz,
XIN = 16 MHz (square wave),
125 kHz on-chip oscillator operates
Main clock stops
40 MHz on-chip oscillator operates
125 kHz on-chip oscillator operates
40 MHz on-chip oscillator No division
mode
Main clock stops
40 MHz on-chip oscillator operates
125 kHz on-chip oscillator operates
Divide-by-8
Main clock stops
40 MHz on-chip oscillator stops
125 kHz on-chip oscillator 125 kHz on-chip oscillator operates
Divide-by-8
mode
FMR22 = FMR23 = 1 (Low-current consumption
Standard
Unit
Min. Typ. Max.
25
45
mA
21
39
mA
17
21
mA
39
6
190
mA
mA
580
μA
read mode)
ICC
Power Supply Current
(VCC = 4.2 V to 5.5 V)
In single-chip mode, the
output pins are open and
other pins are VSS
Low power mode
f(BCLK) = 32 kHz
On Flash memory (2)
FMR22 = FMR23 = 1 (Low-current consumption
200
μA
Main clock stops
40 MHz on-chip oscillator stops
125 kHz on-chip oscillator operates
Peripheral clock operates
Topr = 25°C
25
μA
Main clock stops
40 MHz on-chip oscillator stops
125 kHz on-chip oscillator operates
Peripheral clock operates
Topr = 105°C
85
μA
Main clock stops
40 MHz on-chip oscillator stops
125 kHz on-chip oscillator operates
Peripheral clock operates
Topr = 125°C
125
μA
read mode)
Wait mode
Topr = 25°C
3
Topr = 105°C
60
μA
μA
Topr = 125°C
100
μA
During flash memory
program
f(BCLK) = 10 MHz, PM17 = 1 (one wait)
VCC = 5.0 V
20.0
mA
During flash memory
erase
f(BCLK) = 10 MHz, PM17 = 1 (one wait)
VCC = 5.0 V
30.0
mA
μA
μA
Stop mode
Idet2
Low Voltage Detection Dissipation Current
3
Idet0
Reset Area Detection Dissipation Current
6
15
Note:
1.
This indicates the memory in which the program to be executed exists.
REJ03B0267-0101
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Rev.1.01
Page 132 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 5 V
5.5.2
Timing Requirements (Peripheral Functions and Others)
(VCC = 5 V, VSS = 0 V, at Topr = −40°C to 125°C unless otherwise specified)
5.5.2.1
Reset Input (RESET Input)
Table 5.65
Reset Input (RESET Input)
Symbol
Standard
Parameter
Min.
RESET input low pulse width
tw(RSTL)
Max.
10
Unit
μs
RESET input
t w(RTSL)
Figure 5.37
5.5.2.2
Table 5.66
Reset Input (RESET Input)
External Clock Input
External Clock Input (XIN input) (1)
Symbol
tc
tw(H)
tw(L)
tr
tf
Standard
Min.
Max.
50
20
20
9
9
Parameter
External clock input cycle time
External clock input high pulse width
External clock input low pulse width
External clock rise time
External clock fall time
Unit
ns
ns
ns
ns
ns
Note:
1. The condition is VCC = 5.0V.
XIN input
tr
t w(H)
tf
t w(L)
tc
Figure 5.38
External Clock Input (XIN Input)
REJ03B0267-0101
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Rev.1.01
Page 133 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 5 V
Timing Requirements
(VCC = 5 V, VSS = 0 V, at Topr = −40°C to 125°C unless otherwise specified)
5.5.2.3
Table 5.67
Timer A Input
Timer A Input (Counter Input in Event Counter Mode)
Symbol
Standard
Min.
Max.
Parameter
Unit
tc(TA)
TAiIN input cycle time
100
ns
tw(TAH)
TAiIN input high pulse width
40
ns
tw(TAL)
TAiIN input low pulse width
40
ns
Table 5.68
Timer A Input (Gating Input in Timer Mode)
Symbol
Standard
Min.
Max.
Parameter
Unit
tc(TA)
TAiIN input cycle time
400
ns
tw(TAH)
TAiIN input high pulse width
200
ns
tw(TAL)
TAiIN input low pulse width
200
ns
Table 5.69
Timer A Input (External Trigger Input in One-shot Timer Mode)
Symbol
Standard
Min.
Max.
Parameter
Unit
tc(TA)
TAiIN input cycle time
200
ns
tw(TAH)
TAiIN input high pulse width
100
ns
tw(TAL)
TAiIN input low pulse width
100
ns
Table 5.70
Timer A Input (External Trigger Input in PWM Mode, Programmable Output Mode)
Symbol
Standard
Min.
Max.
Parameter
Unit
tw(TAH)
TAiIN input high pulse width
100
ns
tw(TAL)
TAiIN input low pulse width
100
ns
tc(TA)
t w(TAH)
TAiIN input
t w(TAL)
tc(UP)
t w(UPH)
TAiOUT input
t w(UPL)
Figure 5.39
Timer A Input
REJ03B0267-0101
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Rev.1.01
Page 134 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 5 V
Timing Requirements
(VCC = 5 V, VSS = 0 V, at Topr = −40°C to 125°C unless otherwise specified)
Table 5.71
Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Symbol
Standard
Min.
Max.
Parameter
Unit
tc(TA)
TAiIN input cycle time
800
ns
tsu(TAIN-TAOUT)
TAiOUT input setup time
200
ns
tsu(TAOUT-TAIN)
TAiIN input setup time
200
ns
Two-phase pulse input in event counter mode
tc(TA)
TAiIN input
tsu(TAIN-TAOUT)
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
TAiOUT input
tsu(TAOUT-TAIN)
Figure 5.40
Timer A Input (Two-Phase Pulse Input in Event Counter Mode)
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 135 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 5 V
Timing Requirements
(VCC = 5 V, VSS = 0 V, at Topr = −40°C to 125°C unless otherwise specified)
5.5.2.4
Table 5.72
Timer B Input
Timer B Input (Counter Input in Event Counter Mode)
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time (counted on one edge)
100
ns
tw(TBH)
TBiIN input high pulse width (counted on one edge)
40
ns
tw(TBL)
TBiIN input low pulse width (counted on one edge)
40
ns
tc(TB)
TBiIN input cycle time (counted on both edges)
200
ns
tw(TBH)
TBiIN input high pulse width (counted on both edges)
80
ns
tw(TBL)
TBiIN Input low pulse width (counted on both edges)
80
ns
Table 5.73
Timer B Input (Pulse Period Measurement Mode)
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time
400
ns
tw(TBH)
TBiIN input high pulse width
200
ns
tw(TBL)
TBiIN input low pulse width
200
ns
Table 5.74
Timer B Input (Pulse Width Measurement Mode)
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time
400
ns
tw(TBH)
TBiIN input high pulse width
200
ns
tw(TBL)
TBiIN input low pulse width
200
ns
tc(TB)
t w(TBH)
TBiIN input
t w(TBL)
Figure 5.41
Timer B Input
REJ03B0267-0101
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Page 136 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 5 V
Timing Requirements
(VCC = 5 V, VSS = 0 V, at Topr = −40°C to 125°C unless otherwise specified)
5.5.2.5
Table 5.75
Timer S Input
Timer S Input (Two-phase Pulse Input in Two-phase Pulse Signal Processing Mode)
Symbol
Standard
Min.
Max.
Parameter
Unit
tw(TSH)
TSUDA, TSUDB input high pulse width
2
μs
tw(TSL)
TSUDA, TSUDB input low pulse width
2
μs
tsu(TSUDA-TSUDB)
TSUDB input setup time
1
μs
tsu(TSUDB-TSUDA)
TSUDA input setup time
1
μs
Two-phase pulse input in two-phase pulse signal processing mode
tw(TSH)
tw(TSL)
TSUDA input
tsu(TSUDA-TSUDB)
tsu(TSUDA-TSUDB)
tw(TSH)
tsu(TSUDB-TSUDA)
tw(TSL)
TSUDB input
tsu(TSUDB-TSUDA)
Note:
1. When the TSUDA and TSUDB phases are interchanged, tsu(TSUDA-TSUDB) and tsu(TSUDB-TSUDA)
are also interchanged.
Figure 5.42
Timer S Input (Two-phase Pulse Input in Two-phase Pulse Signal Processing Mode)
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 137 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 5 V
Timing Requirements
(VCC = 5 V, VSS = 0 V, at Topr = −40°C to 125°C unless otherwise specified)
5.5.2.6
Table 5.76
Serial Interface
Serial Interface
Symbol
Standard
Parameter
Min.
Unit
Max.
tc(CK)
CLKi input cycle time
200
ns
tw(CKH)
CLKi input high pulse width
100
ns
tw(CKL)
CLKi input low pulse width
100
ns
td(C-Q)
TXDi output delay time
th(C-Q)
TXDi hold time
0
ns
tsu(D-C)
RXDi input setup time
70
ns
th(C-D)
RXDi input hold time
90
ns
80
ns
tc(CK)
t w(CKH)
CLKi
t w(CKL)
th(C-Q)
TXDi
td(C-Q)
tsu(D-C)
th(C-D)
RXDi
Figure 5.43
5.5.2.7
Table 5.77
Serial Interface
External Interrupt INTi Input
External Interrupt INTi Input
Symbol
Standard
Parameter
Min.
Max.
Unit
tw(INH)
INTi input high pulse width
250
ns
tw(INL)
INTi input low pulse width
250
ns
t w(INL)
INTi input
t w(INH)
Figure 5.44
External Interrupt INTi Input
REJ03B0267-0101
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Rev.1.01
Page 138 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 5 V
Timing Requirements
(VCC = 5 V, VSS = 0 V, at Topr = −40°C to 125°C unless otherwise specified)
Multi-master I2C-bus
5.5.2.8
Table 5.78
Multi-master I2C-bus
Symbol
Standard Clock Mode
Parameter
Min.
High-speed Clock Mode
Max.
Min.
Max.
Unit
tBUF
Bus free time
4.7
1.3
μs
tHD;STA
Hold time in start condition
4.0
0.6
μs
tLOW
Hold time in SCL clock 0 status
4.7
1.3
μs
tR
SCL, SDA signals’ rising time
tHD;DAT
Data hold time
tHIGH
Hold time in SCL clock 1 status
fF
SCL, SDA signals’ falling time
tsu;DAT
Data setup time
250
100
ns
tsu;STA
Setup time in restart condition
4.7
0.6
μs
tsu;STO
Stop condition setup time
4.0
0.6
μs
1000
20 + 0.1 Cb
300
ns
0
0
0.9
μs
4.0
0.6
300
20 + 0.1 Cb
μs
300
ns
SDA
t HD;STA
t BUF
SCL
p
t LOW
t HD;STA
Figure 5.45
tR
tF
Sr
s
t HD;DTA
t HIGH
t su;DTA
t su;STO
p
t su;STA
Multi-master I2C-bus
REJ03B0267-0101
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Rev.1.01
Page 139 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 5 V
Timing Requirements
(VCC = 5 V, VSS = 0 V, at Topr = −40°C to 125°C unless otherwise specified)
5.5.2.9
Table 5.79
Serial bus interface
Serial Bus Interface
Symbol
tc(SSCK)
Measurement
condition
Characteristic
Value
Min.
Typ.
Max.
Unit
SSCK clock cycle time
250
tw(SSCKH)
SSCK clock high pulse width
0.4
0.6
tc(SSCK)
tw(SSCKL)
SSCK clock low pulse width
0.4
0.6
tc(SSCK)
Master
1
tCYC (1)
Slave
1
μs
Master
1
tCYC (1)
Slave
1
μs
tr(SSCK)
SSCK clock rising time
tf(SSCK)
SSCK clock falling time
tsu(SSIO-SSCK) SSO, SSI data input setup time
th(SSCK-SSIO)
100
ns
1
tCYC (1)
Slave
1 tCYC + 50 (1)
ns
Slave
1 tCYC + 50 (1)
ns
SSO, SSI data input hold time
tsu(SCS-SSCK) SCS setup time
ns
th(SSCK-SCS)
SCS hold time
td(SSCK-SSIO)
SS0, SSI data output delay time
1
tCYC (1)
ten(SCS-SSI)
SSI output enable time
3.0 V ≤ VCC ≤ 5.5 V
1.5 tCYC + 100 (1)
ns
tdis(SCS-SSI)
SSI output disable time
3.0 V ≤ VCC ≤ 5.5 V
1.5 tCYC + 100 (1)
ns
Note:
1.
1 tCYC is 1/f1 (s).
REJ03B0267-0101
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M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 5 V
4-Wire Bus Communication Mode, Master, CPHS = 1
VIH or VOH
SCS (output)
VIL or VOL
t w(SSCKH)
t f(SSCK)
t r(SSCK)
SSCK (output)
(CPOS = 1)
t w(SSCKL)
t w(SSCKH)
SSCK (output)
(CPOS = 0)
t c(SSCK)
t w(SSCKL)
SSO (output)
t d(SSCK-SSIO)
SSI (input)
t su(SSIO-SSCK)
t h(SSCK-SSIO)
4-Wire Bus Communication Mode, Master, CPHS = 0
VIH or VOH
SCS (output)
VIL or VOL
t w(SSCKH)
t f(SSCK)
t r(SSCK)
SSCK (output)
(CPOS = 1)
t w(SSCKL)
t w(SSCKH)
SSCK (output)
(CPOS =0)
t w(SSCKL)
t c(SSCK)
SSO (output)
t d(SSCK-SSIO)
SSI (input)
t su(SSIO-SSCK)
t h(SSCK-SSIO)
CPHS, CPOS: Bits in the SSMR register
Figure 5.46
I/O Timing of Serial Bus Interface (Master)
REJ03B0267-0101
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Rev.1.01
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M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 5 V
4-Wire Bus Communication Mode, Slave, CPHS = 1
VIH or VOH
SCS (input)
VIL or VOL
t r(SSCK)
t f(SSCK)
t su(SCS-SSCK) t w(SSCKH)
t h(SSCK-SCS)
SSCK (input)
(CPOS = 1)
t w(SSCKL)
t w(SSCKH)
SSCK (input)
(CPOS = 0)
t c(SSCK)
t w(SSCKL)
SSO (input)
t su(SSIO-SSCK)
t h(SSCK-SSIO)
SSI (output)
t d(SSCK-SSIO)
t en(SCS-SSI)
t dis(SCS-SSI)
4-Wire Bus Communication Mode, Slave, CPHS = 0
SCS (input)
VIH or VOH
VIL or VOL
t su(SCS-SSCK) t w(SSCKH)
t f(SSCK)
t r(SSCK)
t h(SSCK-SCS)
SSCK (input)
(CPOS = 1)
t w(SSCKL)
t w(SSCKH)
SSCK (input)
(CPOS = 0)
t c(SSCK)
t w(SSCKL)
SSO (input)
t su(SSIO-SSCK)
t h(SSCK-SSIO)
SSI (output)
t en(SCS-SSI)
t d(SSCK-SSIO)
t dis(SCS-SSI)
CPHS, CPOS: Bits in the SSMR register
Figure 5.47
I/O Timing of Serial Bus Interface (Slave)
REJ03B0267-0101
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Rev.1.01
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M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 5 V
t w(SSCKH)
VIH or VOH
SSCK
VIL or VOL
t c(SSCK)
t w(SSCKL)
SSO (output)
t d(SSCK-SSIO)
SSI (input)
t su(SSIO-SSCK)
Figure 5.48
t h(SSCK-SSIO)
I/O Timing of Serial Bus Interface (Synchronous Communication Mode)
MCU
Pin to be
measured
Figure 5.49
30 pF
Switching Characteristic Measurement Circuit
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 143 of 156
M16C/5M Group, M16C/57 Group
5.6
5. Electrical Characteristics
Electrical Characteristics (K-Version, VCC = 3 V)
5.6.1
Electrical Characteristics
K-Version, VCC = 3 V
Table 5.80
Electrical Characteristics (1)
VCC = 3.0 to 3.6 V, VSS = 0 V at Topr = −40°C to 125°C, f(BCLK)=32 MHz unless otherwise specified.
Symbol
VOH
Parameter
P0_0 to P0_7, P1_0 to P1_7, P2_0 to
P2_7, P3_0 to P3_7, P4_0 to P4_7,
P5_0 to P5_7, P6_0 to P6_7, P7_0 to
P7_7, P8_0 to P8_4, P8_6 to P8_7,
P9_0 to P9_7, P10_0 to P10_7
HIGH
Output
Voltage
HIGH Output Voltage
XOUT
HIGH Output Voltage
XCOUT
VOH
VOL
Measuring Condition
LOW Output Voltage
XOUT
LOW Output Voltage
XCOUT
VOL
Typ.
Max.
IOH = −1 mA
VCC−0.5
VCC
HIGH POWER
IOH = −0.1 mA
VCC−0.5
VCC
LOW POWER
IOH = −50 μA
VCC−0.5
VCC
HIGH POWER
With no load applied
2.5
LOW POWER
With no load applied
1.6
P0_0 to P0_7, P1_0 to P1_7, P2_0 to
P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0
to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_7, P9_0 to P9_7, P10_0 to
P10_7
LOW
Output
Voltage
Standard
Min.
0.5
HIGH POWER
IOL = 0.1mA
0.5
LOW POWER
IOL = 50μA
0.5
HIGH POWER
With no load applied
0
With no load applied
0
VT+-VT-
Hysteresis
TA0IN to TA4IN, TB0IN to TB5IN, INT0
to INT7, NMI, ADTRG, CTS0 to CTS3,
SCL2, SDA2, CLK0 to CLK4, TA0OUT
to TA4OUT, KI0 to KI3, RXD0 to RXD4,
ZP, IDU, IDW, IDV, SD, INPC1_0 to
INPC1_7, SSI0, SSCK0, SCS0, LIN0IN,
CRX0, CRX1
VT+-VT-
Hysteresis
VT+-VT-
V
V
V
IOL = 1mA
LOW POWER
Unit
V
V
V
0.4VCC
V
RESET
1.8
V
Hysteresis
XIN
0.8
V
HIGH Input
Current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to
P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0
to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_7, P9_0 to P9_7, P10_0 to
P10_7
XIN, RESET, CNVSS
VI = 3V
4.0
μA
IIL
LOW Input
Current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to
P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0
to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_7, P9_0 to P9_7, P10_0 to
P10_7
XIN, RESET, CNVSS
VI = 0V
−4.0
μA
RPULLUP
Pull-Up
Resistance
P0_0 to P0_7, P1_0 to P1_7, P2_0 to
P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0
to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_4, P8_6 to P8_7, P9_0 to
P9_7, P10_0 to P10_7
VI = 0V
500
kΩ
RfXIN
Feedback Resistance XIN
RfXCIN
Feedback Resistance XCIN
VRAM
RAM Retention Voltage
IIH
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
At stop mode
50
2.0
100
3.0
MΩ
25
MΩ
V
Page 144 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 3 V
Table 5.81
Electrical Characteristics (2)
Topr = −40°C to 125°C unless otherwise specified.
Symbol
ICC
Parameter
Power Supply Current
(VCC = 3.0 V to 3.6 V)
In single-chip mode, the
output pins are open and
other pins are VSS
Measuring Condition
f(BCLK) = 32 MHz,
XIN = 8 MHz (square wave), PLL multiply-by-8
125 kHz on-chip oscillator operates
f(BCLK) = 20 MHz,
High speed mode
XIN = 20 MHz (square wave),
125 kHz on-chip oscillator operates
f(BCLK) = 16 MHz,
XIN = 16 MHz (square wave),
125 kHz on-chip oscillator operates
Main clock stops
40 MHz on-chip oscillator operates
125 kHz on-chip oscillator operates
40 MHz on-chip oscillator No division
mode
Main clock stops
40 MHz on-chip oscillator operates
125 kHz on-chip oscillator operates
Divide-by-8
Main clock stops
40 MHz on-chip oscillator stops
125 kHz on-chip oscillator 125 kHz on-chip oscillator operates
mode
Divide-by-8
FMR22 = FMR23 = 1 (Low-current consumption read
mode)
f(BCLK) = 32 kHz
On ROM
Low power mode
FMR22 = FMR23 = 1 (Low-current consumption read
mode)
Main clock stops
40 MHz on-chip oscillator stops
125 kHz on-chip oscillator operates
Peripheral clock operates
Topr = 25°C
Wait mode
Standard
Unit
Min. Typ. Max.
23
43
mA
20
38
mA
16
20
38
6
190
mA
mA
580
μA
200
μA
25
μA
Main clock stops
40 MHz on-chip oscillator stops
125 kHz on-chip oscillator operates
Peripheral clock operates
Topr = 105°C
85
μA
Main clock stops
40 MHz on-chip oscillator stops
125 kHz on-chip oscillator operates
Peripheral clock operates
Topr = 125°C
125
μA
Topr = 25°C
2
Topr = 105°C
60
Topr = 125°C
100
μA
μA
μA
During flash memory
program
f(BCLK) = 10 MHz, PM17 = 1 (one wait)
VCC = 3.0 V
20.0
mA
During flash memory
erase
f(BCLK) = 10 MHz, PM17 = 1 (one wait)
VCC = 3.0 V
30.0
mA
μA
μA
Stop mode
Idet2
Low Voltage Detection Dissipation Current
3
Idet0
Reset Area Detection Dissipation Current
6
REJ03B0267-0101
Jul 23, 2010
mA
Rev.1.01
12
Page 145 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 3 V
5.6.2
Timing Requirements (Peripheral Functions and Others)
(VCC = 3 V, VSS = 0 V, at Topr = −40°C to 125°C unless otherwise specified)
5.6.2.1
Reset Input (RESET Input)
Table 5.82
Reset Input (RESET Input)
Symbol
Standard
Parameter
Min.
RESET input low pulse width
tw(RSTL)
Max.
10
Unit
μs
RESET input
t w(RTSL)
Figure 5.50
5.6.2.2
Table 5.83
Reset Input (RESET Input)
External Clock Input
External Clock Input (XIN input) (1)
Symbol
tc
tw(H)
tw(L)
tr
tf
Standard
Min.
Max.
50
20
20
9
9
Parameter
External clock input cycle time
External clock input high pulse width
External clock input low pulse width
External clock rise time
External clock fall time
Unit
ns
ns
ns
ns
ns
Note:
1. The condition is VCC = 3.0V.
XIN input
tr
t w(H)
tf
t w(L)
tc
Figure 5.51
External Clock Input (XIN Input)
REJ03B0267-0101
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Rev.1.01
Page 146 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 3 V
Timing Requirements
(VCC = 3 V, VSS = 0 V, at Topr = −40°C to 125°C unless otherwise specified)
5.6.2.3
Table 5.84
Timer A Input
Timer A Input (Counter Input in Event Counter Mode)
Symbol
Standard
Min.
Max.
Parameter
Unit
tc(TA)
TAiIN input cycle time
150
ns
tw(TAH)
TAiIN input high pulse width
60
ns
tw(TAL)
TAiIN input low pulse width
60
ns
Table 5.85
Timer A Input (Gating Input in Timer Mode)
Symbol
Standard
Min.
Max.
Parameter
Unit
tc(TA)
TAiIN input cycle time
600
ns
tw(TAH)
TAiIN input high pulse width
300
ns
tw(TAL)
TAiIN input low pulse width
300
ns
Table 5.86
Timer A Input (External Trigger Input in One-shot Timer Mode)
Symbol
Standard
Min.
Max.
Parameter
Unit
tc(TA)
TAiIN input cycle time
300
ns
tw(TAH)
TAiIN input high pulse width
150
ns
tw(TAL)
TAiIN input low pulse width
150
ns
Table 5.87
Timer A Input (External Trigger Input in PWM Mode, Programmable Output Mode)
Symbol
Standard
Min.
Max.
Parameter
Unit
tw(TAH)
TAiIN input high pulse width
150
ns
tw(TAL)
TAiIN input low pulse width
150
ns
tc(TA)
t w(TAH)
TAiIN input
t w(TAL)
tc(UP)
t w(UPH)
TAiOUT input
t w(UPL)
Figure 5.52
Timer A Input
REJ03B0267-0101
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Rev.1.01
Page 147 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 3 V
Timing Requirements
(VCC = 3 V, VSS = 0 V, at Topr = −40°C to 125°C unless otherwise specified)
Table 5.88
Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Symbol
Standard
Min.
Max.
Parameter
Unit
tc(TA)
TAiIN input cycle time
2
μs
tsu(TAIN-TAOUT)
TAiOUT input setup time
500
ns
tsu(TAOUT-TAIN)
TAiIN input setup time
500
ns
Two-phase pulse input in event counter mode
tc(TA)
TAiIN input
tsu(TAIN-TAOUT)
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
TAiOUT input
tsu(TAOUT-TAIN)
Figure 5.53
Timer A Input (Two-Phase Pulse Input in Event Counter Mode)
REJ03B0267-0101
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Rev.1.01
Page 148 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 3 V
Timing Requirements
(VCC = 3 V, VSS = 0 V, at Topr = −40°C to 125°C unless otherwise specified)
5.6.2.4
Table 5.89
Timer B Input
Timer B Input (Counter Input in Event Counter Mode)
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time (counted on one edge)
150
ns
tw(TBH)
TBiIN input high pulse width (counted on one edge)
60
ns
tw(TBL)
TBiIN input low pulse width (counted on one edge)
60
ns
tc(TB)
TBiIN input cycle time (counted on both edges)
300
ns
tw(TBH)
TBiIN input high pulse width (counted on both edges)
120
ns
tw(TBL)
TBiIN Input low pulse width (counted on both edges)
120
ns
Table 5.90
Timer B Input (Pulse Period Measurement Mode)
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time
600
ns
tw(TBH)
TBiIN input high pulse width
300
ns
tw(TBL)
TBiIN input low pulse width
300
ns
Table 5.91
Timer B Input (Pulse Width Measurement Mode)
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time
600
ns
tw(TBH)
TBiIN input high pulse width
300
ns
tw(TBL)
TBiIN input low pulse width
300
ns
tc(TB)
t w(TBH)
TBiIN input
t w(TBL)
Figure 5.54
Timer B Input
REJ03B0267-0101
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Rev.1.01
Page 149 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 3 V
Timing Requirements
(VCC = 3 V, VSS = 0 V, at Topr = −40°C to 125°C unless otherwise specified)
5.6.2.5
Table 5.92
Timer S Input
Timer S Input (Two-phase Pulse Input in Two-phase Pulse Signal Processing Mode)
Symbol
Standard
Min.
Max.
Parameter
Unit
tw(TSH)
TSUDA, TSUDB input high pulse width
2
μs
tw(TSL)
TSUDA, TSUDB input low pulse width
2
μs
tsu(TSUDA-TSUDB)
TSUDB input setup time
1
μs
tsu(TSUDB-TSUDA)
TSUDA input setup time
1
μs
Two-phase pulse input in two-phase pulse signal processing mode
tw(TSH)
tw(TSL)
TSUDA input
tsu(TSUDA-TSUDB)
tsu(TSUDA-TSUDB)
tw(TSH)
tsu(TSUDB-TSUDA)
tw(TSL)
TSUDB input
tsu(TSUDB-TSUDA)
Note:
1. When the TSUDA and TSUDB phases are interchanged, tsu(TSUDA-TSUDB) and tsu(TSUDB-TSUDA)
are also interchanged.
Figure 5.55
Timer S Input (Two-phase Pulse Input in Two-phase Pulse Signal Processing Mode)
REJ03B0267-0101
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Rev.1.01
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M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 3 V
Timing Requirements
(VCC = 3 V, VSS = 0 V, at Topr = −40°C to 125°C unless otherwise specified)
5.6.2.6
Table 5.93
Serial Interface
Serial Interface
Symbol
Standard
Parameter
Min.
Unit
Max.
tc(CK)
CLKi input cycle time
300
ns
tw(CKH)
CLKi input high pulse width
150
ns
tw(CKL)
CLKi input low pulse width
150
ns
td(C-Q)
TXDi output delay time
th(C-Q)
TXDi hold time
tsu(D-C)
th(C-D)
160
ns
0
ns
RXDi input setup time
100
ns
RXDi input hold time
90
ns
tc(CK)
t w(CKH)
CLKi
t w(CKL)
th(C-Q)
TXDi
td(C-Q)
tsu(D-C)
th(C-D)
RXDi
Figure 5.56
5.6.2.7
Table 5.94
Serial Interface
External Interrupt INTi Input
External Interrupt INTi Input
Symbol
Standard
Parameter
Min.
Max.
Unit
tw(INH)
INTi Input HIGH Pulse Width
380
ns
tw(INL)
INTi Input LOW Pulse Width
380
ns
t w(INL)
INTi input
t w(INH)
Figure 5.57
External Interrupt INTi Input
REJ03B0267-0101
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Rev.1.01
Page 151 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 3 V
Timing Requirements
(VCC = 3 V, VSS = 0 V, at Topr = −40°C to 125°C unless otherwise specified)
Multi-master I2C-bus
5.6.2.8
Table 5.95
Multi-master I2C-bus
Symbol
Standard Clock Mode
Parameter
Min.
High-speed Clock Mode
Max.
Min.
Max.
Unit
tBUF
Bus free time
4.7
1.3
μs
tHD;STA
Hold time in start condition
4.0
0.6
μs
tLOW
Hold time in SCL clock 0 status
4.7
1.3
μs
tR
SCL, SDA signals’ rising time
tHD;DAT
Data hold time
tHIGH
Hold time in SCL clock 1 status
fF
SCL, SDA signals’ falling time
tsu;DAT
Data setup time
250
100
ns
tsu;STA
Setup time in restart condition
4.7
0.6
μs
tsu;STO
Stop condition setup time
4.0
0.6
μs
1000
20 + 0.1 Cb
300
ns
0
0
0.9
μs
4.0
0.6
300
20 + 0.1 Cb
μs
300
ns
SDA
t HD;STA
t BUF
SCL
p
t LOW
t HD;STA
Figure 5.58
tR
tF
Sr
s
t HD;DTA
t HIGH
t su;DTA
t su;STO
p
t su;STA
Multi-master I2C-bus
REJ03B0267-0101
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Rev.1.01
Page 152 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 3 V
Timing Requirements
(VCC = 3 V, VSS = 0 V, at Topr = −40°C to 125°C unless otherwise specified)
5.6.2.9
Table 5.96
Serial bus interface
Serial Bus Interface
Symbol
tc(SSCK)
Measurement
condition
Characteristic
Value
Min.
Typ.
Max.
Unit
SSCK clock cycle time
250
tw(SSCKH)
SSCK clock high pulse width
0.4
0.6
tc(SSCK)
tw(SSCKL)
SSCK clock low pulse width
0.4
0.6
tc(SSCK)
Master
1
tCYC (1)
Slave
1
μs
Master
1
tCYC (1)
Slave
1
μs
tr(SSCK)
SSCK clock rising time
tf(SSCK)
SSCK clock falling time
tsu(SSIO-SSCK) SSO, SSI data input setup time
th(SSCK-SSIO)
100
ns
1
tCYC (1)
Slave
1 tCYC + 50 (1)
ns
Slave
1 tCYC + 50 (1)
ns
SSO, SSI data input hold time
tsu(SCS-SSCK) SCS setup time
ns
th(SSCK-SCS)
SCS hold time
td(SSCK-SSIO)
SS0, SSI data output delay time
1
tCYC (1)
ten(SCS-SSI)
SSI output enable time
3.0 V ≤ VCC ≤ 5.5 V
1.5 tCYC + 100 (1)
ns
tdis(SCS-SSI)
SSI output disable time
3.0 V ≤ VCC ≤ 5.5 V
1.5 tCYC + 100 (1)
ns
Note:
1.
1 tCYC is 1/f1 (s).
REJ03B0267-0101
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Page 153 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 3 V
4-Wire Bus Communication Mode, Master, CPHS = 1
VIH or VOH
SCS (output)
VIL or VOL
t w(SSCKH)
t f(SSCK)
t r(SSCK)
SSCK (output)
(CPOS = 1)
t w(SSCKL)
t w(SSCKH)
SSCK (output)
(CPOS = 0)
t c(SSCK)
t w(SSCKL)
SSO (output)
t d(SSCK-SSIO)
SSI (input)
t su(SSIO-SSCK)
t h(SSCK-SSIO)
4-Wire Bus Communication Mode, Master, CPHS = 0
VIH or VOH
SCS (output)
VIL or VOL
t w(SSCKH)
t f(SSCK)
t r(SSCK)
SSCK (output)
(CPOS = 1)
t w(SSCKL)
t w(SSCKH)
SSCK (output)
(CPOS =0)
t w(SSCKL)
t c(SSCK)
SSO (output)
t d(SSCK-SSIO)
SSI (input)
t su(SSIO-SSCK)
t h(SSCK-SSIO)
CPHS, CPOS: Bits in the SSMR register
Figure 5.59
I/O Timing of Serial Bus Interface (Master)
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 154 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 3 V
4-Wire Bus Communication Mode, Slave, CPHS = 1
VIH or VOH
SCS (input)
VIL or VOL
t r(SSCK)
t f(SSCK)
t su(SCS-SSCK) t w(SSCKH)
t h(SSCK-SCS)
SSCK (input)
(CPOS = 1)
t w(SSCKL)
t w(SSCKH)
SSCK (input)
(CPOS = 0)
t c(SSCK)
t w(SSCKL)
SSO (input)
t su(SSIO-SSCK)
t h(SSCK-SSIO)
SSI (output)
t d(SSCK-SSIO)
t en(SCS-SSI)
t dis(SCS-SSI)
4-Wire Bus Communication Mode, Slave, CPHS = 0
SCS (input)
VIH or VOH
VIL or VOL
t su(SCS-SSCK) t w(SSCKH)
t f(SSCK)
t r(SSCK)
t h(SSCK-SCS)
SSCK (input)
(CPOS = 1)
t w(SSCKL)
t w(SSCKH)
SSCK (input)
(CPOS = 0)
t c(SSCK)
t w(SSCKL)
SSO (input)
t su(SSIO-SSCK)
t h(SSCK-SSIO)
SSI (output)
t en(SCS-SSI)
t d(SSCK-SSIO)
t dis(SCS-SSI)
CPHS, CPOS: Bits in the SSMR register
Figure 5.60
I/O Timing of Serial Bus Interface (Slave)
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 155 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 3 V
t w(SSCKH)
VIH or VOH
SSCK
VIL or VOL
t c(SSCK)
t w(SSCKL)
SSO (output)
t d(SSCK-SSIO)
SSI (input)
t su(SSIO-SSCK)
Figure 5.61
t h(SSCK-SSIO)
I/O Timing of Serial Bus Interface (Synchronous Communication Mode)
MCU
Pin to be
measured
Figure 5.62
30 pF
Switching Characteristic Measurement Circuit
REJ03B0267-0101
Jul 23, 2010
Rev.1.01
Page 156 of 156
REVISION HISTORY
Rev.
Date
1.01
Jul 23, 2010
Page
—
M16C/5M Group Datasheet
Description
Summary
First edition issued
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A- 1
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the
manual.
 The input pins of CMOS products are generally in the high-impedance state. In operation
with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the
vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur
due to the false recognition of the pin state as an input signal become possible. Unused
pins should be handled as described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
 The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states
of pins are not guaranteed from the moment when power is supplied until the reset
process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset
function are not guaranteed from the moment when power is supplied until the power
reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
 The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become
stable. When switching the clock signal during program execution, wait until the target clock
signal has stabilized.
 When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization of
the clock signal. Moreover, when switching to a clock signal produced with an external
resonator (or by an external oscillator) while program execution is in progress, wait until
the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different part number, confirm
that the change will not lead to problems.
 The characteristics of MPU/MCU in the same group but having different part numbers may
differ because of the differences in internal memory capacity and layout pattern. When
changing to products of different part numbers, implement a system-evaluation test for
each of the products.
Notice
1.
All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas
Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to
be disclosed by Renesas Electronics such as that disclosed through our website.
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technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or
others.
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You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.
4.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the
use of these circuits, software, or information.
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range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the
use of Renesas Electronics products beyond such specified ranges.
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Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and
malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the
possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,
please evaluate the safety of the final products or system manufactured by you.
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no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.
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12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.
(Note 1)
"Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2)
"Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
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