Preliminary Datasheet R1EV24004ASAS0I Two-wire serial interface 4k EEPROM (512-word 8-bit) R10DS0123EJ0100 Rev.1.00 Apr. 08, 2013 Description R1EV24xxx series are two-wire serial interface EEPROM (Electrically Erasable and Programmable ROM). They realize high speed, low power consumption and a high level of reliability by employing advanced MONOS memory technology and CMOS process. They also have a 16-byte page programming function to make their write operation faster. Features Single supply: 2.5 V to 5.5 V Two-wire serial interface (I2C serial bus) Clock frequency: 400 kHz Power dissipation: Standby: 2 A (max) Active (Read): 1 mA (max) Active (Write): 2.5 mA (max) Automatic page write: 16-byte/page Write cycle time: 5 ms Endurance: 1,000k Cycles @25C Data retention: 100 Years @25C Small size packages: SOP-8pin Shipping tape and reel SOP 8-pin: 4,000 IC/reel Temperature range: 40 to +85C Lead free products. Halogen free products. Preliminary: The specifications of this device are subject to change without notice. Please contact your nearest Renesas Electronics’ Sales Dept. regarding specifications. R10DS0123EJ0100 Rev.1.00 Apr. 08, 2013 Page 1 of 15 R1EV24004ASAS0I Ordering Information Orderable Part Numbers R1EV24004ASAS0I#K0 Internal organization 4k bit (512 8-bit) Package 150 mil 8-pin plastic SOP PRSP0008DF-B (FP-8DBV) Lead free, Halogen free Shipping tape and reel 4,000 IC/reel Pin Arrangement 8-pin SOP A0 (NC) 1 8 VCC A1 2 7 WP A2 3 6 SCL VSS 4 5 SDA (Top view) Pin Description Pin name Function A0 to A2 SCL SDA WP VCC VSS NC Device address Serial clock input Serial data input/output Write protect Power supply Ground No connection Block Diagram Voltage detector VCC High voltage generator A0(NC), A1, A2 SCL X decoder Control logic Y decoder WP Address generator VSS Memory array Y-select & Sense amp. SDA Serial-parallel converter R10DS0123EJ0100 Rev.1.00 Apr. 08, 2013 Page 2 of 15 R1EV24004ASAS0I Absolute Maximum Ratings Parameter Supply voltage relative to VSS Input voltage relative to VSS Operating temperature range*1 Storage temperature range Symbol VCC Vin Topr Tstg Value 0.6 to +7.0 0.5*2 to +7.0 40 to +85 55 to +125 Unit V V C C Notes: 1. Including electrical characteristics and data retention. 2. Vin (min): 3.0 V for pulse width 50 ns. DC Operating Conditions Parameter Symbol VCC VSS VIH VIL Topr Supply voltage Input high voltage Input low voltage Operating temperature Note: Min 2.5 0 VCC 0.7 0.3*1 40 Typ 0 Max 5.5 0 VCC + 0.5 VCC 0.3 +85 Unit V V V V C 1. VIL (min): 1.0 V for pulse width 50 ns. DC Characteristics (Ta = 40 to +85C, VCC = 2.5 V to 5.5 V) Parameter Input leakage current Output leakage current Standby VCC current Symbol ILI ILO ISB Read VCC current ICC1 Write VCC current ICC2 Output low voltage VOL Min Typ 0.5 0.2 1.0 Max 2.0 2.0 2.0 1.0 2.5 0.4 Unit A A A A mA mA mA mA V Test conditions VCC = 5.5 V, Vin = 0 to 5.5 V VCC = 5.5 V, Vout = 0 to 5.5 V VCC = 5.5 V, Vin = VSS or VCC VCC = 3.3 V, Vin = VSS or VCC, Ta=25C VCC = 5.5 V, Read at 400 kHz VCC = 3.3 V, Read at 400 kHz, Ta=25C VCC = 5.5 V, Write at 400 kHz VCC = 3.3 V, Write at 400 kHz, Ta=25C IOL = 3.0 mA Capacitance (Ta = +25C, f = 1 MHz) Parameter Input capacitance (A0 to A2, SCL, WP) Output capacitance (SDA) Note: Symbol Cin*1 CI/O*1 Min Typ Max 6.0 6.0 Unit pF pF Test conditions Vin = 0 V Vout = 0 V 1. Not 100 tested. Memory Cell Characteristics (VCC = 2.5 V to 5.5 V) Endurance Data retention Note: Ta=25C 1,000k Cycles min. 100 Years min. Ta=85C 100k Cycles min 10 Years min. Notes 1 1 1. Not 100 tested. Data of shipped sample All bits of EEPROM are logical “1” (FF Hex) at shipment. R10DS0123EJ0100 Rev.1.00 Apr. 08, 2013 Page 3 of 15 R1EV24004ASAS0I AC Characteristics Test Conditions Input pules levels: VIL = 0.2 VCC VIH = 0.8 VCC Input rise and fall time: 20 ns Input and output timing reference levels: 0.5 VCC Output load: TTL Gate + 100 pF (Ta = 40 to +85C, VCC = 2.5 to 5.5 V) Parameter Clock frequency Clock pulse width low Clock pulse width high Noise suppression time Access time Symbol fSCL tLOW tHIGH tI tAA Min 1200 600 100 Typ Max 400 50 900 Unit kHz ns ns ns ns tBUF ns ns 300 300 5 ns ns ns ns ns ns ns ns ns ms Bus free time for next mode Start hold time tHD.STA 1200 600 Start setup time Data in hold time Data in setup time Input rise time Input fall time Stop setup time Data out hold time Write protect hold time Write protect setup time Write cycle time tSU.STA tHD.DAT tSU.DAT tR tF tSU.STO tDH tHD.WP tSU.WP tWC 600 0 100 600 50 1200 0 Notes 1 1 1 2 Notes: 1. Not 100 tested. 2. tWC is the time from a stop condition to the end of internally controlled write cycle. R10DS0123EJ0100 Rev.1.00 Apr. 08, 2013 Page 4 of 15 R1EV24004ASAS0I Timing Waveforms Bus Timing tF tHIGH 1/fSCL tLOW tR SCL tSU.STA tHD.DAT tSU.DAT tHD.STA tSU.STO SDA (in) tBUF tAA tDH SDA (out) tSU.WP tHD.WP WP Write Cycle Timing Stop condition Start condition SCL D0 in SDA Write data (Address (n)) R10DS0123EJ0100 Rev.1.00 Apr. 08, 2013 ACK tWC (Internally controlled) Page 5 of 15 R1EV24004ASAS0I Pin Function Serial Clock (SCL) The SCL pin is used to control serial input/output data timing. The SCL input is used to positive edge clock data into EEPROM device and negative edge clock data out of each device. Maximum clock rate is 400 kHz. Serial Input/Output Data (SDA) The SDA pin is bidirectional for serial data transfer. The SDA pin needs to be pulled up by resistor as that pin is opendrain driven structure. Use proper resistor value for your system by considering VOL, IOL and the SDA pin capacitance. Except for a start condition and a stop condition which will be discussed later, the SDA transition needs to be completed during the SCL low period. Data Validity (SDA data change timing waveform) SCL SDA Data change Note: Data change High-to-low and low-to-high change of SDA should be done during the SCL low period. Device Address (A0, A1, A2) Four devices can be wired for one common data bus line as maximum. Device address pins are used to distinguish each device and device address pins should be connected to VCC or VSS . When device address code provided from SDA pin matches corresponding hard-wired device address pins A0 to A2, that one device can be activated. Pin Connections for A0 to A2 Memory size Max connect number 4k bit Note: 4 Pin connection A1 A2 VCC/VSS * 1 VCC/VSS * 1 Note A0 * 2 Use A0 for memory address a8 1. During floating, “VCC/VSS” are fixed to VSS , because these are internally pulled-down. 2. Floating state can be possible, because it is not connected inside. Write Protect (WP) When the Write Protect pin (WP) is high, the write protection feature is enabled and operates as shown in the following table. Also, acknowledgment "0" is outputted after inputting device address and memory address. After inputting write data, acknowledgment "1"(NO ACK) is outputted. When the WP is low, write operation for all memory arrays are allowed. The read operation is always activated irrespective of the WP pin status. The WP pin is internally pulled-down to VSS. Write operations for all memory array are allowed if unconnected. Write Protect Area WP pin status Write protect area 4k bit VIH VIL Full (4k bit) Normal read/write operation R10DS0123EJ0100 Rev.1.00 Apr. 08, 2013 Page 6 of 15 R1EV24004ASAS0I Functional Description Start Condition A high-to-low transition of the SDA with the SCL high is needed in order to start read, write operation (See start condition and stop condition). Stop Condition A low-to-high transition of the SDA with the SCL high is a stop condition. The stand-by operation starts after a read sequence by a stop condition. In the case of write operation, a stop condition terminates the write data inputs and place the device in a internally-timed write cycle to the memories. After the internally-timed write cycle which is specified as tWC, the device enters a standby mode (See write cycle timing). Start Condition and Stop Condition SCL SDA (in) Start condition Stop condition Acknowledge All addresses and data words are serially transmitted to and from in 8-bit words. The receiver sends a zero to acknowledge that it has received each word. This happens during ninth clock cycle. The transmitter keeps bus open to receive acknowledgment from the receiver at the ninth clock. In the write operation, EEPROM sends a zero to acknowledge after receiving every 8-bit words. In the read operation, EEPROM sends a zero to acknowledge after receiving the device address word. After sending read data, the EEPROM waits acknowledgment by keeping bus open. If the EEPROM receives zero as an acknowledge, it sends read data of next address. If the EEPROM receives acknowledgment "1" (no acknowledgment) and a following stop condition, it stops the read operation and enters a stand-by mode. If the EEPROM receives neither acknowledgment "0" nor a stop condition, the EEPROM keeps bus open without sending read data. Acknowledge Timing Waveform SCL SDA IN 1 2 8 9 Acknowledge out SDA OUT R10DS0123EJ0100 Rev.1.00 Apr. 08, 2013 Page 7 of 15 R1EV24004ASAS0I Device Addressing The EEPROM device requires an 8-bit device address word following a start condition to enable the chip for a read or a write operation. The device address word consists of 4-bit device code, 3-bit device address code and 1-bit read/write(R/W) code. The most significant 4-bit of the device address word are used to distinguish device type and this EEPROM uses “1010” fixed code. The device address word is followed by the 2-bit device address code A2, A1 memory adderess a8. The device address code selects one device out of four devices which are connected to the bus. This means that the device is selected if the inputted 2-bit device address code are equal to the corresponding hardwired A2 , A1 pin status. The eighth bit of the device address word is the read/write(R/W) bit. A write operation is initiated if this bit is “0” and a read operation is initiated if this bit is “1” . The EEPROM turns to a stand-by state if the device code is not “1010” or device address code doesn’t coincide with status of the correspond hard-wired device address pins A2 to A0. Device Address Word 4k Note: 1 Device code (fixed) 0 1 Device address word (8-bit) Device address code 0 A2 A1 a8 R/W code*1 R/W 1. R/W=“1” is read and R/W = “0” is write. R10DS0123EJ0100 Rev.1.00 Apr. 08, 2013 Page 8 of 15 R1EV24004ASAS0I Write Operations (WP=Low) Byte Write: (Write operation during WP=Low status) A write operation requires an 8-bit device address word with R/W = “0”. Then the EEPROM sends acknowledgment "0" at the ninth clock cycle. After these, the 4k bit EEPROM receives 8-bit memory address words. Upon receipt of this memory address, the EEPROM outputs acknowledgment "0" and receives a following 8-bit write data. After receipt of write data, the EEPROM outputs acknowledgment "0". If the EEPROM receives a stop condition, the EEPROM enters an internally-timed write cycle and terminates receipt of SCL, SDA inputs until completion of the write cycle. The EEPROM returns to a standby mode after completion of the write cycle. Byte Write Operation WP W ACK ACK R/W Start Write data (n) D7 D6 D5 D4 D3 D2 D1 D0 1010 a7 a6 a5 a4 a3 a2 a1 a0 4k Memory address (n) a8 Device address ACK Stop Page Write: (Write operation during WP=Low status) The EEPROM is capable of the page write operation which allows any number of bytes up to 16 bytes to be written in a single write cycle. The page write is the same sequence as the byte write except for inputting the more write data. The page write is initiated by a start condition, device address word, memory address(n) and write data (Dn) with every ninth bit acknowledgment. The EEPROM enters the page write operation if the EEPROM receives more write data (Dn+1) instead of receiving a stop condition. The a0 to a3 address bits are automatically incremented upon receiving write data (Dn+1). The EEPROM can continue to receive write data up to 16 bytes. If the a0 to a3 address bits reaches the last address of the page, the a0 to a3 address bits will roll over to the first address of the same page and previous write data will be overwritten. Upon receiving a stop condition, the EEPROM stops receiving write data and enters internally-timed write cycle. Page Write Operation WP Start R10DS0123EJ0100 Rev.1.00 Apr. 08, 2013 ACK R/W ACK Write data (n+m) D5 D4 D3 D2 D1 D0 W Write data (n) D7 D6 D5 D4 D3 D2 D1 D0 1010 a7 a6 a5 a4 a3 a2 a1 a0 4k Memory address (n) a8 Device address ACK ACK Stop Page 9 of 15 R1EV24004ASAS0I Write Operations (WP=High) Byte Write: (Write operation during WP=High status) A write operation requires an 8-bit device address word with R/W = “0”. Then the EEPROM sends acknowledgment "0" at the ninth clock cycle. After these, the 4k bit EEPROM receives 8-bit memory address. Upon receipt of this memory address, the EEPROM outputs acknowledgment "0". After receipt of 8-bit write data, the EEPROM outputs acknowledgment "1"(NO ACK). Then the EEPROM write operations are not allowed. Byte Write Operation 1010 W Memory address (n) Write data (n) D7 D6 D5 D4 D3 D2 D1 D0 4k a8 Device address a7 a6 a5 a4 a3 a2 a1 a0 WP ACK R/W Start ACK No ACK Stop Page Write: (Write operation during WP=High status) The page write is the same sequence as the byte write. The page write is initiated by a start condition, device address word and memory address(n) with every ninth bit acknowledgment"0". But after inputting write data(Dn) , the EEPROM outputs acknowledgment "1"(NO ACK). Then the EEPROM write operations are not allowed. Page Write Operation WP Start R10DS0123EJ0100 Rev.1.00 Apr. 08, 2013 ACK R/W No ACK No ACK Write data (n+m) D5 D4 D3 D2 D1 D0 W Write data (n) D7 D6 D5 D4 D3 D2 D1 D0 1010 a7 a6 a5 a4 a3 a2 a1 a0 4k Memory address (n) a8 Device address ACK Stop Page 10 of 15 R1EV24004ASAS0I Acknowledge Polling: Acknowledge polling feature is used to show if the EEPROM is in a internally-timed write cycle or not. This feature is initiated by the stop condition after inputting write data. This requires the 8-bit device address word following the start condition during a internally-timed write cycle. Acknowledge polling will operate when the R/W code = “0”. Acknowledgment “1” (no acknowledgment) shows the EEPROM is in a internally-timed write cycle and acknowledgment “0” shows that the internally-timed write cycle has completed. See Write Cycle Polling using ACK. Write Cycle Polling Using ACK Send write command Send stop condition to initiate write cycle Send start condition Send device address word with R/W = 0 ACK returned No Yes Next operation is addressing the memory No Yes Proceed write operation R10DS0123EJ0100 Rev.1.00 Apr. 08, 2013 Send memory address Send start condition Proceed random address read operation Send stop condition Send stop condition Page 11 of 15 R1EV24004ASAS0I Read Operation There are three read operations: current address read, random read, and sequential read. Read operations are initiated the same way as write operations with the exception of R/W = “1”. Current Address Read: The internal address counter maintains the last address accessed during the last read or write operation, with incremented by one. Current address read accesses the address kept by the internal address counter. After receiving a start condition and the device address word (R/W is “1”), the EEPROM outputs the 8-bit current address data from the most significant bit following acknowledgment “0”. If the EEPROM receives acknowledgment “1” (no acknowledgment) and a following stop condition, the EEPROM stops the read operation and is turned to a standby state. In case the EEPROM has accessed the last address of the last page at previous read operation, the current address will roll over and returns to zero address. In case the EEPROM has accessed the last address of the page at previous write operation, the current address will roll over within page addressing and returns to the first address in the same page. The current address is valid while power is on. The current address after power on will be indefinite. The random read operation described below is necessary to define the memory address. Current Address Read Operation Device address 1010 Start 1* R D7 D6 D5 D4 D3 D2 D1 D0 4k Read data (n+1) ACK R/W No ACK Stop Note :1*Don't care bit R10DS0123EJ0100 Rev.1.00 Apr. 08, 2013 Page 12 of 15 R1EV24004ASAS0I Random Read: This is a read operation with defined read address. A random read requires a dummy write to set read address. The EEPROM receives a start condition, device address word (R/W=0) and memory address 8-bit sequentially. The EEPROM outputs acknowledgment “0” after receiving memory address then enters a current address read with receiving a start condition. The EEPROM outputs the read data of the address which was defined in the dummy write operation. After receiving acknowledgment “1”(no acknowledgment) and a following stop condition, the EEPROM stops the random read operation and returns to a standby state. Random Read Operation W ACK R/W Start Device address 1010 Start ACK Dummy write Read data (n) # # 1* R D7 D6 D5 D4 D3 D2 D1 D0 1010 @@ 1* a8 4k Memory address (n) a7 a6 a5 a4 a3 a2 a1 a0 Device address R/W ACK No ACK Stop Currect address read Notes: 1. Don't care bit 2. 2nd device address code (#) should be same as 1st (@). Sequential Read: Sequential reads are initiated by either a current address read or a random read. If the EEPROM receives acknowledgment “0” after 8-bit read data, the read address is incremented and the next 8-bit read data are coming out. This operation can be continued as long as the EEPROM receives acknowledgment “0”. The address will roll over and returns address zero if it reaches the last address of the last page. The sequential read can be continued after roll over. The sequential read is terminated if the EEPROM receives acknowledgment “1” (no acknowledgment) and a following stop condition. Sequential Read Operation ACK R/W Note: 1. Don't care bit Start R10DS0123EJ0100 Rev.1.00 Apr. 08, 2013 D7 D6 D5 D4 D3 D2 D1 D0 1* R D7 D6 D5 D4 D3 D2 D1 D0 1010 4k Read data (n+1) Read data (n+2) ACK ACK Read data (n+m) D5 D4 D3 D2 D1 D0 Device address No ACK Stop Page 13 of 15 R1EV24004ASAS0I Notes Data Protection at VCC On/Off When VCC is turned on or off, noise on the SCL and SDA inputs generated by external circuits (CPU, etc) may act as a trigger and turn the EEPROM to unintentional program mode. To prevent this unintentional programming, this EEPROM has a power on reset function. Be careful of the notices described below in order for the power on reset function to operate correctly. SCL and SDA should be fixed to VCC or VSS during VCC on/off. Low to high or high to low transition during VCC on/off may cause the trigger for the unintentional programming. VCC should be turned off after the EEPROM is placed in a standby state. VCC should be turned on from the ground level(VSS) in order for the EEPROM not to enter the unintentional programming mode. VCC turn on rate should be slower than 2 s/V. Noise Suppression Time This EEPROM have a noise suppression function at SCL and SDA inputs, that cut noise of width less than 50 ns. Be careful not to allow noise of width more than 50 ns. Power Source Noise Countermeasures In order to suppress power-source-noise which causes malfunction of the device, it is recommended to put 0.1uF bypass-capacitor (such as a monolithic ceramic capacitor which has good high-frequency characteristics) between VCC and VSS, and shorten the wiring length between the capacitor and VCC/VSS terminals as much as possible. Device Address Input, Write Protect input These can be used in the open state because these are pulled down inside the device. But please note that the noise does not enter due to wiring connections at the floating state. If you connect the wiring, we recommend that you connect to Vcc or Vss to avoid malfunction due to noise. R10DS0123EJ0100 Rev.1.00 Apr. 08, 2013 Page 14 of 15 R1EV24004ASAS0I Package Dimensions R1EV24004ASAS0I (PRSP0008DF-B / Previous Code: FP-8DBV) JEITA Package Code P-SOP8-3.9x4.89-1.27 RENESAS Code PRSP0008DF-B *1 Previous Code FP-8DBV MASS[Typ.] 0.08g D 8 F NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 5 *2 c E HE bp Index mark Terminal cross section ( Ni/Pd/Au plating ) Reference Dimension in Millimeters Symbol 4 1 Z e *3 bp x M A L1 A1 θ L y Detail F R10DS0123EJ0100 Rev.1.00 Apr. 08, 2013 D E A2 A1 A bp b1 c c1 θ HE e x y Z L L1 Min Nom Max 4.89 5.15 3.90 0.102 0.14 0.254 1.73 0.35 0.40 0.45 0.15 0.20 0.25 0° 8° 5.84 6.02 6.20 1.27 0.25 0.10 0.69 0.406 0.60 0.889 1.06 Page 15 of 15 Revision History Rev. 0.01 1.00 R1EV24004ASAS0I Data Sheet Date Page Aug. 23, 2012 Apr. 08, 2013 — — Description Summary Initial issue Delete Preliminary All trademarks and registered trademarks are the property of their respective owners. C-1 Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. 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