DAC-S FEATURES PRODUCT OVERVIEW 100MHz conversion rate The DAC-S is a 12-bit, ultra high speed, current output digital-to-analog converter. This TTL/CMOS compatible device converts at a rate of 100MHz and features a 3.0pV-s glitch energy and excellent frequency domain specifications. Low power, 650mW, typical Low glitch energy, 3.0pV-s Excellent dynamic specifications TTL/CMOS compatible inputs 20ns settling time Pin compatible with Analog Devices AD9713 Models available in commercial (0 to + 70°C), industrial (–40 to +100°C), or military (–55 to +125°C) operating temperature ranges The DAC-S develops complementary current outputs of 0 to –20.48mA and can directly drive 50 Ohm loads. The excellent dynamic specifications (to Nyquist at fOUT=2.02MHz) include an SFDR of –85dB. Static performance includes maximum over temperature specifications of ±.1.75LSB and ±1.5LSB for integral and differential nonlinearity, respectively. The DAC-S achieves low power and high speed performance from an advanced BiCMOS process. The architecture employs an R/2R resistor network and a segmented switching current cell arrangement to reduce glitch. Laser trimming assures that 12-bit linearity is achieved and maintained over the transfer curve. It also incorporates a 12-bit input data register and bandgap voltage reference with a buffer amplifier. The DAC-S runs on +5V and –5.2V supplies and dissipates a maximum of 802mW. It is available in a 28-pin CLCC package with an operating temperature range of 0 to 70°C or –55 to +125°C. FUNCTIONAL BLOCK DIAGRAM BIT 1 ( MSB ) 28 BIT 2 1 BIT 3 2 BIT 4 3 BIT 5 4 BIT 6 5 BIT 7 6 BIT 8 7 BIT 9 8 BIT 10 9 BIT 11 10 12-BIT MASTER REGISTER 8 LSBs CURRENT CELLS DATA BUFFER LEVEL SHIFTER SLAVE REGISTER R / 2R NETWORK 15 SWITCHED CURRENT CELLS UPPER 4-BIT DECODER BIT 12 ( LSB ) 11 REF CELL 14 IOUT 16 IOUT 17 Ref In Latch Enable 26 Data Clock + – OVERDRIVEABLE VOLTAGE REFERENCE RefGND 22 23 +5V SUPPLY 12,21 –5.2V DIGITAL SUPPLY 13 AGND DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA 20 REF OUT • Tel: (508) 339-3000 24 RSET • 19 CTRL IN www.datel.com 25 7 18 CTRL OUT 15,25 –5.2V ANALOG SUPPLY • 27 DGND e-mail: [email protected] 26 Jun 2015 MDA_DAC-S.B06 Page 1 of 7 DAC-S ABSOLUTE MAXIMUM RATINGS LIMITS PARAMETERS +5.5 +5V Digital Supply –5.5 –5.2V Digital Supply –5.5 –5.2V Analog Supply –0.5 to +5V Supply level Digital Input Voltages ±2.5 Internal Reference Output Current 2.5 to 0 Voltage from CTRL IN to –5.2V (A) Supply ±2.5 CTRL OUT Output Current –5.2V (A) Supply Level to –3.7 Reference Input Voltage Range 30 Analog Output Current, IOUT 300 Lead Temperature (10 seconds) PHYSICAL/ENVIRONMENTAL PARAMETERS Operating Temperature Range DAC-S/MC & -C DAC-S/ME & -C DAC-S & -C Storage Temperature Range Thermal Resistance, θja Junction Temperature Package Type UNITS Volts Volts Volts Volts mA Volts mA Volts mA °C MIN. TYP. MAX. UNITS 0 –40 –55 –65 — +70 — +100 — +125 — +150 24 — +150 28 Pin CLCC °C °C °C °C (°C/W) °C — FUNCTIONAL SPECIFICATIONS (TA = See specification table, –5.2V (A) Supply = –5.2V (D) Supply = –4.94 to –5.46V, +5V Supply = 4.75 to 5.25V, VREF = Internal, RL = 50 Ohms and fs = 100MHz unless otherwise specified.) DIGITAL INPUTS Resolution Logic Levels Logic "1" Logic "0" Logic Loading "1" Logic Loading "0" Digital Input Capacitance, CIN MIN. 12 0 TO +70°C TYP. — MAX. — MIN. 12 –55 TO +125°C TYP. — MAX. — UNITS Bits +2.0 — — — — — — — — 3.0 — +0.8 400 700 15 +2.0 — — — — — — — — 3.0 — +0.8 400 700 15 Volts Volts μA μA pF TIMING CHARACTERISTICS Data setup time, tSU Data Hold Time, tHLD Propagation Delay Time, tPD CLOCK Pulse Width, TPW1, TPW2 3 0.5 — 3 2 0.25 4.5 — — — 7 — 3 0.5 — 3 2 0.25 4.5 — — — 7 — ns ns ns ns STATIC PERFORMANCE Integral Nonlinearity ➀ Differential Nonlinearity Offset Error Gain Error ➁ — — — — ±0.75 ±0.5 20 ±1 ±1.0 ±.75 75 ±10 — — — — ±1.0 0.5 20 ±1 ±1.75 ±1 75 ±10 LSB LSB μA % 100 — — 100 — — MHz — — 11 20 13 22 — — 12 20 15 22 ns ns — — 900 625 425 — — 2 3 1000 675 470 0.15 0.07 10 — — — — — — — — 900 625 425 — — 2 3 1000 675 470 0.15 0.07 10 — — — — — — pV-s pV-s V/μs ps ps % Deg — — — — — — 100 — — — — — — — — — — — — — — — — — — — — 100 82 77 75 80 78 79 — 77 74 71 76 75 75 — dB dB dB dB dB dB MSPS — –1.25 –20.48 — — 0 — –1.25 –20.48 — — 0 mA Volts DYNAMIC PERFORMANCE Conversion Rate ➂ Output Voltage Settling Time, tSET Full Scale Step to ±1LSB Full Scale Step to ±0.5LSB Glitch Area Singlet (Peak) Doublet (Net) Output Slew Rate Output Rise Time Output Fall Time Differential Gain Differential Phase Spurious Free Dynamic Range, SFDR fCLK=10MSPS, fOUT=1.23MHz fCLK=20MSPS, fOUT=5.055MHz fCLK=40MSPS, fOUT=16 MHz fCLK=50MSPS, fOUT= 10.1MHz fCLK=80MSPS, fOUT= 5.1MHz fCLK=100MSPS, fOUT=10.1MHz Throughput rate ANALOG OUTPUT Full Scale Output Current Output Voltage Compliance ➃ DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: [email protected] 26 Jun 2015 MDA_DAC-S.B06 Page 2 of 7 DAC-S MAX. –1.17 100 +50 MIN. –1.27 — –125 –55 TO +125°C TYP. –1.23 175 — MAX. –1.17 100 +50 UNITS Volts μV/°C μA 50 12 — — — 10 50 12 — — μV kOhms 200 1.4 — — 50 3 200 1.4 — — MHz kOhms 3 — 1 3 — MHz 10 — 4 10 — MHz +4.75 –4.94 — — +5.25 –5.46 +4.75 –4.94 — — +5.25 –5.46 Volts Volts — — — — — 13 70 42 650 5 20 85 50 800 10 — — — — — 13 70 42 650 5 20 95 50 800 10 mA mA mA mW μA/V INTERNAL REFERENCE/AMPLIFIER MIN. Reference Voltage, VREF –1.27 Reference Voltage Drift — Reference Current Sink/Source Capability –125 Reference Load Regulation (IREF = 0 to –125μA) — Reference Input (CTRL IN) Impedance — Reference Input (CTRL IN) Multiplying Bandwidth (100mV sine wave, to -3dB loss at IOUT) 50 Input Impedance at REF OUT 3 Amplifier Large Signal Bandwidth (4V p-p sine wave input, to slew rate limit) 1 Amplifier Small Signal Bandwidth (1V p-p sine wave input, to –3dB loss) 4 POWER REQUIREMENTS Power Supply Ranges +5V Supply –5.2V Supplies Power Supply Currents +5V Supply –5.2V Digital Supply –5.2V Analog Supply Power Dissipation Power Supply Rejection (±5% variation) 0 TO +70°C TYP. –1.23 50 Footnotes: ➀ Best fit straight line. ➁ Gain Error measured as the error in the ratio between the full scale output current and the current through RSET (1.28mA typ.). Ideally the ratio should be 16. ➂ Clock frequency range is from DC to the guaranteed minimum conversion rate. ➃ Dynamic Range must be limited to a 1V swing within the compliance range. TECHNICAL NOTES Clock Termination The internal 12-bit register is updated on the rising edge of the Latch Enable (pin 26). To minimize reflections and noise at high clock speeds proper termination techniques should be used. In the PCB layout the clock runs should be kept as short as possible and have minimal loading. The PCB should employ a controlled characteristic line impedance (Z0) of 50 Ohms. A shunt termination resistor, equal to Z0, should be placed as close to the CLOCK pin as possible, see Figure 2. The rise, fall and propagation delay times will be effected by the shunt termination resistor. The sum of the two currents is always equal to the full scale current minus one LSB. See Table 1. The output can be converted to a voltage through a load resistor, typically 50 Ohms. Both current outputs should have the same load resistance value. See Figure 2. The output voltage generated is: VOUT = IOUT (ROUT || 227 Ohms) where 227 Ohms is the nominal DAC output resistance. Table 1. Input Coding Table Digital Inputs INPUT CODE The DAC-S is TTL/CMOS compatible. Data is latched by a Master register. MSB Iout (mA) Iout (mA) Outputs 1111 1111 1111 –20.48 0 The outputs IOUT (pin 14) and IOUT (pin 16) are complementary current outputs. Current is steered to either IOUT or IOUT in proportion to the input code. 1000 0000 0000 –10.24 –10.24 0000 0000 0000 0 –20.48 DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA • Tel: (508) 339-3000 • LSB www.datel.com • e-mail: [email protected] 26 Jun 2015 MDA_DAC-S.B06 Page 3 of 7 DAC-S POWER SUPPLIES REFERENCE In order to reduce power supply noise separate –5.2V analog and digital power supplies should be used. The power supply lines should be bypassed with 0.1μF and 0.01μF ceramic capacitors placed as close to the –5.2V analog pins (15, 25) and digital pins (12, 21) as possible. The analog and digital power supply ground returns should be connected at one point as close to the power source as possible. The +5V supply pin (23) should be bypassed with a 0.1μF ceramic capacitor connected as close to the pin as possible. See Figure 2. The internal reference is a –1.23V, typical, bandgap voltage reference. The internal reference is connected to Reference OUT (REF OUT, pin 20) and the internal control Amplifier (CTRL IN, pin 19). The control Amplifier OUT (CTRL OUT, pin 18) should be connected to Reference IN (REF IN, pin17) and to –5.2V (pin 15) Analog Supply through a 0.1μF ceramic capacitor (as shown in figure 2) in order to improve the settling time This reduces switching noise and improves output settling time. The Full Scale Output Current, IOUT (pin 14) and IOUT (pin 16), is controlled by the REF OUT (pin 20) voltage and the RSET (pin 24) resistor through the following equation: Full Scale IOUT = [REF OUT Voltage/(RSET Resistance + 100Ω)] x 16 Note: Internal 100Ω is ± 1% tolerance The internal reference (REF OUT) may be overdriven with a more precise external reference, capable of delivering up to 2mA, to provide better over temperature performance. -5.2V (A) +5V (D) 0.1μ F (17) REF IN 0.1μ F (18) CTRL OUT +5V (D) (23) (19) CTRL IN (20) REF OUT BIT 1 ( MSB) BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 9 BIT 10 BIT 11 BIT 12 (LSB) (28) (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) 50 7 DAC-S 507 (16) IOUT 100Ω (24) RSET 976 7 LATCH ENABLE (26) –5.2V (D) 507 D/A OUT (14) IOUT DGND (27) (22) REF GND –5.2V (A) (13) AGND 0.1μ F 0.01μ F –5.2 V (D) (12, 21) (15, 25) –5.2 V (A) 0.01μ F 0.1μ F Figure 2. Typical Connection Diagram DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: [email protected] 26 Jun 2015 MDA_DAC-S.B06 Page 4 of 7 DAC-S TPW2 TPW1 CLOCK 50% tSU tSU tSU tHLD tHLD tHLD DATA IN tSET tPD ½ LSB CHANGE IOUT ½ LSB CHANGE tPD tSET tSET tPD Figure 3a. Timing Diagram CLOCK 50% DATA IN ±1/2 LSB ERROR BAND IOUT tSET tPD Figure 3b. Full Scale Settling Time Diagram DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: [email protected] 26 Jun 2015 MDA_DAC-S.B06 Page 5 of 7 DAC-S 28 680 Clock Frequency Does Not Alter Power Dissipation 24 mW μA 640 20 600 16 560 12 –50 –30 –10 10 50 30 70 – 40 90 –20 20 0 40 60 100 80 Temperature Temperature Figure 5a. Typical Power Dissipation Over Temperature Figure 5b. Offset Current Over temperature 1.5 0.8 0.4 LSB LSB 0.5 –0.5 0.0 –0.4 –0.8 1.5 0 600 1200 1800 2400 3000 3600 4200 400 1000 1600 2200 Code Figure 5c. Typical INL 3400 4000 Figure 5d. Typical DNL 10dB/ 10dB/ FC = 80MHz FC = 100MHz FO =2.02MHz FO =2.02MHz S S C C Start Frequency 500 kHz 2800 Code Stop Frequency 40MHz Start Frequency 500 kHz Figure 5e. Spurious Free Dynamic Range = 70.5dB DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA Stop Frequency 50MHz Figure 5f. Spurious Free Dynamic range = 70dB • Tel: (508) 339-3000 • www.datel.com • e-mail: [email protected] 26 Jun 2015 MDA_DAC-S.B06 Page 6 of 7 DAC-S INPUT/OUTPUT CONNECTIONS MECHANICAL DIMENSIONS (inches (mm)) PIN FUNCTION PIN FUNCTION 1 D2, Digital input bit 2 28 D1 (MSB), Digital input bit 1 2 D3, Digital input bit 3 27 DGND, Digital Ground 3 D4, Digital input bit 4 26 LATCH ENABLE, Data Clock Pin (Rising Edge) 4 D5, Digital input bit 5 25 ANALOG VEE, Nomimally –5.2V 5 D6, Digital input bit 6 24 RSET, where RSET=(VREF OUT/ FS IOUT) x 16 6 D7, Digital input bit 7 23 DIGITAL VCC, Nomimally +5V 7 D8, Digital input bit 8 22 REF GND, Connected closely to pin 13 & RSET ground side 8 D9, Digital input bit 9 21 DIGITAL VEE, Nomimally –5.2 9 D10, Digital input bit 10 20 REF OUT, –1.26V connected to CTRL AMP IN (Pin 19), Can be connected to an External Ref 10 D11, Digital input bit 11 19 CONTROL AMP IN, Connected to REF OUT (Pin 20), Can be connected to an External Ref 11 D12, (LSB) Digital input bit 12 18 CONTROL AMP OUT, Usually connected to REF IN (Pin 17) 12 DIGITAL VEE, Nomimally –5.2V 17 REF IN, Usually connected to CTRL AMP OUT (Pin 18) 13 ANALOG GND, Connected closely to pin 22 & RSET ground side 16 IOUT, Complementary analog output current, Zero scale output when all “1” 14 IOUT, Analog output current, Full scale output when inputs all "1" 15 ANALOG VEE, Analog VEE, Nominally -5.2V A 18 17 16 15 14 13 12 19 11 DATEL DAC-S 20 21 10 9 C 22 8 23 7 24 6 25 5 26 27 28 1 2 3 B 4 E D G F SYMBOL INCHES A 0.300 B 0.466 C 0.450 D 0.090 E 0.420 F 0.050 G 0.055 ORDERING INFORMATION MODEL DAC-S/MC DAC-S/MC-C DAC-S/ME DAC-S/ME-C DAC-S DAC-S-C OPERATING TEMPERATURE RANGE PACKAGE RoHS 0 to 70°C 0 to 70°C 28-PIN CLCC 28-PIN CLCC 28-PIN CLCC 28-PIN CLCC 28-PIN CLCC 28-PIN CLCC No Yes No Yes No Yes –40 to 100°C –40 to 100°C –55 to 125°C –55 to 125°C DATEL is a registered trademark of DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA DATEL, Inc. makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice. ITAR and ISO 9001/14001 REGISTERED © 2015 DATEL, Inc. www.datel.com • e-mail: [email protected] 26 Jun 2015 MDA_DAC-S.B06 Page 7 of 7