Memory ICs 4,096-Bit Serial Electrically Erasable PROM BR93LC66 / BR93LC66F / BR93LC66RF / BR93LC66FV •• Features Low power CMOS Technology • 256 × 16 bit configuration • 2.7V to 5.5V operation • Low power dissipation – 3mA (max.) active current: 5V – 5µA (max.) standby current: 5V • Auto increment for efficient data bump • Automatic erase-before-write • Hardware and software write protection – Default to write-disable state at power up – Software instructions for write-enable / disable – Vcc lockout inadvertent write protection • 8-pin SOP / 8-pin SSOP-B / 8-pin DIP packages • Device status signal during write cycle • TTL compatible Input / Output • 100,000 ERASE / write cycles • 10 years Data Retention •Pin assignments CS 1 SK 2 DI 3 BR93LC66 / BR93LC66RF DO 4 8 VCC NC 1 7 N.C. VCC 2 6 N.C. CS 3 5 GND SK 4 BR93LC66F / BR93LC66FV 8 N.C. 7 GND 6 DO 5 DI •Pin descriptions Pin Name Function CS Chip select input SK Serial clock input DI DO Start bit, operating code, address, and serial data input Serial data output, READY / BUSY internal status display output GND Ground N.C. Not connected N.C. Not connected VCC Power supply •TheOverview BR93LC66 series are CMOS serial input / output-type memory circuits (EEPROMs) that can be programmed electrically. Each is configured of 256 words × 16 bits (4096 bits), and each word can be accessed individually and data read from it and written to it. Operation control is performed using five types of commands. The commands, addresses, and data are input through the DI pin under the control of the CS and SK pins. In a write operation, the internal status signal (READY or BUSY) can be output from the DO pin. 1 Memory ICs BR93LC66 / BR93LC66F / BR93LC66RF / BR93LC66FV •Block diagram Power supply CS voltage detector Command code Control High voltage Write disable SK generator Clock generation Address DI Address 8bit Command buffer decoder Data R/W 8bit register 4096bit 16bit register DO amplifier Dummy bit •Absolute maximum ratings (Ta = 25°C) Parameter Symbol Limits Unit VCC – 0.3 ~ + 6.5 V Applied voltage 500∗1 BR93LC66 Power dissipation BR93LC66F / RF BR93LC66FV 350∗2 Pd mW 300∗3 Storage temperature Tstg Operating temperature Topr — Terminal voltage – 65 ~ + 125 °C – 40 ~ + 85 °C – 0.3 ~ VCC + 0.3 V ∗1 Reduced by 5.0mW for each increase in Ta of 1°C over 25°C. ∗2 Reduced by 3.5mW for each increase in Ta of 1°C over 25°C. ∗3 Reduced by 3.0mW for each increase in Ta of 1°C over 25°C. •Recommended operating conditions (Ta = 25°C) Parameter Power supply voltage Input voltage 2 Writing Reading Symbol VCC VIN Min. Typ. Max. Unit 2.7 — 5.5 V 2.0 — 5.5 V 0 — VCC V EEPROM array 16bit Memory ICs BR93LC66 / BR93LC66F / BR93LC66RF / BR93LC66FV •Electrical characteristics (unless otherwise noted, Ta = – 40 to 85°C, V CC Parameter Symbol Input low level voltage Min. VIL – 0.3 = 5V ± 10%) Typ. Max. Unit Conditions — 0.8 V — Input high level voltage VIH 2.0 — VCC + 0.3 V Output low level voltage 1 VOL1 — — V Output high level voltage 1 VOH1 2.4 — — V IOH = – 0.4mA Output low level voltage 2 VOL2 — — 0.2 V IOL = 10µA Output high level voltage 2 VOH2 VCC – 0.4 — — V IOH = – 10µA 0.4 — IOL = 2.1mA Input leakage current ILI – 1.0 — 1.0 µA VIN = 0V ~ VCC Output leakage current ILO – 1.0 — 1.0 µA VOUT = 0V ~ VCC, CS = GND Operating current dissipation 1 Operating current dissipation 2 ICC1 — 1.5 3 mA VIN = VIH / VIL, DO = OPEN, fsk = 1MHz, WRITE ICC2 — 0.7 1.5 mA VIN = VIH / VIL, DO = OPEN, fsk = 1MHz, READ Standby current ISB — 1.0 5 µA CS = SK = DI = GND, DO = OPEN (unless otherwise noted, Ta = – 40 to 85°C, VCC = 3V ± 10%) Parameter Symbol Input low level voltage VIL Input high level voltage VIH Output low level voltage VOL Output high level voltage VOH Min. Unit Conditions V — VCC + 0.3 V — — 0.2 V IOL = 10µA VCC – 0.4 — — V IOH = – 10µA – 0.3 Typ. — 0.15 × VCC 0.7 × VCC — — Max. Input leakage current ILI – 1.0 — 1.0 µA VIN = 0V ~ VCC Output leakage current Operating current dissipation 1 Operating current dissipation 2 ILO – 1.0 — 1.0 µA VOUT = 0V ~ VCC, CS = GND ICC1 — 0.5 2 mA VIN = VIH / VIL, DO = OPEN, fsk = 250kHz, WRITE ICC2 — 0.2 1 mA VIN = VIH / VIL, DO = OPEN, fsk = 250kHz, READ Standby current ISB — 0.4 3 µA CS = SK = DI = GND, DO = OPEN •Electrical characteristics (unless otherwise noted, Ta = – 40 to 85°C, V CC Parameter Symbol Input low level voltage VIL Input high level voltage VIH Output low level voltage VOL Output high level voltage VOH Min. Unit Conditions — 0.15 × VCC V — 0.7 × VCC — VCC + 0.3 V — – 0.3 — Typ. Max. = 2.0V) — 0.2 V IOL = 10µA VCC – 0.4 — — V IOH = – 10µA Input leakage current ILI – 1.0 — 1.0 µA VIN = 0V ~ VCC Output leakage current ILO – 1.0 — 1.0 µA VOUT = 0V ~ VCC, CS = 0V Operating current dissipation 2 ICC2 — 0.2 1 mA VIN = VIH / VIL, DO = OPEN, fsk = 200kHz, READ Standby current ISB — 0.4 3 µA CS = SK = DI = 0V, DO = OPEN 3 Memory ICs BR93LC66 / BR93LC66F / BR93LC66RF / BR93LC66FV operation •(1)Circuit Command mode With these ICs, commands are not Start Operating Address Data Command code bit recognized or acted upon until the start bit is received. The start bit is 1 10 A7 ~ A0 — Read (READ)∗1 taken as the first “1” that is received 1 00 11XXXXXX — Write Enabled (WEN) after the CS pin rises. 1 01 A7 ~ A0 D15 ~ D0 Write (WRITE)∗2 ∗1 After setting of the read command 2 ∗ 1 00 01XXXXXX D15 ~ D0 Write to All Addresses (WRAL) and input of the SK clock, data corre1 00 00XXXXXX — Write Disabled (WDS) sponding to the specified address is 3 ∗ 1 11 A7 ~ A0 — output, with data corresponding to upErase (ERASE) per addresses then output in se1 00 10XXXXXX — Chip Erase (ERAL)∗3 quence. (Auto increment function) X: Either VIH or VIL ∗2 When the write or write all addresses command is executed, all data in the selected memory cell is erased automatically, and the input data is written to the cell. ∗3 These modes are optional modes. Please contact Rohm for information on operation timing. (2) Operation timing characteristics (unless otherwise noted, Ta = – 40 to 85°C, VCC = 5V ± 10%) Parameter Symbol Min. Typ. Max. Unit SK clock frequency fSK — — 1 MHz SK "H" time tSKH 450 — — ns SK "L" time — — ns tSKL 450 CS "L" time tCS 450 — — ns CS setup time tCSS 50 — — ns DI setup time tDIS 100 — — ns CS hold time tCSH 0 — — ns DI hold time tDIH 100 — — ns Data "1" output delay time tPD1 — — 500 ns Data "0" output delay time tPD0 — — 500 ns Time from CS to output confirmation tSV — — 500 ns tDF — — 100 ns tE / W — — 10 ms Time from CS to output High impedance Write cycle time 4 Memory ICs BR93LC66 / BR93LC66F / BR93LC66RF / BR93LC66FV For low voltage operation (unless otherwise noted, Ta = – 40 to 85°C, VCC = 3V ± 10%) Parameter Min. Typ. Max. Unit fSK — — 250 kHz SK "H" time tSKH 1 — — µs SK "L" time tSKL 1 — — µs CS "L" time tCS 1 — — µs CS setup time tCSS 200 — — ns DI setup time tDIS 400 — — ns CS hold time tCSH 0 — — ns DI hold time tDIH 400 — — ns Data "1" output delay time tPD1 — — 2 µs Data "0" output delay time tPD0 — — 2 µs Time from CS to output confirmation tSV — — 2 µs Time from CS to output High impedance tDF — — 400 ns tE / W — — 25 ms SK clock frequency Write cycle time Symbol When reading at low voltage (Unless otherwise noted, Ta = – 40 to 85°C, VCC = 2.0V) Parameter Symbol Min. Typ. Max. Unit SK clock frequency fSK SK "H" time tSKH — — 200 kHz 2 — — µs SK "L" time CS "L" time tSKL 2 — — µs tCS 2 — — µs CS setup time tCSS 400 — — ns DI setup time tDIS 800 — — ns CS hold time tCSH 0 — — ns DI hold time tDIH 800 — — ns Data "1" output delay time tPD1 — — 4 µs Data "0" output delay time tPD0 — — 4 µs Time from CS to output High impedance tDF — — 800 ns 䊊 Not designed for radiation resistance. 5 Memory ICs BR93LC66 / BR93LC66F / BR93LC66RF / BR93LC66FV (3) Timing chart CS tCSS tSKH tSKL tCSH SK tDIS tDIH DI tPD0 tPD1 tDF DO (READ) tDF STATUS VALID DO (WRITE) • Data is acquired from DI in synchronization with the SK rise. • During a reading operation, data is output from DO in synchronization with the SK rise. • During a writing operation, a Status Valid (READY or BUSY) is valid from the time CS is HIGH until time tcs after CS falls following the input of a write command and before the output of the next command start bit. Also, CS must be in a HIGH-Z state when DO is LOW. • After the completion of each mode, make sure that CS is set to LOW, to reset the internal circuit, before changing modes. Fig.1 Data synchronization timing 6 Memory ICs BR93LC66 / BR93LC66F / BR93LC66RF / BR93LC66FV (4) Reading (Figure 2) When the read command is acknowledged, the data (16 bits) for the input address is output serially. The data is synchronized with the SK rise during A0 acquisition and a “0” (dummy bit) is output. All further data is output in synchronization with the SK pulse rises. (5) Write enable (Figure 3) These ICs are set to the write disabled state by the internal reset circuit when the power is turned on. Therefore, before performing a write command, the write enable command must be executed. When this command is executed, it remains valid until a write disable command is issued or the power supply is cut off. However, read commands can be used in either the write enable or write disable state. CS (6) Write (Figure 4) This command writes the input 16-bit data (D15 to D0) to the specified address (A7 to A0). Actual writing of the data begins after CS falls (following the 27th clock pulse after the start bit input), and DO is in the Acquire state. STATUS is not detected if CS = LOW after the time tE / W. When STATUS is detected (CS = HIGH), no commands are accepted while DO is LOW (BUSY). Therefore, no commands should be input during this period. ∗1 SK DI 1 2 1 1 4 0 11 A7 A6 12 27 28 A0 A1 ∗2 DO 0 D15 D14 D1 D0 D15 D14 High-Z ∗1 If the first data input following the rise of the start bit CS is "1", the start bit is acknowledged. Also, if a "1" is input following several zeroes in succession, the "1" is recognized as the start bit, and subsequent operation commences. This applies also to all commands described subsequently. ∗2 Address auto increment function: These ICs are equipped with an address auto increment function which is effective only during reading operations. With this function, if the SK clock is input following execution of one of the above reading commands, data is read from upper addresses in succession. CS is held in HIGH state during automatic incrementing. Fig.2 Read cycle timing (READ) CS SK DI 1 0 0 1 1 DO High-Z Fig.3 Write enable cycle timing 7 Memory ICs BR93LC66 / BR93LC66F / BR93LC66RF / BR93LC66FV CS tCS 1 SK DI 1 2 0 4 A7 1 A6 A1 11 12 A0 D15 STATUS 27 D14 D1 D0 tSV DO BUSY READY High-Z tE / W Fig.4 Write cycle timing (WRITE) CS tCS 1 SK DI 1 2 0 5 0 12 D15 D14 0 STATUS 27 D1 D0 tSV DO BUSY READY High-Z tE / W Fig.5 Write all address cycle timing (WRAL) (STATUS) After time tCS following the fall of CS, after input of the write command), if CS is set to HIGH, the write execute = BUSY (LOW) and the command wait status READY (HIGH) are output. If in the command wait status (STATUS = READY), the next command can be performed within the time tE / W. Thus, if data is input via SK and DI with CS = HIGH in the t E / W period, erroneous operations may be performed. To avoid this, make sure that DI = LOW when CS = HIGH. (Caution is especially important when common input ports are used.) This applies to all of the write commands. (7) All address write (Figure 5) With this command, the input 16-bit data is written simultaneously to all of the addresses (128 words). Rather than writing one word at a time, in succession, data is written all at one time, enabling a write time of t E / W. (8) Write disable (Figure 6) When the power supply is turned on, the IC enters the write disable status. Similarly, when a write disable command is issued, the IC enters the same status. When in this status, all write commands are ignored, but read commands may be executed. In the write enable status, writing begins even if a write command is entered accidentally. To prevent errors of this type, we recommend executing a write disable command after writing has been completed. CS SK DI 1 0 0 0 0 DO High-Z Fig.6 Write disable cycle timing (WDS) 8 Memory ICs BR93LC66 / BR93LC66F / BR93LC66RF / BR93LC66FV notes •(1)Operation Cancelling modes 〈READ〉 Start bit Operating code Address Data 1bit 2bits 8bits 16bits Cancel can be performed for the entire read mode space Cancellation method: CS LOW 〈WRITE, WRAL〉 Start bit Operating code Address Data 1bit 2bits 8bits 16bits a tE / W b ∗ a: Canceled by setting CS LOW or VCC OFF ( ) b: Cannot be canceled by any method. If VCC is set to OFF during this time, the data in the designated address is not secured. : VCC OFF (VCC is turned off after CS is set to LOW) ∗ Fig.7 9 Memory ICs BR93LC66 / BR93LC66F / BR93LC66RF / BR93LC66FV (2) Timing in the standby mode As shown in Figure 8, during standby, if CS rises when SK is HIGH, the DI state may be read on the rising edge. If this happens, and DI is HIGH, this is taken to be the start bit, causing a bit error (see point “a” in Figure 8). Make sure all inputs are LOW during standby or when turning the power supply on or off (see Figure 9). Point a: Start bit position during erroneous operation Point b: Actual position of start bit SK To prevent erroneous writing, these ICs are equipped with a POR (Power On Reset) circuit, but in order to achieve operation at a low power supply, VCC is set to operate at approximately 1.3V. After the POR has been activated, writing is disabled, but if CS is set to HIGH, writing may be enabled because of noise or other factors. However, the POR circuit is effective only when the power supply is on, and will not operate when the power is off. Also, to prevent erroneous writing at low voltages, these ICs are equipped with a built-in circuit (VCC-lockout circuit) which resets the write command if V CC drops to approximately 2V or lower (typ.). CS + 5V VCC GND 0 DI 1 + 5V a b CS GND Fig.8 Timing during erroneous operation Bad example Good example (Bad example) Here, the CS pin is pulled up to VCC. In this case, CS is HIGH (active state). Please be aware that the EEPROM SK may perform erroneous operations or write erroneous data because of noise or other factors. Also, be aware that this may occur ever if the CS input is at High-2. (Good example) In this case, CS is LOW when the power supply is turned CS on or off. DI 0 1 b Fig.9 Timing during normal operation (3) Precautions when turning power on and off When turning the power supply on and off, make sure CS is set to LOW (see Figure 10). When CS is HIGH, the EEPROM enters the active state. To avoid this, make sure CS is set to LOW (disable mode) when turning on the power supply. (When CS is LOW, all input is cancelled.) When the power supply is turned off, the low power state can continue for a long time because of the capacity of the power supply line. Erroneous operations and erroneous writing can occur at such times for the same reasons as described above. To avoid this, make sure CS is set to LOW before turning off the power supply. 10 Fig.10 (4) Clock (SK) rise conditions If the clock pin (SK) signal of the BR93LC66 / BR93LC66A has a long rise time (tr) and if noise on the signal line exceeds a certain level, erroneous operation can occur due to erroneous counts in the clock. To prevent this, a Schmitt trigger is built into the SK input of the BR93LC66. The hysteresis amplitude of this circuit is set to approximately 0.2V, so if the noise exceeds the SK input, the noise amplitude should be set to 0.2VP-P or lower. Furthermore, rises and falls in the clock input should be accelerated as much as possible. (5) Power supply noise The BR93LC66 discharge high volumes of high voltage when a write is completed. The power supply may fluctuate at such times. Therefore, make sure a capacitor of 1000pF or greater is connected between VCC (Pin 8) and GND (Pin 5). Memory ICs BR93LC66 / BR93LC66F / BR93LC66RF / BR93LC66FV (6) Connecting DI and DO directly The BR93LC66 have an independent input pin (DI) and output pin (DO). These are treated as individual signals on the timing chart but can be controlled through one control line. Control can be initiated on a single control line by inserting a resistor R. µ - COM BR93LC66 I / O PORT DI R DO Fig.11 Common connections for the DI and DO control line 1) Data collision between the µ-COM output and the DO output Within the input and output timing of the BR93LC66 the drive from the µ-COM output to the DI input and a signal output from the DO output can be emitted at the same time. This happens only for the 1 clock cycle (a dummy bit “0” is output to the DO pin) which acquires the AO address data during a read cycle. When the address data AO = 1, the µ-COM output becomes a direct current source for the DO pin. The resistor R is the only resistance which limits this current. Therefore, a resistor with a value which satisfies the µ-COM and the BR93LC66 current capacity is required. When using a single control line, when a dummy bit “0” is output to the DO, the µ-COM I / O address data AO is also output. Therefore, the dummy bit cannot be detected. 2) Feedback to the DI input from the DO output Data is output from the DO pin and then feeds back into the DI input through the resistor R. This happens when: • DO data is output during a read operation • A READY / BUSY signal is output during WRITE or WRAL operation Such feedback does not cause problems in the basic operation of the BR93LC66. The µ-COM input level must be adequately maintained for the voltage drop at R which is caused by the total input leakage current for the µ-COM and the BR93LC66. In the state in which SK is input, when the READY / BUSY function is used, make sure that CS is dropped to LOW within four clock pulses of the output of the READY signal HIGH and the standby mode is restored. For input after the fifth clock pulse, the READY HIGH will be taken as the start bit and WDS or some other mode will be activated, depending on the DI state. 11 Memory ICs BR93LC66 / BR93LC66F / BR93LC66RF / BR93LC66FV •External dimension (Units: mm) BR93LC66 BR93LC66F / RF 9.3 ± 0.3 5.0 ± 0.2 5 0.11 0.3 ± 0.1 0.5 ± 0.1 2.54 5 1 4 0°~15° 1.27 0.15 ± 0.1 1.5 ± 0.1 7.62 8 4.4 ± 0.2 4 0.51Min. 3.2 ± 0.2 3.4 ± 0.3 1 6.2 ± 0.3 6.5 ± 0.3 8 0.4 ± 0.1 0.3Min. 0.15 SOP8 DIP8 BR93LC66FV 8 5 1 4 (0.52) 0.15 ± 0.1 4.4 ± 0.2 0.1 1.15 ± 0.1 6.4 ± 0.3 3.0 ± 0.2 0.65 0.22 ± 0.1 0.3Min. 0.1 SSOP-B8 12