MAXIM MAX3710

19-5910; Rev 0; 8/11
EVALUATION KIT AVAILABLE
MAX3710
125Mbps to 2.5Gbps Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
General Description
The MAX3710 limiting amplifier and burst mode laser
driver provides a highly integrated, low-cost, high-performance PMD solution for GPON/EPON ONU applications
in modules or directly on the ONU board.
The low-jitter laser diode driver provides transmit burst
mode average power control (APC) of laser bias current
as well as an integrated modulation current control loop
(extinction ratio control, or ERC). The ERC eliminates the
need for temperature lookup tables (LUTs) controlling the
modulation current.
The low-noise limiting amplifier maximizes optical sensitivity and has adjustable SD/LOS threshold plus programmable output levels. The differential CML output stage
features a slew-rate adjustment for 1.25Gbps EPON
operation. Integrated bias current monitor, burst mode Tx
power monitor, and a digital laser power monitor enable
a low-cost implementation of the next-generation GPON
and EPON modules with digital diagnostics.
A novel auto-calibration mode enables low-cost fiber
optic module production. An integrated 3-wire digital
interface controls the laser driver and limiting amplifier
functions, and enables communication with a low-cost
controller.
The MAX3710 is offered in a small, 4mm x 4mm, 24-pin
TQFN package with exposed pad, and operates over the
-40NC to +95NC temperature range.
Benefits and Features
SSimplifies Module Manufacturing
Enables Single-Temperature Module Testing
Production Laser Auto-Calibration Mode
SImproved ONU Performance
Integrated APC and ERC Loops
1.3mVP-P Receiver Sensitivity

Separate Laser Driver Supply (Rogue ONU
Shutdown)
SFlexibility
LVDS, LVPECL, and CML Compatible High Speed I/Os
Programmable I/O Polarity
3-Wire Digital Interface
SSafety and Reliability
Integrated Safety Features with FAULT Mask
Register
Supports SFP MSA and SFF-8472 Digital
Diagnostic
Selectable Analog Monitor of Laser Power or
BIAS Current at BMON Pin
Applications
BOSA On-Board
GPON/EPON ONU
Ordering Information appears at end of data sheet.
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
ABSOLUTE MAXIMUM RATINGS
VCCX, VCCTO, VCCD............................................... -0.3V to 4.0V
Voltage Range at DISABLE, SDA, SCL, CSEL,
FAULT, LOS, MDREF, LPD................... -0.3V to (VCC + 0.3V)
Voltage Range at RIN+, RIN-......... (VCC - 1.7V) to (VCC + 0.3V)
Voltage Range at ROUT+, ROUT-........... (VCC - 2V) to (VCC + 0.3V)
Voltage Range at TIN+, TIN-,
BEN+, BEN-........................................... -0.3V to (VCC + 0.3V)
Voltage Range at TOUT........................................0.3V to VCCTO
Voltage Range at IOUT..........(VCCTO - 1.8V) to (VCCTO + 1.2V)
Current Range into FAULT, LOS,
MDIN, SDA....................................................... -1mA to +5mA
Current Range into LPD....................................... -5mA to +5mA
Current out of ROUT+, ROUT-............................................40mA
Current into TOUT.............................................................180mA
Current into IOUT..............................................................120mA
Voltage Range at BMON..........................................-0.3V to VCC
Continuous Power Dissipation (TA = +70NC)
TQFN (derate 27.8mW/NC above +70NC)..................2222mW
Storage Temperature Range ........................... -55NC to +150NC
Die Attach Temperature ..................................................+400NC
Lead Temperature (soldering, 10s).................................+300NC
Soldering Temperature (reflow).......................................+260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = 2.97V to +3.63V, TA = -40°C to +95°C; CML receiver output is AC-coupled to differential 100Ω load; registers are set to default
values, unless implied by test conditions. Typical values are at VCC = +3.3V, TA = +25°C, data rate = 2.5Gbps, IBIAS = 20mA, and
IMOD = 40mA, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2.97
3.3
3.63
V
75
110
mA
2.55
2.75
V
OPERATING CONDITIONS
Power Supply Voltage
VCC
POWER SUPPLY
Power-Supply Current
ICC
Includes Rx CML output current,
excludes Tx IBIAS = 20mA, IMOD = 40mA
POWER-ON RESET
VCC for Enable High
VCCX connected to VCCD
VCCX connected to VCCD
VCC for Enable Low
2.3
2.45
V
75
100
125
I
1.3
2
mVP-P
Rx INPUT SPECIFICATION
Differential Input Resistance
RIN
Input Sensitivity
VINMIN
Input Overload
VINMAX
Differential Input Return Loss
SDD11
Common-Mode Input Return
Loss
SCC11
223 - 1 PRBS, 2.5Gbps, TX_EN = 0
(Note 2)
(Note 2)
1.2
VP-P
Device powered on, f P 2GHz
19
Device powered on, f P 5GHz
12
Device powered on, 1GHz P f P 2GHz
11
Device powered on, 2GHz P f P 5GHz
14
dB
dB
Rx OUTPUT SPECIFICATION
Differential Output Resistance
ROUTDIFF
Differential Output Return Loss
SDD22
Common-Mode Output Return
Loss
SCC22
75
100
Device powered on, f P 2GHz
19
Device powered on, 2GHz P f P 5GHz
15
Device powered on, f P 2GHz
14
Device powered on, 2GHz P f P 5GHz
10
125
I
dB
dB
2
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.97V to +3.63V, TA = -40°C to +95°C; CML receiver output is AC-coupled to differential 100Ω load; registers are set to default
values, unless implied by test conditions. Typical values are at VCC = +3.3V, TA = +25°C, data rate = 2.5Gbps, IBIAS = 20mA, and
IMOD = 40mA, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CML Differential Output
Voltage
CONDITIONS
MIN
TYP
MAX
4mVP-P P VIN P 1200mVP-P,
SET_CML[3:0] = 10d
600
800
1000
mVP-P
4mVP-P P VIN P 1200mVP-P,
SET_CML[3:0] = 0
CML Differential Output
Voltage When Disabled
410
Output AC-coupled, VINMAX at input,
SET_CML[3:0] = 10d (Note 2)
Data Output Transition Time
(20% to 80%) (Note 2)
UNITS
5
4mVP-P P VIN P 1200mVP-P,
SLEW_RATE = 1
85
115
4mVP-P P VIN P 1200mVP-P,
SLEW_RATE = 0
140
200
mVP-P
ps
LOS Output High Voltage
VOH
RLOS = 4.7kI - 10kI to VCC
VCC 0.1
LOS Output Low Voltage
VOL
RLOS = 4.7kI - 10kI to VCC
0
V
0.4
V
Rx TRANSFER CHARACTERISTICS
2.5Gbps, 4mVP-P P VIN P 1200mVP-P,
SET_CML[3:0] = 10d
7
15
1.25Gbps, 4mVP-P P VIN P 1200mVP-P,
SET_CML[3:0] = 10d
10
20
psP-P
125Mbps, 4mVP-P P VIN P 1200mVP-P,
SET_CML[3:0] = 10d, K28.5 pattern
21
Input = 4mVP-P at 2.5Gbps,
1111 0000 pattern, SET_CML[3:0] = 10d
(Notes 2, 4)
3.5
5
psRMS
Low-Frequency Cutoff
(Simulated Value)
I/O coupling capacitors = 1FF
10
kHz
Small-Signal Bandwidth
(Simulated Value)
SLEW_RATE = 1
2.0
GHz
Deterministic Jitter
(Notes 2, 3)
Random Jitter
DJ
RJ
LOS SPECIFICATIONS (Notes 2, 5)
LOS Hysteresis
10log(VDEASSERT/VASSERT)
1.25
LOS Assert/Deassert Time
(Note 6)
2.3
LOS_RANGE = 0
4.6
36
LOS_RANGE = 1
14
115
LOS Assert Sensitivity Range
LOS assert
LOS Assert/Deassert Level
(Low Range, LOS_RANGE = 0)
LOS deassert
2.2
dB
30
SET_LOS = 5
3
3.8
4.6
SET_LOS = 31
18
23
28
SET_LOS = 63
36
47
56
SET_LOS = 5
5
6.5
8
SET_LOS = 31
32
39
46
SET_LOS = 63
64
80
95
Fs
mVP-P
mVP-P
3
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.97V to +3.63V, TA = -40°C to +95°C; CML receiver output is AC-coupled to differential 100Ω load; registers are set to default
values, unless implied by test conditions. Typical values are at VCC = +3.3V, TA = +25°C, data rate = 2.5Gbps, IBIAS = 20mA, and
IMOD = 40mA, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
LOS assert
LOS Assert/Deassert Level
(High Range, LOS_RANGE = 1)
LOS deassert
MIN
TYP
MAX
SET_LOS = 5
9
11.5
14
SET_LOS = 31
55
68
80
SET_LOS = 63
115
138
160
SET_LOS = 5
15
19
23
SET_LOS = 31
97
117
136
SET_LOS = 63
197
238
278
UNITS
mVP-P
Tx INPUT SPECIFICATIONS
Differential Input Resistance
(TIN and BEN)
Internal Common-Mode Bias
Voltage (TIN and BEN)
For AC-coupled operation
Differential Input Voltage
(TIN and BEN)
DC-coupled, 100I, differential resistors,
Figure 1 and Figure 3
Common-Mode Input Voltage
Range (TIN and BEN)
DC-coupled, Figure 1 and Figure 3
DISABLE Input Current
DISABLE = VCC
DISABLE = GND
13
kI
1.3
V
0.2
1.6
VP-P
1.125
VCC VIN/2.5
V
10
33
60.5
FA
DISABLE Input High Voltage
VIH
1.8
VCC
V
DISABLE Input Low Voltage
VIL
0
0.8
V
DISABLE Input Hysteresis
VHYST
DISABLE Input Impedance
RPULL
80
Pullup resistor
60
100
mV
138
kI
Tx OUTPUT SPECIFICATIONS
FAULT Output High Voltage
VOH
RFAULT is 4.7kI - 10kI to VCC
FAULT Output Low Voltage
VOL
LPD Output High Voltage
VOH
RFAULT is 4.7kI - 10kI to VCC
ILPD = -1mA
LPD Output Low Voltage
VOL
ILPD = +1mA
VCC - 0.1
V
0
0.4
VCC - 0.5
V
V
0
0.4
V
LASER MODULATOR
Maximum Modulation-On
Current
85
mA
Minimum Modulation-On
Current
Modulation Current DAC
Stability
Modulation Current Rise/Fall
Time (Note 2)
5
mA
%
10mA P IMOD P 85mA (Notes 2, 7)
1
4
20% to 80%, 10mA P IMOD P 85mA,
RLOAD = 12I, TRF[1:0] = 11b
65
120
20% to 80%, 10mA P IMOD P 85mA,
RLOAD = 12I, TRF[1:0] = 00b
72
ps
4
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.97V to +3.63V, TA = -40°C to +95°C; CML receiver output is AC-coupled to differential 100Ω load; registers are set to default
values, unless implied by test conditions. Typical values are at VCC = +3.3V, TA = +25°C, data rate = 2.5Gbps, IBIAS = 20mA, and
IMOD = 40mA, unless otherwise noted.) (Note 1)
PARAMETER
Compliance Voltage at TOUT
SYMBOL
VTOUT
Deterministic Jitter
(Notes 2, 3)
DJ
Random Jitter
(Notes 2, 4)
RJ
CONDITIONS
Instantaneous voltage,
10mA P IMOD P 85mA
MIN
TYP
0.6
15
10mA P IMOD P 85mA, 2.5Gbps
10mA P IMOD P 85mA, 1.25Gbps
MAX
UNITS
2.4
V
40
15
10mA P IMOD P 85mA, 125Mbps,
K28.5 pattern
psP-P
20
10mA P IMOD P 20mA, 1111 0000 pattern
20mA P IMOD P 85mA, 1111 0000 pattern
1.2
1.65
1
1.45
psRMS
BIAS GENERATOR
Maximum Bias Current
Current into TOUT
Minimum Bias Current
Current into TOUT
Bias Current DAC Stability
2mA P IBIAS P 70mA, VTOUT = 2V
(Notes 2, 7)
Bias Current Monitor Current
Gain
IBIAS/
IBMON
Compliance Voltage Range at
BMON
VBMON
BMON Current Gain Stability
(as Bias Monitor)
70
External resistor to GND defines voltage
gain, 2mA P IBIAS P 6mA
54
External resistor to GND defines voltage
gain, 6mA P IBIAS P 70mA
64
mA
1
mA
1
4
%
64
72
A/A
72
0
2
2mA P IBIAS P 70mA (Notes 2, 7)
80
1.8
V
5
%
LASER CONTROL SPECIFICATIONS
APC Loop Stability (1.25Gbps,
223 - 1 PRBS Pattern) (Note 8)
IMDINAVG = 50FA, KMD x SE = 0.005
IMDINAVG = 2mA, KMD x SE = 0.05
0.1
APC Loop Stability (2.5Gbps,
223 - 1 PRBS Pattern) (Note 8)
IMDINAVG = 50FA, KMD x SE = 0.005
IMDINAVG = 2mA, KMD x SE = 0.05
0.1
ERC Loop Stability (1.25Gbps,
223 - 1 PRBS Pattern,
eR = 11dB) (Note 8)
IMDINAVG = 50FA, KMD x SE = 0.005
0.5
IMDINAVG = 2mA, KMD x SE = 0.05
0.5
ERC Loop Stability (2.5Gbps,
223 - 1 PRBS Pattern,
eR = 11dB) (Note 8)
IMDINAVG = 50FA, KMD x SE = 0.005
1.3
IMDINAVG = 2mA, KMD x SE = 0.05
1.1
MDIN Bias Voltage
MD Average Current Range
Programmable Extinction Ratio
Range
eR
10log(dB)
0.1
VMDIN
IMDINAVG
10log(dB)
0.1
10log(dB)
10log(dB)
1.2
Average current into MDIN
50
P1/P0 (DPC closed-loop operation)
10
V
2000
16
FA
24
5
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.97V to +3.63V, TA = -40°C to +95°C; CML receiver output is AC-coupled to differential 100Ω load; registers are set to default
values, unless implied by test conditions. Typical values are at VCC = +3.3V, TA = +25°C, data rate = 2.5Gbps, IBIAS = 20mA, and
IMOD = 40mA, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
From the rising edge of the final SCL
clock of the 3-wire cycle to 90% of
steady state at BMON
MD Current Monitor/BMON
Activation Time
TYP
MAX
100
UNITS
ns
SAFETY FEATURES
Fault Threshold Voltage at
TOUT
VTOUT
Fault always occurs for VTOUT < 0.35V,
fault never occurs for VTOUT R 0.55V
0.35
0.55
V
Fault Threshold Voltage at
MDIN
VMDIN
Fault always occurs for VMDIN < 0.3V,
fault never occurs for VMDIN R 0.5V
0.3
0.5
V
Fault Threshold Voltage at
IOUT
Fault always occurs for VIOUT < VCCTO
- 1.7V, fault never occurs for VIOUT R
VCCTO - 1.45V, VCCTO = 3.3V
VCCTO
- 1.7
VCCTO
- 1.45
V
Warning Threshold Voltage at
BEN (Differential Voltage)
Warning occurs if |(BEN+) - (BEN-)| <
20mV and never occurs if |(BEN+) (BEN-)| R 100mV
20
100
mV
Warning Threshold Voltage at
BEN (Common-Mode Voltage)
Warning occurs if both BEN+ and BENfall below 880mV
Fault Threshold Voltage at
VCCTO
Fault always occurs for VCCTO < 2V; fault
never occurs for VCCTO R 2.95V
Maximum Laser Current in
Disable State or Burst-Off State
Combined total current into TOUT during
fault, DISABLE = 1, TX_EN = 0, or
BEN = 0
880
2
mV
2.95
V
100
FA
Tx TIMING SPECIFICATIONS
DPC Loop Initialization Time
tAPCINIT
IBIAS = 40mA and IMOD = 60mA,
IBIAS_INT = 8mA, time from restart to
IBIAS and IMOD at 90% of steady state
Burst Enable Time
tBSTART
Time from 50% of BENQ input signal to
IBIAS and IMOD at 90% of steady state
(Note 2)
2
ns
Burst Disable Time
tBSTOP
Time from 50% of BENQ input signal to
IBIAS and IMOD at 10% of steady state
(Note 2)
2
ns
3
Fs
Minimum Burst-On Time to
Update BIAS and MOD
tBRSTON
MDON_DLY[1:0] = 00 (Note 2)
60
100
ns
Minimum Burst-Off Time to
Update BIAS and MOD
tBRSTOFF
(Note 2)
110
200
ns
Time from rising edge of DISABLE input
signal to IBIAS and IMOD at 10% of
steady state (Note 2)
30
100
ns
DISABLE Assert Time
tOFF
6
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.97V to +3.63V, TA = -40°C to +95°C; CML receiver output is AC-coupled to differential 100Ω load; registers are set to default
values, unless implied by test conditions. Typical values are at VCC = +3.3V, TA = +25°C, data rate = 2.5Gbps, IBIAS = 20mA, and
IMOD = 40mA, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
tON
Fault Assert Time
LPD Assert Time
DISABLE Negate Time
LPD Deassert Time
MIN
TYP
MAX
UNITS
Time from falling edge of DISABLE
input signal to IBIAS and IMOD at 90% of
steady state (Note 2)
200
300
ns
tFAULT
Time from fault condition to FAULT high,
CFAULT P 20pF, RFAULT is 4.7kI - 10kW
to VCC (Note 2)
2.5
10
Fs
tLPD-ASSERT
Time from positive BEN edge to 90% of
steady state at LPD output, CLPD P 10pF
100
ns
tLPDDEASSERT
Time from negative BEN edge to 90% of
steady state at LPD output, CLPD P 10pF
100
ns
Minimum required time DISABLE must
be held high to reset a fault
DISABLE to Reset
100
ns
Nx
12.5
FA
1000
mVP-P
40
mVP-P
LASER POWER DETECTOR (LPD) SPECIFICATIONS
KIMD[1:0] = 00: N = LPD_TH[2:0] + 1,
KIMD[1:0] = 01: N = 2 x (LPD_TH[2:0] + 1),
KIMD[1:0] = 1X: N = 4 x (LPD_TH[2:0] + 1)
LPD Threshold Values
Rx OUTPUT LEVEL DAC
Full-Scale Voltage
VFS
Resolution
SET_CML[3:0] = 15d
820
4 bits
LOS THRESHOLD DAC
Full-Scale Voltage
Resolution
Integral Nonlinearity
LOS_RANGE = 0
47
LOS_RANGE = 1
138
LOS_RANGE = 0
0.75
LOS_RANGE = 1
2.2
SET_LOS[5:0] = 5d to 63d
mVP-P
mVP-P
Q0.7
LSB
78
mA
75
FA
89
mA
167
FA
BIAS CURRENT DAC
Full-Scale Current
Resolution
IFS_BIAS
LSB_BIAS
IBIAS = (12 + BIASREG[9:0]) x LSB_BIAS
70
10-bit DAC
MODULATION CURRENT DAC
Full-Scale Current
Resolution
IFS_MOD
LSB_MOD
IMOD = (20 + MODREG[8:0]) x
LSB_MOD
85
9-bit DAC
3-WIRE DIGITAL INTERFACE
Input High Voltage
Input Low Voltage
Input Hysteresis
VIH
2.0
VCC
VIL
VHYST
0.8
80
V
V
mV
7
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.97V to +3.63V, TA = -40°C to +95°C; CML receiver output is AC-coupled to differential 100Ω load; registers are set to default
values, unless implied by test conditions. Typical values are at VCC = +3.3V, TA = +25°C, data rate = 2.5Gbps, IBIAS = 20mA, and
IMOD = 40mA, unless otherwise noted.) (Note 1)
PARAMETER
Input Leakage Current
SYMBOL
IIL, IIH
CONDITIONS
MIN
TYP
Voltage at pin 0V to VCC, internal pullup
or pulldown 75kI typical
Output High Voltage
VOH
External pullup of 4.7kI to VCC
Output Low Voltage
VOL
External pullup of 4.7kI to VCC
MAX
UNITS
85
FA
VCC - 0.1
V
0.4
V
1
MHz
3-WIRE DIGITAL INTERFACE TIMING (Figure 6)
SCL Clock Frequency
fSCL
SCL Pulse-Width High
tCH
0.5
Fs
SCL Pulse-Width Low
tCL
0.5
Fs
SDA Setup Time
tDS
100
ns
SDA Hold Time
tDH
100
ns
tD
5
ns
SCL Rise to SDA Propagation
Time
CSEL Pulse-Width Low
tCSW
500
ns
CSEL Leading Time Before the
First SCL Edge
tL
500
ns
CSEL Trailing Time After the
Last SCL Edge
tT
500
ns
SDA, SCL External Load
CB
Total bus capacitance on one line
20
pF
Note 1: Specifications at TA = -40NC and TA = +95NC are guaranteed by design and characterization, .
Note 2: Guaranteed by design and characterization, TA = -40NC to +95NC.
Note 3: The data input transition time is controlled by 4th-order Bessel filter with f-3dB = 0.75 x 1.25GHz and f-3dB = 0.75 x
2.5GHz, respectively. The deterministic jitter caused by this filter is not included in the DJ. A 223 - 1 PRBS equivalent pattern was used.
Note 4: RJ was tested without input filter.
Note 5: For all Rx LOS specifications LOS_LOWBW = 1 for 1.25Gbps operation and LOS_LOWBW = 0 for 2.5Gbps operation.
Note 6: Measurement includes an input AC-coupling capacitor of 0.1FF. The signal at the RIN input is switched between two
amplitudes: Signal_ON and Signal_OFF.
1) Receiver operates at sensitivity level plus 1dB power penalty
a) Signal_OFF = 0
Signal_ON = 10log(min_assert_level) + 8dB
b) Signal_ON = 10log(max_deassert_level) + 1dB
Signal_OFF = 0
2) Receiver operates at overload
Signal_OFF = 0
Signal_ON = 1.2VP-P
max_deassert_level and min_assert_level are measured for one SET_LOS setting
Note 7: Stability is defined [IMEASURED) - (IREFERENCE)]/(IREFERENCE) over the listed current range temperature and supply variation. Reference current measured at VCC = 3.3V and TA = +25NC. Measured current is measured at VCC = 3.3V ±5% and
TA = -40NC to +95NC.
Note 8: KMD is the laser diode to monitor diode gain in A/W. SE is the laser’s slope efficiency.
8
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
INPUT COMMON MODE
COMPLIANCE (V)
VCC - 0.05V
VCC - 0.2V
DC-COUPLED CML
VCC - 0.32V
TIN AND BEN
OPERATIONAL RANGE
VCC - 1.28V
LVPECL
VCC - 1.49V
VCC/2
50Ω TO VCC - 2V
CMOS SINGLE-ENDED INPUT RANGE
LVPECL
1.275V
1.149V
1.125V
130Ω TO VCC AND
82Ω TO GND
LVDS
0.2V
0.4V
0.6V
0.8V
1.0V
1.2V
1.4V
1.6V
DIFFERENTIAL INPUT
SWING (VP-P)
Figure 1. BEN/TIN Input Voltage Diagram
9
MAX3710
125Mbps to 2.5Gbps Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
Typical Operating Characteristics
(Typical values are at VCC = +3.3V, TA = +25°C, data pattern = 223 - 1 PRBS, unless otherwise noted.)
90
MAX3710 toc01
0.7
0.6
250
70
LOS THRESHOLD (mVP-P)
0.8
2.5Gbps
LOS_LOWBW = 0
80
LOS THRESHOLD (mVP-P)
0.9
60
50
DEASSERT
40
30
20
0.5
0.4
DEASSERT
150
100
8
10
12
14
16
0
0
10
SET_CML[3:0]
20
30
40
50
60
70
0
10
20
SET_LOS[5:0]
BIT-ERROR RATE vs. DIFFERENTIAL INPUT
AMPLITUDE (1.25Gbps)
1E-05
40
50
60
70
BIT-ERROR RATE vs. DIFFERENTIAL INPUT
AMPLITUDE (2.5Gbps)
1E-04
MAX3710 toc04
1E-04
30
SET_LOS[5:0]
MAX3710 toc05
6
1E-05
1E-06
1E-06
BER
1E-07
TX_EN = 0
1E-08
1E-09
TX_EN = 0
1E-08
1E-09
TX_EN = 1
Tx IN BURST MODE
1E-10
1E-07
TX_EN = 1
Tx IN BURST MODE
1E-10
1E-11
1E-11
0.6
0.5
0.8
0.9
0.9
1.0
1.1
1.2
1.3
1.4
DIFFERENTIAL INPUT AMPLITUDE (mVP-P)
IMOD CURRENT vs. SET_IMOD[7:0]
(OPEN LOOP OPERATION)
IBIAS CURRENT vs. SET_IBIAS[7:0]
(OPEN LOOP OPERATION)
THIS IS THE PRECONDITION VALUE
FOR MOD CURRENT IF IMUPDT = 1.
90
0.8
DIFFERENTIAL INPUT AMPLITUDE (mVP-P)
90
MAX3710 toc06
100
0.7
80
THIS IS THE PRECONDITION VALUE
FOR BIAS CURRENT IF IBUPDT = 1.
80
70
70
1.5
MAX3710 toc07
4
BER
60
60
IBIAS (mA)
2
ASSERT
50
0
0
2.5Gbps
LOS_LOWBW = 0
200
ASSERT
10
IMOD (mAP-P)
DIFFERENTIAL OUTPUT (VP-P)
1.0
Rx INPUT-BASED LOS THRESHOLD vs. SET_LOS
(LOS_EN = 1 AND LOS_RANGE = 1)
MAX3710 toc03
Rx INPUT-BASED LOS THRESHOLD vs. SET_LOS
(LOS_EN = 1 AND LOS_RANGE = 0)
MAX3710 toc02
DIFFERENTIAL Rx OUTPUT SWING
vs. SET_CML
50
40
50
40
30
30
20
20
10
10
0
0
0
50
100
150
200
SET_IMOD[7:0]
250
300
0
50
100
150
200
250
300
SET_IBIAS[7:0]
10
MAX3710
125Mbps to 2.5Gbps Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
Typical Operating Characteristics (continued)
(Typical values are at VCC = +3.3V, TA = +25°C, data pattern = 223 - 1 PRBS, unless otherwise noted.)
LASER STARTUP WITHOUT
PRECONDITIONING
MAX3710 toc08
VCCX
DPC CLOSED LOOP
IMUPDT_EN = 0, IBUPDT_EN = 0
BIASINC[3:0] = 5
MODINC[3:0] = 5
LASER STARTUP WITH PRECONDITIONING
(SET_IBIAS[7:0] AND SET_IMOD[7:0]
LOADED WITH VALUES CLOSE TO
BIASREG[9:2] AND MODREG[8:1] FINAL VALUES)
MAX3710 toc09
VCCX
DPC CLOSED LOOP
IMUPDT_EN = 1, IBUPDT_EN = 1
BIASINC[3:0] = 1
MODINC[3:0] = 1
BEN
BEN
VCCTO
VCCTO
OPTICAL OUTPUT
OPTICAL OUTPUT
8µs/div
8µs/div
2.488Gbps OPTICAL EYE
MAX3710 toc10
DPC CLOSED LOOP
11.9dB eR
LASER STARTUP WITHOUT PRECONDITIONING (200ns BURSTS),
STARTING FROM MINIMUM IBIAS AND IMOD
MAX3710 toc11
DPC CLOSED LOOP, IMUPDT_EN = 0, IBUPDT_EN = 0
BIASINC[3:0] = 10d
MODINC[3:0] = 10d
OPTICAL OUTPUT
BEN
58ps/div
2µs/div
11
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
MDREF
VCCTO
IOUT
TOUT
LPD
TOP VIEW
MDIN
Pin Configuration
18
17
16
15
14
13
BMON 19
12
TIN-
VCCX 20
11
TIN+
10
BEN-
9
BEN+
8
SDA
7
VCCD
RIN- 21
MAX3710
RIN+ 22
VCCX 23
EP
+
1
2
3
4
5
6
FAULT
DISABLE
CSEL
ROUT+
ROUT-
SCL
LOS 24
TQFN
(4mm x 4mm)
Pin Description
PIN
1
NAME
OUTPUT FUNCTION
FAULT
Transmitter Fault, Open-Drain. Logic-high
indicates a fault condition has been detected
(FAULT_POL = 1). It remains high even after the
fault condition has been removed. A logic-low
occurs when the fault condition has been removed
and the fault latch has been cleared by toggling
the DISABLE signal, or by setting MODECTRL =
68h. FAULT should be pulled up to 3.3V supply
through a 4.7kI to 10kI resistor. Note that pulling
up the pin to a supply voltage above VCCX can
turn on the ESD protection diode.
EQUIVALENT CIRCUIT
ESD
PROTECTION
FAULT
VCCX
2
DISABLE
Transmitter Disable Input, TTL/CMOS. Set to
logic-low for normal operation (DIS_POL = 1).
Logic-high or open disables both the modulation
current and the bias current. Internally pulled up
by a 100kI resistor to VCCX.
VCCX
VCCX
VCCX
100kΩ
DISABLE
ESD
PROTECTION
12
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
Pin Description (continued)
PIN
NAME
OUTPUT FUNCTION
EQUIVALENT CIRCUIT
VCCX
3
CSEL
Chip-Select Input, CMOS. Setting CSEL to
logic-high starts a cycle. Setting CSEL to logiclow ends the cycle and resets the control state
machine. Internally pulled down by a 75kI resistor to ground.
ESD
PROTECTION
VCCD
CSEL
75kΩ
VCCX
ESD
50Ω PROTECTION
50Ω
4, 5
ROUT+,
ROUT-
ROUT+
ROUT-
Differential Receiver Data Output, CML. This output has 50I terminations to VCC. Polarity is set
by the RX_POL bit.
SET_CML
VCCD
6
SCL
Serial-Clock Input, CMOS. Internally pulled down
by a 75kI resistor to ground.
VCCD
ESD
PROTECTION
SCL
75kΩ
7
VCCD
Power Supply. Provides supply voltage to the
digital block.
—
VCCD
8
SDA
Serial-Data Bidirectional Input, CMOS. Opendrain output. This pin has a 75kI internal pullup,
but it requires an external 4.7kI to 10kI pullup
to meet 3-wire timing specifications.
VCCD
VCCD
75kΩ
SDA
ESD
PROTECTION
13
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
Pin Description (continued)
PIN
NAME
OUTPUT FUNCTION
EQUIVALENT CIRCUIT
VCCX
1.3V
6.5kΩ
6.5kΩ
BEN+
1kΩ
9, 10
BEN+/
BEN-
Burst-Enable Input. This differential 13kI input is
compatible with LVDS, PECL, and CML input levels. The polarity is set by the BEN_POL bit.
1kΩ
BENESD
PROTECTION
1.3V
VCCX
6.3kΩ
6.3kΩ
TIN+
11,
12
TIN+/TIN-
210Ω
Differential Transmitter Data Input. This differential 13kI input is compatible with LVDS, PECL,
and CML input levels. The polarity is set by the
TX_POL bit.
210Ω
TINESD
PROTECTION
VCCX
13
LPD
Laser Power Detector Output. The polarity of the
LPD signal is controlled by the LPD_POL bit. The
output impedance is approximately 150I.
ESD
PROTECTION
VCCX
LPD
14
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
Pin Description (continued)
PIN
14
NAME
OUTPUT FUNCTION
TOUT
Noninverting Laser Diode Modulation and Bias
Current Output. Connect to the cathode of the
laser diode. A differential 1 at TIN± results in current flow at the laser.
15
IOUT
16
VCCTO
EQUIVALENT CIRCUIT
VCCTO
ESD
PROTECTION
IOUT
TOUT
Inverting Laser Diode Modulation and Bias
Current Output. Connect to the anode of the
laser diode.
MODREG
BIASREG
Power-Supply Connection. Provides supply voltage to the transmitter output.
—
VCCX
17
18
19
20,
23
MDREF
Monitor Diode Reference. Connect this to a filtered VCCTO.
MDIN
Monitor Diode Input. Connect this pin to the
anode of the monitor diode. MDIN can be left
open for open-loop operation. Keep capacitance
minimized at this pin.
BMON
Bias Current/Laser Power Monitor Output.
Current out of this pin develops a ground-referenced voltage across external resistor(s) that is
proportional to the laser bias current or MDIN pin
current. The current sourced by this pin is typically 1/72 the laser bias current.
VCCX
Transceiver Power Supply. Provides supply voltage to the receiver and transmitter cores.
MDREF
VCCX
40Ω
MDIN
VCCX
BMON
ESD
PROTECTION
—
15
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
Pin Description (continued)
PIN
NAME
OUTPUT FUNCTION
EQUIVALENT CIRCUIT
VCCX - 1.2V
VCCX
50Ω
50Ω
RIN+
21,
22
RIN-,
RIN+
Differential Receiver Data Input. Contains 100I
differential termination on-chip. Connect these
inputs to the TIA outputs using 1FF coupling
capacitors.
RINESD
PROTECTION
24
—
LOS
EP
Receiver Loss-of-Signal (LOS) Output, Open
Drain. This output goes to a logic-high when
the level of the input signal drops below the
SET_LOS register threshold. Polarity is set by
LOS_POL. All LOS circuitry can be disabled by
setting LOS_EN = 0. The LOS output is pulled up
to host VCC with a 4.7kI to 10kI resistor.
Exposed Pad. Ground. This is the only electrical connection to ground on the MAX3710
and must be soldered to circuit board ground
for proper thermal and electrical performance
(see the Exposed-Pad Package and Thermal
Considerations section).
ESD
PROTECTION
VCCX
LOS
—
16
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
125Mbps TO 2.5Gbps LIMITING AMPLIFIER
VCCX
MAX3710
OFFSET
CORRECTION
50Ω
VCCX - 1.2V
50Ω
AZ_EN
50Ω
ROUT+
SLEW_RATE
RX_POL
50Ω
ROUT-
RIN+
1
RIN-
0
SLEW-RATE
CONTROL
RO_EN
SQ_EN
LOSS OF SIGNAL
OUTPUT CONTROL
LOGIC
LOS_RANGE
LOS_POL
LOS_EN
LOS
VCCD
6b DAC SET_LOS
4b DAC SET_CML
75kΩ
SDA
8b SET_2XAPC
3-WIRE
INTERFACE
SCL
DIGITAL CONTROL CIRCUITRY
8b SET_IMOD
CSEL
75kΩ
8b SET_IBIAS
75kΩ
9b DAC MODREG
APC/ERC LOOP LASER POWER
STARTUP MANAGEMENT
VCCX
10b DAC BIASREG
125Mbps TO 2.5Gbps BURST MODE LASER DRIVER
DIS_POL
POWER-ON RESET
100kΩ
1
DISABLE
0
EYE SAFETY
AND
OUTPUT CONTROL
TX_EN
CASCODE
TOUT
1
FAULT
IOUT
0
1.3V
FAULT_POL
6.5kΩ
TX_POL
6.5kΩ
1
TIN+
TIN-
BIAS
MONITOR
0
1.3V
BEN_POL
6.5kΩ
6.5kΩ
BEN+
1
BEN-
0
BMON
Tx POWER
MONITOR
BURST
CONTROL
LASER
POWER
DETECTOR
MDIN
MDREF
KRMD
KIMD
LPD
Figure 2. Functional Diagram
17
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
Detailed Description
cutoff of the offset cancellation loop is 10kHz when
1FF AC-coupling capacitors are used.
The MAX3710 combines a high-gain limiting amplifier with a burst-mode laser driver. The limiting amplifier
includes offset cancellation and programmable signaldetect threshold. The laser driver includes average
power and extinction ratio control, average or peak
laser power measurement capability, overcurrent limiting, laser power detector, bias current/MD current monitor, and fault detection. A 3-wire serial control interface
enables an external controller to set all parameters
necessary for operation of the limiting amplifier and laser
diode driver. The interface enables real-time laser bias
and/or modulation current control and provides operation
and status readouts.
Loss-of-Signal Circuitry (LOS)
This block detects amplitude of the incoming signal and
compares it against a preset threshold, which is controlled by SET_LOS[5:0]. The programming range of the
LOS assert level is 3.8mVP-P to 138mVP-P.
The features and performance are specifically designed
to be compatible with low-cost microcontrollers and
provide complete EPON and GPON PMD functionality,
including laser fault detection, diagnostics, and average
power control with extinction ratio control. The MAX3710
includes all the logic required for laser protection, control
loop operation, and monitor diode current measurement.
1.25Mbps to 2.5Gbps Limiting Amplifier
Block Description
Continuous Mode Limiter
The limiting amplifier consists of a multistage amplifier,
offset-correction circuit, output buffer, and loss-of-signal/
signal-detect circuitry. Its low noise (1.3mVP-P typical
sensitivity) and high gain can provide 0.3dB to 0.5dB of
additional sensitivity in typical 2.5Gbps GPON applications. Programmable configuration options (LOS threshold, LOS polarity, CML output with adjustable level, slew
rate, and output polarity) enhance layout flexibility and
triplexer/ROSA compatibility.
High-Speed Input Signal Path
The inputs, RIN±, have an internal 100I differential
termination and should be AC-coupled to the transimpedance amplifier.
Offset Cancellation
The limiting amplifier has approximately 68dB of
gain, which makes it very susceptible to both DC offsets and pulse-width distortion in the signal from the
transimpedance amplifier. A low-frequency feedback
loop provides offset cancellation to compensate for
these effects; the nominal small-signal low-frequency
Changing the LOS threshold during operation (i.e., without executing a reset) does not cause a glitch or incorrect LOS output. The detector has 2dB of hysteresis to
control chatter at the LOS output. The LOS output polarity
is controlled by the LOS_POL bit. The entire LOS circuit
block can be disabled by setting LOS_EN = 0.
Output Drivers
The CML data outputs, ROUT±, are terminated with 50I
to VCCX. The differential output level can be programmed
through the SET_CML[3:0] register between 410mVP-P
and 1000mVP-P, and the output polarity can be inverted.
Serial commands can also be used to manually disable
the output (to its common-mode voltage, i.e., near zero
differential voltage DC), or cause the limiting amp to
automatically disable the output under an LOS condition
(squelch through the SQ_EN bit). The output slew rate
can be optimized for either 2.5Gbps or low data-rate
operation by setting the SLEW_RATE bit.
1.25Mbps to 2.5Gbps Laser Driver
Block Description
The burst mode laser driver consists of TINQ/BENQ differential high-speed input buffers, TINQ/BENQ polarity
switch buffers, DISABLE TTL/CMOS input buffer, combined laser modulator and bias generator, monitor diode
current input buffer with calibration features, digital laser
power detector (LPD) with CMOS output buffer, analog
bias current monitor, analog transmit power monitor,
APC and ERC loop circuitry, eye-safety monitoring, and
FAULT output buffer.
Differential High-Speed Input Buffers
The high-speed laser driver data inputs, BENQ and
TINQ, are compatible with LVDS, LVPECL, and CML
outputs. BEN can be driven single-ended (Figure 3). For
burst mode operation TINQ should be DC-coupled with
external differential termination of 100I placed close to
the input pins. The BENQ and TINQ inputs can also be
DC-coupled to LVDS outputs using a 100I differential
termination. The polarity of TINQ and BENQ can be
inverted by the TX_POL and BEN_POL bits, respectively.
18
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
VCC
130Ω
VCC
130Ω
LVPECL
VCM = VCC x (82/212)
TIN/BEN
82Ω
100Ω
LVDS
VCM IS SET BY THE DRIVER.
82Ω
VCC
5.1kΩ
3kΩ
CML
100Ω
TIN/BEN
TIN/BEN
VCC
5.1kΩ
LVTTL
BEN
VCM = VCC - (VIN/2.5)
VCM IS SET BY HOST VCC AND THE DRIVER OUTPUT SWING.
8.2kΩ
Figure 3. Interfacing to the MAX3710 TIN± and BEN± Inputs
Laser Modulator and Bias Generator
The laser modulator provides DC coupled current into
the cathode of the laser diode at the TOUT pin. The
modulation current amplitude is set by MODREG[8:0].
The modulation current DAC guarantees modulation
amplitudes up to 85mA.
The laser bias current output stage is similar to the
modulation current output stage because the burst
mode operation requires fast switching on/off times.
The amplitude of the laser bias current is controlled by
BIASREG[9:0]. The laser bias current DAC guarantees
values up to 70mA.
During burst-on the modulation and bias currents are
summed at the TOUT pin. During burst-off the bias and
modulation currents are switched to the IOUT pin. Note
that TOUT and IOUT are not differential in the general
sense; TOUT must be connected to the laser diode cathode and the cascoded IOUT pin must be connected to
the laser diode anode.
Monitor Diode Current Input Buffer
The input stage covers a large input signal range by
having adjustable gain settings. The KIMD[1:0] bits set
the current gain. This is followed by an adjustable transimpedance amplifier (TIA). The TIA gain settings are
programmed by the KRMD[2:0] bits. The input has high
bandwidth, allowing the MAX3710 to monitor not only
average laser power, but also extinction ratio. In addition,
laser power detection (LPD) for rogue ONUs is made
possible by the MDIN input.
MDIN current is mirrored at the BMON output and selected by setting MDMON_EN = 1 and MON_SEL = 1. In this
mode, the current sourced by BMON is scaled by KIMD,
where the value KIMD is set by the KIMD[1:0] bits. The
high bandwidth of the MDIN–BMON path enables tuning of the laser-to-monitor diode external components
to minimize crosstalk and to optimize filtering on the
MDIN signal.
19
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
and MD1REGH[7:0] and MD1REGL[7:0]. The values are MD0[15:8] = MD0REGH[7:0], MD0[7:0] =
MD0REGL[7:0], MD1[15:8] = MD1REGH[7:0],
MD1[7:0] = MD1REGL[7:0]. The number of averages
used to generate MD1[15:0] and MD0[15:0] is determined by MDAVG_CNT.
Digital Laser Power Detector
This detector compares the monitor diode current value
with a preset threshold and generates a CMOS logic
level output at the LPD pin. The threshold level scales
with gain settings at MDIN through KIMD[1:0].
There are two basic modes for reporting the results of
LPD, which performs light detection during the off_state:
Off_state is defined as a disable of the device by
DISABLE, TX_EN, MOD_EN, BIAS_EN, BEN, or a fault.
To monitor average transmitter power, use the following equation:
MD0[15 : 0]
+ MD1[15 : 0]
8
=
PAVG 0.00292 ×
512 × KIMD × KRMD × K MD
where KMD is the laser diode to monitor diode gain in
A/W.
Mode 1, LPD_MODE = 1:
LPD reports any light burst (when BEN = 1, the LPD
output is high).
Mode 2, LPD_MODE = 0:
LPD reports light bursts during a laser off state only
(when BEN = 1, the LPD output is low).
Polarity of the LPD output is selectable by setting the
LPD_POL bit. The mode of operation is controlled by
the LPD_MODE bit.
Use the LPD_TH[2:0] bits to set the LPD threshold in
steps of 12.5FA/KIMD, where the value KIMD is set by the
KIMD[1:0] bits. If the monitor diode exhibits a “slow-tail”
behavior where the monitor diode current slowly decays
after light disappears, the LPD threshold may need to
be adjusted high enough so the LPD output does not
produce an unintentional pulse directly after BEN transitions low.
Average Power and Extinction Ratio Control Circuitry
The MAX3710 includes full closed-loop control of laser
average power and extinction ratio. Figure 4 shows the
dual power control, or DPC, loop. Operation is as follows:
The monitor diode (MD) is connected to the MDIN pin,
and the MD current is amplified by a gain set by the
KIMD[1:0] and KRMD[2:0] bits.
The output of the MDIN input buffer is sent through
a programmable filter, controlled by the CPRG[4:0],
MDLBW[1:0], and MDRNG bits.
The filter output is fed to a 10MS/s analog-to-digital converter (ADC), where the peak values of
both the high current and the low current (proportional to the high power and low power of the
laser) are determined and converted to 16-bit digital words, MD0REGH[7:0] and MD0REGL[7:0],
For example, if KMD = 0.1, KIMD[1:0] = 00
(gain = 1), KRMD[2:0] = 000 (gain = 2800I),
MD0[15:0] = 35750d, and MD1[15:0] = 44680d, the
calculated PAVG = 1mW.
From the ADC to the TOUT/IOUT outputs, operation
is dictated by the state of the BENQ pins. The ADC
only samples during the burst-on time and is frozen
during burst-off. Therefore, MD1 and MD0 values are
held static during burst-off. The TX_EN bit must also
be high for the ADC to sample.
The delay from the rising edge of BEN to the first
sample is selected by the MDON_DLY[1:0] bits in
100ns steps. For MDON_DLY[1:0] = 00, the minimum
burst-on time for DPC updating is approximately 60ns
(typ), and it can be adjusted up to 360ns by setting
MDON_DLY[1:0] = 11.
Returning to the main forward path of the DPC,
MD1[15:0] and MD0[15:0] are used to compute the
average power and extinction ratio at the MDIN input
in the “COMPUTATION” block (Figure 4). These values
are compared with the target values of average power
(SET_2XAPC[7:0]) and extinction ratio (ERSET[3:0] bits).
If the error magnitude is greater than the value set
by THRSHLD, then the output registers BIASREG[9:0]
and MODREG[8:0] are updated with the error value.
The update value is limited by the BIASINC[3:0] and
MODINC[3:0] registers.
The IBIASMAX[7:0] and IMODMAX[7:0] values are used
to limit BIASREG[9:2] and MODREG[8:1]. Note only the
upper 8 bits of the output current registers are compared.
20
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
The EOB_EN bit conditions updating of the output
registers.
Full DPC Mode. DPC_EN = 1, APC_EN = X:
BIASREG[9:0] and MODREG[8:0] are controlled
based on the SET_2XAPC[7:0] register and ERSET[3:0]
targets.
If EOB_EN = 1, the output registers are only updated
once immediately following the falling edge of BEN.
However, the DPC must acquire the entire set of
averages, N, set by MDAVG_CNT, before changing
BIASREG[9:0] and MODREG[8:0]. The averaging
process can stretch over multiple bursts and freezes
between bursts. Once the required number of averages has been satisfied, the ADC outputs freeze until
BEN falls and BIASREG[9:0] and MODREG[8:0] can
be updated.
APC Only Mode. DPC_EN = 0, APC_EN = 1:
The BIASREG[9:0] register is controlled based
on the SET_2XAPC[7:0] target and MODREG[8:0]
is controlled directly through SET_IMOD[7:0].
MODINC[4:0] is used to adjust the lower bits of
MODREG[8:0] using two’s complement to increase
or decrease its value.
Open Loop Mode. DPC_EN = 0, APC_EN = 0:
The BIASREG[9:2] register is controlled directly
by SET_IBIAS[7:0] and MODREG[8:1] is controlled
directly by SET_IMOD[7:0]. Registers BIASINC[4:0]
and MODINC[4:0] are used to adjust the lower bits
of BIASREG[9:0] and MODREG[8:0] using two’s
complement.
If EOB_EN = 0, the output registers are updated continuously while BEN = 1.
The “CONTROL” block (Figure 4) controls the updating
and startup behavior of the entire DPC.
The bits APC_EN and DPC_EN control the operating
mode of the DPC:
MDMON_EN,
MON_SEL
MD0REGH[7:0],
MD0REGL[7:0]
(IBIAS/72)
BMON
MDIN
SET_2XAPC[7:0]
BIAS_EN
IMUPDT_EN
IBUPDT_EN
DAC
IBIAS
MODREG[8:0]
DAC
IMOD
ERSET[2:0]
SET_IMOD[7:0]
CONTROL
DPC_EN
BEN_POL
LOGIC
BIASREG[9:0]
COMPUTATION
MD1REGH[7:0],
MD1REGL[7:0]
MOD_EN
TX_EN
DIS_POL
IBIASMAX[7:0]
MDAVG_CNT
CPRG[4:0],
MDLBW[1:0],
MDRNG
BEN+
SET_IBIAS[7:0]
THRSHLD
BIASINC[4:0]
ADC
KIMD[1:0],
KRMD[2:0]
DISABLE
MODINC[4:0]
MDON_DLY
IMODMAX[7:0]
RESTART
DPC_RUN
DPC_STOP
APC_EN
EOB_EN
SYNC
Figure 4. DPC Loop Diagram
21
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
The DPC acquisition mode is controlled by several
bits: RESTART, IBUPDT_EN, IMUPDT_EN, DPC_RUN,
and DPC_STOP.
soft reset requires approximately 50Fs to complete. The
recommended POR procedure is as follows:
Anytime the DPC FSM is reset (through an
unmasked fault or if RESTART is issued),
BIASREG[9:2] and MODREG[8:1] are optionally
reinitialized to SET_IBIAS[7:0] and SET_IMOD[7:0],
respectively. Reinitialization is accomplished by
setting bit IBUPDT_EN (for BIASREG[9:0]) or
IMUPDT_EN (for MODREG[8:0]) to 1. This allows
accurate output current in the first burst.
• Controller initiates 3-wire communication after POR
with MAX3710 by repeatedly reading out the LVFLAG
(VCCTO flag) bit until the 1-to-0 transition occurs
(VCCTO is needed for the Tx output and DPC only).
The bit RESTART resets the state machine, sets
DPC_RUN = 1, and reinitializes BIASREG[9:2]
and MODREG[8:1], subject to IBUPDT_EN and
IMUPDT_EN, respectively. The state machine then
moves to a coarse acquisition mode, a binarysearch mode, and finally a steady-state mode
where averaging begins. In steady-state mode,
the SSMODE status bit is set high and RESTART
is reset.
The BMON pin can be selected to either provide a monitor of the laser bias current or the MDIN pin current. It
sources 1/72 of the laser bias current when the MON_SEL
bit is 0 (default). A resistor to ground sets the full-scale
voltage range and can be monitored by an external
ADC. When BMON is set to replicate the MDIN current
(MON_SEL = 1 and MDMON_EN = 1), the pin sources a
KIMD[1:0]-scaled MD current.
In coarse acquisition mode, the BIASREG[9:0] step
size is 2 x BIASINC[3:0] and the MODREG[8:0]
step size is 2 x MODINC[3:0]. An update is made
every 200ns.
The eye safety circuitry consists of fault detection, warning flags, faults, and fault masking. Certain pins of the
device are monitored for conditions that indicate nonstandard operation (Figure 5).
The bit DPC_STOP prevents the DPC from updating the output registers, while DPC_RUN allows
the DPC to operate. If a 1 is written to DPC_STOP,
DPC_RUN is reset to 0. If a 1 is written to DPC_RUN,
DPC_STOP is reset to 0. Writing a 0 to either bit has
no affect. If the state machine is not in steady state,
setting DPC_STOP = 1 forces it into steady state.
Note that the loop no longer updates BIASREG[9:0]
and MODREG[8:0] since DPC_STOP is high.
Less critical conditions are flagged by a warning flag.
These conditions trigger a bit to go high and remain high
until the condition is removed and the bit is read. These
do not cause the device to disable itself. The Tx warning
flags are located in the TXSTAT1[7:0] register and are
LPDFLAG and BENLOS.
Power-On Reset (POR)
A power-on-reset circuit provides proper startup sequencing and ensures that the laser is off while the supply voltage is ramping or below a specified threshold (~2.55V).
The serial interface can also be used to command a manual reset at any time by setting SOFTRESET = 1, which is
identical to a power-on reset. When using SOFTRESET,
the MAX3710 transmitter must be disabled, either by the
DISABLE pin or by setting TX_EN = 0. Either power-on or
• POR sets all registers to their defaults.
• Controller writes/initializes all registers (see the DPC
startup procedure).
BMON Functions
Eye Safety Circuitry
Critical conditions create a fault. A fault disables the
transmitter’s bias and modulation current DACs and
the Tx circuitry remains in a fault state until cleared
by toggling DISABLE, cycling power, or writing 68h to
MODECTRL[7:0]. Faults are maskable, meaning that by
setting the mask bits high, specific faults do not cause
the device to become disabled. Faults are indicated
by the TXINLOS, FMD, FIOUT, LVFLAG, and FTOUT
bits. Note that a fault at MDIN (indicated by FMD) can
be masked, but still causes the DPC to stop operation,
regardless of the mask. In this condition, the DPC must
be started to resume operation (set DPC_RUN = 1 or
RESTART = 1).
22
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
REGISTER (TXSTAT1)
TOUT
IOUT
REGISTER (TXSTAT1)
ADDRESS = H0x1E
1.3V
0.35V
IBIAS
IMOD
<0> TX_FAULT
<1> FTOUT
TXIN+
VCCTO - 1.7V
TXIN-
<2> FIOUT
AC SIGNAL
DETECT
0.3V
<3> FMD
<4> TXINLOS
MDIN
1.3V
<5> BENLOS
<6> LPDFLAG
BEN+
LPD THRESHOLD
BEN-
POR THRESHOLD
<7> LVFLAG
SIGNAL
DETECT
RESET
POR
FAULT CLEAR MODE
VCCTO
MODECTRL = 68h
100kΩ
DISABLE
Figure 5. Eye Safety Circuitry
23
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
Table 1. Circuit Response to Single-Point Faults
PIN
NAME
SHORT TO VCC
No effect, but open-drain nMOS
output life can be stressed (Note 1)
SHORT TO GND
OPEN
1
FAULT
2
DISABLE
3
4
5
6
CSEL
ROUT+
ROUTSCL
7
VCCD
No effect
POR on
POR on
8
SDA
No effect, but open-drain nMOS
output life can be stressed (Note 1)
No effect (Note 1)
No effect (Note 1)
9
10
BEN+
BEN-
No effect
No effect
No effect
No effect
No effect
No effect
11
TIN+
TXINLOS flag asserted
TXINLOS flag is asserted
No effect depending on TINamplitude
12
TIN-
TXINLOS flag asserted
TXINLOS flag is asserted
No effect depending on TIN+
amplitude
13
LPD
No effect, but output device life can
be stressed
No effect, but output device life
can be stressed
No effect (Note 1)
14
TOUT
Laser diode is off
FAULT asserted, laser power
exceeds programmed value
FAULT asserted
15
IOUT
No effect
FAULT asserted
FAULT asserted
16
VCCTO
No effect
LVFLAG flag asserted, laser
diode is off
LVFLAG asserted, laser diode
is off
17
MDREF
No effect
No effect
No effect
FMD flag asserted
Output current limited by
IBIASMAX[7:0] and IMODMAX[7:0]
No effect (Note 1)
No effect (Note 1)
Tx output is off if DIS_POL = 1
(default)
No effect if DIS_POL = 0
No effect if DIS_POL = 1 (default)
Tx output is off if DIS_POL = 0
(Note 1)
Tx output is off if DIS_POL = 1
(default)
No effect if DIS_POL = 0
No
No
No
No
No
No
No
No
No
No
No
No
effect
effect
effect
effect
(Note
(Note
(Note
(Note
1)
1)
1)
1)
effect
effect
effect
effect
(Note
(Note
(Note
(Note
1)
1)
1)
1)
effect
effect
effect
effect
(Note
(Note
(Note
(Note
1)
1)
1)
1)
18
MDIN
Output current limited by
IBIASMAX[7:0] and IMODMAX[7:0]
19
BMON
No effect
No effect (Note 1)
No effect
No effect (Note 3)—Redundant
path
20
VCCX
No effect
Board supply collapsed, POR on
(Note 2)
21
22
RINRIN+
No effect
No effect
No effect
No effect
No effect
No effect
23
VCCX
No effect
Board supply collapsed, POR on
(Note 2)
No effect (Note 3)—Redundant
path
24
LOS
No effect, but open-drain nMOS
output life can be stressed
No effect
No effect
—
EP
POR on, I/O device life can be
stressed (Note 2)
No effect
POR on
Note 1: Normal—Does not affect laser power.
Note 2: Supply-shorted current is assumed to be primarily on the circuit board (outside this device) and the main supply is collapsed by the short.
Note 3: Normal in functionality, but performance could be affected.
Warning: Shorted to VCC or shorted to ground on some pins can violate the Absolute Maximum Ratings.
24
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
3-Wire Interface
The MAX3710 implements a proprietary 3-wire digital
interface, and an external controller generates the clock.
The 3-wire interface consists of an SDA bidirectional data
line, an SCL clock signal input, and a CSEL chip-select
input (active high). The external master initiates a data
transfer by asserting the CSEL pin. Then it generates a
clock signal after the CSEL pin has been set to a logichigh. All data transfers are most significant bit (MSB) first.
Protocol
Each nonblock operation consists of 16-bit transfers (15bit address/data, 1-bit RWN). The bus master generates
16 clock cycles to SCL. All operations transfer 8 bits to
the MAX3710; the RWN bit determines if the cycle is read
or write. See Table 2.
Write Mode (RWN = 0)
The master generates 16 clock cycles at SCL in total. It
outputs a total of 16 bits (MSB first) to the SDA line at the
falling edge of the clock. The master closes the transmission by setting CSEL to 0. Figure 6 shows the 3-wire
interface timing.
Read Mode (RWN = 1)
The master generates 16 clock cycles at SCL in total. The
master outputs a total of 8 bits (MSB first) to the SDA line
at the falling edge of the clock. The SDA line is released
after the RWN bit has been transmitted. The slave outputs
8 bits of data (MSB first) at the rising edge of the clock.
The master closes the transmission by setting CSEL to 0.
Figure 6 shows the 3-wire interface timing.
Block Write Mode (RWN = 0)
The master initiates the block write mode by writing
H0x12 into the MODECTRL[7:0] register. The block write
mode starts by stretching the CSEL interval beyond
the 16 clock cycles, and it is exited automatically when
the master has written into any register other than
MODECTRL[7:0] and CSEL has been set to 0. The two
different modes of operation are described below:
BLOCK WRITE MODE 1 (STARTS AT ADDRESS H0x01)
Master sets CSEL to 1
ADDR H0x00 + RWN = 0
Data H0x12
Data 1 (ADDR H0x01)
Data 2 (ADDR H0x02)
Data 3 (ADDR H0x03)
Data 4 (ADDR H0x04)
...
Data 19 (ADDR H0x13)
Master sets CSEL to 0
BLOCK WRITE MODE 2 (STARTS AT ANY ADDRESS)
Master sets CSEL to 1
ADDR H0x00 + RWN = 0
Data H0x12
Master sets CSEL to 0
Master sets CSEL to 1
ADDR H0xN + RWN = 0
Data 1 (ADDR H0xN)
...
Data i (ADDR H0xN + i - 1)
Master sets CSEL to 0
Block Read Mode (RWN = 1)
The master initiates the block read mode by accessing
any register address and setting the RWN bit to 1. The
block read mode starts by stretching the CSEL interval
beyond the 16 clock cycles, and it is exited automatically
when the master has set CSEL to 0.
Table 2. Digital Communication Word
Structure
BIT
NAME
DESCRIPTION
15:9
Address
7-Bit Internal Register
Address
8
RWN
0: Write; 1: Read
7:0
Data
8-Bit Read or Write Data
25
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
WRITE MODE
CSEL
tL
tT
tCH tCL
SCL
0
1
2
3
4
5
6
7
8
9
A4
A3
A2
A1
A0
RWN
D7
D6
10
11
12
13
14
15
tDS
SDA
A6
A5
D5
D4
D3
D2
D1
D0
tDH
READ MODE
CSEL
tL
tT
tCH tCL
SCL
0
1
2
3
4
5
6
7
8
9
tDS
SDA
A6
A5
A4
10
11
12
13
14
15
tD
A3
A2
A1
A0
RWN
D7
D6
D5
D4
D3
D2
D1
D0
tDH
Figure 6. 3-Wire Digital Interface Timing Diagram
SCL
Mode Control
To speed up the laser control by a factor of two, the
MODINC, BIASINC, and APCINC registers can be
updated in normal mode. All other registers are read-only
in normal mode, which is the default mode.
SCL
75kΩ
VCCD
SDO
5kΩ
SDI
MAX3710
75kΩ
SDA
CP
CSEL
CSEL
75kΩ
µC
Setup mode allows the master to write unrestricted data
into any register except the status (TXSTAT1, TXSTAT2,
DPCSTAT, and RXSTAT) and read-only (BIASREG,
MODREG,
MD1REGH,
MD1REGL,
MD0REGH,
MD0REGL) registers. To enter the setup mode, H0x12 is
written to the MODECTRL register. After the MODECTRL
register has been set to H0x12 ,the next operation is
unrestricted. The setup mode is automatically exited after
the next operation is finished. This sequence must be
repeated if further unrestricted settings are necessary.
Fault-clear mode allows the clearing of all faults, and
restarts operation of the device. It is activated by writing
68h to the MODECTRL register.
Figure 7. 3-Wire Implementation Recommendation Using a
Generic Microcontroller
26
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
Register Descriptions
Mode Control Register (MODECTRL), Address: H0x00
Bit
D7
D6
D5
D4
D3
D2
D1
D0
MODECTRL
[7]
MODECTRL
[6]
MODECTRL
[5]
MODECTRL
[4]
MODECTRL
[3]
MODECTRL
[2]
MODECTRL
[1]
MODECTRL
[0]
Read/Write
W
W
W
W
W
W
W
W
POR State
0
0
0
0
0
0
0
0
No
No
No
No
No
No
No
No
Bit Name
Reset Upon Read
The MODECTRL register sets the device’s operational mode.
BIT
D[7:0]
NAME
DESCRIPTION
MODECTRL[7:0]
There are three operational modes for the device:
00h = normal mode (default)
12h = setup mode
68h = fault clear mode
Receiver Control Register 1 (RXCTRL1), Address: H0x01
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Bit Name
X
X
X
X
X
X
LOS_LOWBW
RO_EN
Read/Write
X
X
X
X
X
X
R/W
R/W
POR State
X
X
X
X
X
X
0
1
Reset Upon Read
X
X
X
X
X
X
No
No
The RXCTRL1 register sets the operation of the Rx circuitry.
BIT
NAME
D1
LOS_LOWBW
D0
RO_EN
DESCRIPTION
Sets the bandwidth of the Rx LOS circuitry.
0 = 2.5Gbps (default)
1 = 1.25Gbps
Enables the Rx output stage.
0 = disabled
1 = enabled (default)
27
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
Receiver Control Register 2 (RXCTRL2), Address: H0x02
Bit
Bit Name
D7
D6
D5
D4
D3
D2
D1
D0
LOS_RANGE
LOS_EN
LOS_POL
RX_POL
SQ_EN
RX_EN
SLEW_RATE
AZ_EN
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR State
0
1
1
1
0
1
1
1
No
No
No
No
No
No
No
No
Reset Upon Read
The RXCTRL2 register sets the operation of the Rx circuitry.
BIT
NAME
DESCRIPTION
D7
LOS_RANGE
D6
LOS_EN
D5
LOS_POL
D4
RX_POL
Sets the output polarity of ROUT.
0 = inverse
1 = normal (default)
D3
SQ_EN
Enables squelch of the output due to input signal below LOS threshold.
0 = disabled (default)
1 = enabled
D2
RX_EN
Enables the entire Rx block circuitry.
0 = disabled
1 = enabled (default)
D1
SLEW_RATE
D0
AZ_EN
Sets the amplitude range of the Rx LOS circuitry.
0 = 5 to 36mVP-P assert threshold (default)
1 = 14 to 115mVP-P
Enables the LOS circuitry.
0 = disabled
1 = enabled (default)
Sets the output polarity of the LOS output.
0 = inverse
1 = normal (default)
Sets the slew rate of the Rx output drivers.
0 = slow
1 = normal (default)
Auto-zero enable. This enables the Rx input offset cancellation loop.
0 = disabled
1 = enabled (default)
28
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
CML Output Amplitude Register (SET_CML), Address: H0x03
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Bit Name
X
X
X
X
SET_CML[3]
SET_CML[2]
SET_CML[1]
SET_CML[0]
Read/Write
X
X
X
X
R/W
R/W
R/W
R/W
POR State
X
X
X
X
1
0
1
0
Reset Upon Read
X
X
X
X
No
No
No
No
The SET_CML register sets the amplitude of ROUT.
BIT
D[3:0]
NAME
DESCRIPTION
SET_CML[3:0]
Sets the amplitude of the Rx output driver.
Typical values for amplitude:
0000 = 410mVP-P differential output amplitude
...
1010 = 800mVP-P differential output amplitude (default)
...
1111 = 1000mVP-P differential output amplitude
LOS Threshold Register (SET_LOS), Address: H0x04
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Bit Name
X
X
SET_LOS[5]
SET_LOS[4]
SET_LOS[3]
SET_LOS[2]
SET_LOS[1]
SET_LOS[0]
Read/Write
X
X
R/W
R/W
R/W
R/W
R/W
R/W
POR State
X
X
0
0
1
1
0
0
Reset Upon Read
X
X
No
No
No
No
No
No
The SET_LOS register adjusts the threshold of the LOS circuitry.
BIT
NAME
D[5:0]
SET_LOS[5:0]
DESCRIPTION
Sets the threshold of the LOS circuitry.
29
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
Transmitter Configuration Register (TXCFG), Address: H0x05
Bit
Bit Name
D7
D6
D5
D4
D3
D2
D1
D0
TRF[1]
TRF[0]
MDOFF_DLY
LPD_TH[2]
LPD_TH[1]
LPD_TH[0]
LPD_POL
LPD_MODE
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR State
0
0
0
0
0
1
1
0
No
No
No
No
No
No
No
No
Reset Upon Read
The TXCFG register configures the Tx circuitry.
BIT
NAME
DESCRIPTION
D[7:6]
TRF[1:0]
D5
MDOFF_DLY
Adjusts the delay of LPD sampling after the falling edge of burst enable.
0 = 50ns (default)
1 = 150ns
D[4:2]
LPD_TH[2:0]
Programs the LPD threshold in 12.5FA steps.
000 = 12.5FA/KIMD (default)
...
111 = 100FA/KIMD
D1
LPD_POL
D0
LPD_MODE
Adjusts the output rise/fall time of the laser transmitter.
00 = slow (default)
11 = fast
Sets the output polarity of LPD
0 = inverse
1 = normal (default)
Sets the LPD operational mode
0 = LPD flags when MDIN current exceeds LPD_TH[2:0] when burst off (default)
1 = LPD flags when BEN high or MDIN current exceeds LPD_TH[2:0] when burst off
30
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
Transmitter Control Register 1 (TXCTRL1), Address: H0x06
Bit
D7
D6
D5
D4
D3
D2
D1
D0
DPC_STOP
MDON_
DLY[1]
MDON_
DLY[0]
MDRNG
TXSTATMSK
[2]
TXSTATMSK
[1]
TXSTATMSK
[0]
SOFTRES
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR State
0
0
0
0
1
1
1
0
No
No
No
No
No
No
No
Yes
Bit Name
Reset Upon Read
The TXCTRL1 register configures the Tx circuitry.
BIT
D7
NAME
DPC_STOP
DESCRIPTION
Halts the APC and DPC loops. The DPC_RUN bit is reset.
0 = no action (default)
1 = halts loops and resets DPC_RUN bit
Sets the delay of the DPC sampling after the burst-enable rising edge.
00 = 0ns (default)
01 = 100ns
10 = 200ns
11 = 300ns
D[6:5]
MDON_DLY[1:0]
D4
MDRNG
D3
TXSTATMSK[2]
Sets mask for LVFLAG, FTOUT, and FIOUT.
0 = flags do cause fault condition
1 = flags do not cause fault condition (default)
D2
TXSTATMSK[1]
Sets mask for TXINLOS.
0 = flag do cause fault condition
1 = flag do not cause fault conditon (default)
D1
TXSTATMSK[0]
Sets mask for FMD.
0 = flag do cause fault condition
1 = flag do not cause fault condition (default)
D0
SOFTRES
MD range bit.
0 = fast TOSA MD response (default)
1 = slow TOSA MD response
Resets the contents of the registers to their default values. The device must be disabled
(DISABLE pin or TX_EN) to perform a soft reset.
0 = normal (default)
1 = reset
31
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
Transmitter Control Register 2 (TXCTRL2), Address: H0x07
Bit
D7
D6
D5
D4
D3
D2
D1
D0
FAULT_POL
MON_SEL
MDMON_EN
AUX_RSTR
DIS_MODE
DIS_POL
BEN_POL
TX_POL
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR State
1
0
0
0
0
1
1
1
No
No
No
No
No
No
No
No
Bit Name
Reset Upon Read
The TXCTRL2 register configures the Tx circuitry.
BIT
NAME
DESCRIPTION
Sets the polarity of the FAULT pin.
0 = inverted
1 = normal (default)
D7
FAULT_POL
D6
MON_SEL
D5
MDMON_EN
D4
AUX_RSTR
Enables restarting of APC and ERC loops by means of DISABLE pin.
0 = disabled (default)
1 = enabled
D3
DIS_MODE
Sets mode of operation for DISABLE pin.
0 = DISABLE pin powers down Tx output
1 = DISABLE pin acts as BEN (assuming BEN = 1)
D2
DIS_POL
Sets polarity for DISABLE pin.
0 = inverted
1 = normal (default)
D1
BEN_POL
Sets the polarity for the BEN input.
0 = inverted
1 = normal (default)
D0
TX_POL
Sets the BMON pin to output a mirror of BIAS current or MDIN current.
0 = laser bias current mirrored at 1/72 ratio (default)
1 = MDIN current mirrored at BMON
Enables BMON output.
0 = laser bias current mirrored (overrides MON_SEL) (default)
1 = MDIN current mirrored at BMON at a ratio of the current gain setting at KIMD
Sets Tx data path polarity.
0 = inverted
1 = normal (default)
32
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
Transmitter Control Register 3 (TXCTRL3), Address: H0x08
Bit
D7
D6
D5
D4
D3
D2
D1
D0
EOB_EN
DPC_EN
APC_EN
KIMD[1]
KIMD[0]
KRMD[2]
KRMD[1]
KRMD[0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR State
0
0
0
0
0
0
0
0
No
No
No
No
No
No
No
No
Bit Name
Reset Upon Read
The TXCTRL3 register configures the Tx circuitry.
BIT
NAME
DESCRIPTION
EOB_EN
End of burst update enable. Ignored during DPC acquisition.
0 = BIAS and MOD DACs updated continuously (default)
1 = BIAS and MOD DACs updated immediately following the BEN falling edge
D6
DPC_EN
Enables dual power control of the laser (closed-loop control of bias and modulation current).
0 = ERC loop disabled (freeze), APC loop mode depends on APC_EN bit (default)
1 = ERC and APC loops enabled
D5
APC_EN
Enables APC loop (closed-loop control of bias current).
0 = disabled (default)
1 = enabled
D7
D[4:3]
D[2:0]
KIMD[1:0]
Sets the current gain of the MD input in 3dB steps.
00 = x1 (default)
01 = x0.5
1x = x0.25
KRMD[2:0]
Sets the transimpedance gain of the MD input in 1.5dB steps. Total MD input stage gain
is equal to KIMD gain multiplied by the KRMD gain.
000 = 2800I (default)
001 = 1980I
010 = 1400I
011 = 990I
1xx = 700I
33
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
Transmitter Control Register 4 (TXCTRL4), Address: H0x09
Bit
D7
D6
D5
D4
D3
D2
D1
D0
DINT_EN
ARX_EN
MDAVG_CNT
IBUPDT_EN
IMUPDT_EN
MDLBW[1]
MDLBW[0]
ERSET[3]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR State
0
1
1
0
0
0
0
1
No
No
No
No
No
No
No
No
Bit Name
Reset Upon Read
The TXCTRL4 register configures the Tx circuitry.
BIT
NAME
DESCRIPTION
D7
DINT_EN
Routes internal clock signal to the Tx signal path (used in calibration).
0 = normal (default)
1 = routes internal data to the Tx signal path. Note that the data must be running at TIN
or the DPC loop freezes.
D6
ARX_EN
Enables auto-ranging for the APC loop.
0 = auto-ranging disabled
1 = auto-ranging enabled; see the Tracking Error Compensation section
D5
MDAVG_CNT
Sets the number of MD averages.
0 = DPC updates based on 32 averages in steady state
1 = DPC updates based on 256 averages in steady state (default)
IBUPDT_EN
Sets the way BIASREG[9:0] is written to:
APC on:
0 = maintains last value of BIASREG[9:0] in initialization (default)
1 = FAULT/POR/RESTART initializes BIASREG[9:2] with SET_IBIAS[7:0]
APC off:
0 = BIASREG can only be changed by writing to BIASINC[4:0] (default)
1 = if IBUPDT_EN is already set to 1 a write to SET_IBIAS[7:0] is passed to BIASREG[9:2]
(subject to EOB_EN)
IMUPDT_EN
Sets the way MODREG[8:0] is written to:
ERC on:
0 = maintains last value of MODREG[8:0] in initialization (default)
1 = FAULT/POR/RESTART initializes MODREG[8:1] with SET_IMOD[7:0]
ERC off:
0 = MODREG[8:0] can only be changed by writing to MODINC[4:0] (default)
1 = if IMUPDT_EN is already set to 1 a write to SET_IMOD[7:0] is passed to
MODREG[8:1] (subject to EOB_EN)
D[2:1]
MDLBW[1:0]
Controls the bandwidth of the MD input stage.
00 = normal mode (high-frequency signal feedthrough from TOSA is small) (default)
01 = less bandwidth
10 = even less bandwidth
11 = lowest bandwidth (external filter capacitor required on MD input to reduce excessive high-frequency signal feedthrough)
D0
ERSET[3]
D4
D3
Sets range of extinction ratio.
0 = reduced eR setting (5 to 12)
1 = normal eR setting (10 to 24) (default)
34
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
Transmitter Control Register 5 (TXCTRL5), Address: H0x0A
Bit
D7
D6
D5
D4
D3
D2
D1
D0
ERSET[2]
ERSET[1]
ERSET[0]
CPRG[4]
CPRG[3]
CPRG[2]
CPRG[1]
CPRG[0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR State
0
0
0
0
0
0
0
0
No
No
No
No
No
No
No
No
Bit Name
Reset Upon Read
The TXCTRL5 register configures the Tx circuitry.
BIT
NAME
DESCRIPTION
Sets extinction ratio for closed-loop operation.
D[7:5]
ERSET[2:0]
D[4:0]
CPRG[4:0]
If ERSET[3] = 1:
000 = 10 (default)
001 = 12
010 = 14
011 = 16
100 = 18
101 = 20
110 = 22
111 = 24
If ERSET[3] = 0:
000 = 5
001 = 6
010 = 7
011 = 8
100 = 9
101 = 10
110 = 11
111 = 12
Programs the internal MD current reference filter. Used during calibration to match extinction
ratios of the external PRBS data and the slower internal pattern enabled by DINT_EN.
Maximum Bias Current Register (IBIASMAX), Address: H0x0B
Bit
D7
D6
D5
D4
D3
D2
D1
D0
IBIASMAX
[7]
IBIASMAX
[6]
IBIASMAX
[5]
IBIASMAX
[4]
IBIASMAX
[3]
IBIASMAX
[2]
IBIASMAX
[1]
IBIASMAX
[0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR State
0
0
0
1
0
0
1
0
No
No
No
No
No
No
No
No
Bit Name
Reset Upon Read
The IBIASMAX register sets maximum bias current limit.
BIT
D[7:0]
NAME
IBIASMAX[7:0]
DESCRIPTION
Programs the maximum settable bias current (limits the maximum value that can be
written to the BIASREG[9:2] register). Note that it only relates to the eight most significant bits of the BIASREG register.
18d = 6.3mA bias current limit (default)
35
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
Maximum Modulation Current Register (IMODMAX), Address: H0x0C
Bit
D7
D6
D5
D4
D3
D2
D1
D0
IMODMAX
[7]
IMODMAX
[6]
IMODMAX
[5]
IMODMAX
[4]
IMODMAX
[3]
IMODMAX
[2]
IMODMAX
[1]
IMODMAX
[0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR State
0
0
1
1
0
0
0
0
No
No
No
No
No
No
No
No
Bit Name
Reset Upon Read
The IMODMAX register sets maximum modulation current limit.
BIT
D[7:0]
NAME
DESCRIPTION
IMODMAX[7:0]
Programs the maximum settable modulation current (limits the maximum value that can
be written to the MODREG[8:1] register). Note that it only relates to the eight most significant bits of the MODREG register.
48d = 19.5mA modulation current limit (default)
Initial or Open-Loop Bias Value Register (SET_IBIAS), Address: H0x0D
Bit
D7
D6
D5
D4
D3
D2
D1
D0
SET_
IBIAS[7]
SET_
IBIAS[6]
SET_
IBIAS[5]
SET_
IBIAS[4]
SET_
IBIAS[3]
SET_
IBIAS[2]
SET_
IBIAS[1]
SET_
IBIAS[0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR State
0
0
0
0
0
1
0
0
No
No
No
No
No
No
No
No
Bit Name
Reset Upon Read
The SET_IBIAS register sets the initial or open-loop bias current.
BIT
NAME
D[7:0]
SET_IBIAS[7:0]
DESCRIPTION
Programs the initial or open-loop bias current. The value in this register is sent to the
BIASREG[9:0] register’s eight most significant bits.
4d = 2.1mA bias current (default)
36
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
Initial or Open-Loop Modulation Value Register (SET_IMOD), Address: H0x0E
Bit
D7
D6
D5
D4
D3
D2
D1
D0
SET_
IMOD[7]
SET_
IMOD[6]
SET_
IMOD[5]
SET_
IMOD[4]
SET_
IMOD[3]
SET_
IMOD[2]
SET_
IMOD[1]
SET_
IMOD[0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR State
0
0
0
1
0
1
0
0
No
No
No
No
No
No
No
No
Bit Name
Reset Upon Read
The SET_IMOD register sets the initial or open-loop modulation current.
BIT
D[7:0]
NAME
DESCRIPTION
Programs the initial or open-loop bias current. The value in this register is sent to the
MODREG[8:0] register’s eight most significant bits.
20d = 10mA modulation current (default)
SET_IMOD[7:0]
Bias Increment Register (BIASINC), Address: H0x0F
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Bit Name
X
X
X
BIASINC[4]
BIASINC[3]
BIASINC[2]
BIASINC[1]
BIASINC[0]
Read/Write
X
X
X
R/W
R/W
R/W
R/W
R/W
POR State
X
X
X
0
0
0
0
0
Reset Upon Read
X
X
X
No
No
No
No
No
The BIASINC register increments/decrements bias current as described below
BIT
D[4:0]
NAME
BIASINC[4:0]
DESCRIPTION
APC enabled:
BIASINC[3:0] controls the BIAS step (coarse acquisition max step = 2 x BIASINC[3:0]).
APC disabled:
Laser BIAS current increment/decrement applied to BIASREG[9:0] upon write (two’s complement number, the range is +15/-16).
37
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
Modulation Increment Register (MODINC), Address: H0x10
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Bit Name
X
X
X
MODINC[4]
MODINC[3]
MODINC[2]
MODINC[1]
MODINC[0]
Read/Write
X
X
X
R/W
R/W
R/W
R/W
R/W
POR State
X
X
X
0
0
0
0
0
Reset Upon Read
X
X
X
No
No
No
No
No
The MODINC[4:0] register increments/decrements modulation current as described below.
BIT
D[4:0]
NAME
DESCRIPTION
ERC enabled:
MODINC[3:0] controls the MOD step (coarse acquisition max step = 2 x MODINC[3:0]).
ERC disabled:
Laser modulation current increment/decrement applied to MODREG[8:0] upon write
(two’s complement number, the range is +15/-16).
MODINC[4:0]
Average Laser Power-Setting Register (SET_2XAPC), Address: H0x11
Bit
D7
D6
D5
D4
D3
D2
D1
D0
SET_
2XAPC[7]
SET_
2XAPC[6]
SET_
2XAPC[5]
SET_
2XAPC[4]
SET_
2XAPC[3]
SET_
2XAPC[2]
SET_
2XAPC[1]
SET_
2XAPC[0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR State
0
0
1
0
0
0
0
0
No
No
No
No
No
No
No
No
Bit Name
Reset Upon Read
The SET_2XAPC register sets the average laser power for the APC loop (see the Design Procedure section for more information).
BIT
D[7:0]
NAME
DESCRIPTION
SET_2XAPC[7:0]
Average laser power setting x 2. This register must be maintained within the 64 to 255
range for proper operation.
APC Increment Register (APCINC), Address: H0x12
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Bit Name
X
X
X
X
APCINC[3]
APCINC[2]
APCINC[1]
APCINC[0]
Read/Write
X
X
X
X
R/W
R/W
R/W
R/W
POR State
X
X
X
X
0
0
0
0
Reset Upon Read
X
X
X
X
No
No
No
No
The APCINC register increments/decrements the SET_2XAPC register.
BIT
NAME
DESCRIPTION
D[3:0]
APCINC[3:0]
Increments or decrements the SET_2XAPC[7:0] value with the two’s complement value
from APCINC[3:0] (the range is +7/-8).
38
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
Transmitter Control Register 6 (TXCTRL6), Address: H0x13
Bit
D7
D6
D5
D4
D3
D2
D1
D0
THRSHLD
DPC_RUN
RESTART
SOFT_RSTR
[1]
SOFT_RSTR
[0]
BIAS_EN
MOD_EN
TX_EN
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR State
0
1
0
0
0
1
1
0
No
No
Yes
No
No
No
No
No
Bit Name
Reset Upon Read
The TXCTRL6 register configures the Tx circuitry.
BIT
D7
D6
D5
NAME
DESCRIPTION
THRSHLD
Sets threshold for updating BIASREG[9:0] in APC mode and BIASREG[9:0] and
MODREG[8:0] in DPC mode.
0 = 0.125LSB (default)
1 = 0.75LSB
DPC_RUN
Controls the APC and ERC loops.
0 = no action
1 = APC and ERC loops start from prefreeze conditions (subject to IBUPDT_EN and
IMUPDT_EN if starting from reset state); resets DPC_STOP bit (default)
RESTART
Forces APC and ERC loops into acquisition mode from reset state. Once the loop is in
steady state, the restart bit is reset.
0 = disabled (default)
1 = enabled
Soft restart for the DPC
00 = fastest acquisition (default)
...
11 = slowest (least disruptive) acquisition
D[4:3]
SOFT_RSTR[1:0]
D2
BIAS_EN
Enables the bias DAC.
0 = bias DAC disabled
1 = bias DAC enabled (default)
D1
MOD_EN
Enables the modulation DAC.
0 = mod DAC disabled
1 = mod DAC enabled (default)
D0
TX_EN
Enables the Tx data path, control loops, and the bias and modulation DACs.
0 = Tx disabled (default)
1 = Tx enabled
39
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
Bias DAC Readback Register (BIASREG), Address: H0x16
Bit
Bit Name
Read/Write
POR State
Reset Upon Read
D7
D6
D5
D4
D3
D2
D1
D0
BIASREG
[9]
BIASREG
[8]
BIASREG
[7]
BIASREG
[6]
BIASREG
[5]
BIASREG
[4]
BIASREG
[3]
BIASREG
[2]
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
No
No
No
No
No
No
No
No
The BIASREG register is a read-only register for the Tx bias DAC.
BIT
D[7:0]
NAME
DESCRIPTION
BIASREG[9:2]
Bias current DAC readback. The two LSBs for this register are located at address
H0x1F.
Modulation DAC Readback Register (MODREG), Address: H0x17
Bit
D7
D6
D5
D4
D3
D2
D1
D0
MODREG
[8]
MODREG
[7]
MODREG
[6]
MODREG
[5]
MODREG
[4]
MODREG
[3]
MODREG
[2]
MODREG
[1]
Read/Write
R
R
R
R
R
R
R
R
POR State
0
0
0
0
0
0
0
0
No
No
No
No
No
No
No
No
Bit Name
Reset Upon Read
The MODREG register is a read-only register for the Tx modulation DAC.
BIT
NAME
D[7:0]
MODREG[8:1]
DESCRIPTION
Modulation current DAC readback. The LSB for this register is located at address
H0x1F.
40
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
Monitor Diode Top Peak (Averaged) Register (MD1REGH), Address: H0x18
Bit
Bit Name
Read/Write
POR State
Reset Upon Read
D7
D6
D5
D4
D3
D2
D1
D0
MD1REGH
[7]
MD1REGH
[6]
MD1REGH
[5]
MD1REGH
[4]
MD1REGH
[3]
MD1REGH
[2]
MD1REGH
[1]
MD1REGH
[0]
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
No
No
No
No
No
No
No
No
The MD1REGH register is a read-only register for MD top peak current.
BIT
D[7:0]
NAME
DESCRIPTION
MD1REGH[7:0]
Stored (averaged) value for monitor-diode current peak corresponding to optical P1.
MD1REGH[7:0] is the upper 8 bits of the 16-bit value MD1[15:0].
Monitor Diode Top Peak (Averaged) Register (MD1REGL), Address: H0x19
Bit
D7
D6
D5
D4
D3
D2
D1
D0
MD1REGL
[7]
MD1REGL
[6]
MD1REGL
[5]
MD1REGL
[4]
MD1REGL
[3]
MD1REGL
[2]
MD1REGL
[1]
MD1REGL
[0]
Read/Write
R
R
R
R
R
R
R
R
POR State
0
0
0
0
0
0
0
0
No
No
No
No
No
No
No
No
Bit Name
Reset Upon Read
The MD1REGL register is a read-only register for MD top peak current.
BIT
NAME
D[7:0]
MD1REGL
DESCRIPTION
Stored (averaged) value for monitor-diode current peak corresponding to optical P1.
MD1REGL[7:0] is the lower 8 bits of the 16-bit value MD1[15:0].
41
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
Monitor Diode Bottom Peak (Averaged) Register (MD0REGH), Address: H0x1A
Bit
Bit Name
Read/Write
POR State
Reset Upon Read
D7
D6
D5
D4
D3
D2
D1
D0
MD0REGH
[7]
MD0REGH
[6]
MD0REGH
[5]
MD0REGH
[4]
MD0REGH
[3]
MD0REGH
[2]
MD0REGH
[1]
MD0REGH
[0]
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
No
No
No
No
No
No
No
No
The MD0REGH register is a read-only register for MD current.
BIT
D[7:0]
NAME
MD0REGH
DESCRIPTION
Stored (averaged) value for monitor-diode current peak corresponding to optical P0.
MD0REGH[7:0] is the upper 8 bits of the 16-bit value MD0[15:0].
Monitor Diode Bottom Peak (Averaged) Register (MD0REGL), Address: H0x1B
Bit
Bit Name
Read/Write
POR State
Reset Upon Read
D7
D6
D5
D4
D3
D2
D1
D0
MD0REGL
[7]
MD0REGL
[6]
MD0REGL
[5]
MD0REGL
[4]
MD0REGL
[3]
MD0REGL
[2]
MD0REGL
[1]
MD0REGL
[0]
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
No
No
No
No
No
No
No
No
The MD0REGL register is a read-only register for MD current.
BIT
D[7:0]
NAME
MD0REGL
DESCRIPTION
Stored (averaged) value for monitor-diode current peak corresponding to optical P0.
MD0REGL[7:0] is the lower 8 bits of the 16-bit value MD0[15:0].
42
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
LOS Status Register (RXSTAT), Address: H0x1C
D7
D6
D5
D4
D3
D2
D1
D0
(STICKY)
Bit Name
X
X
X
X
X
X
X
LOS_STAT
Read/Write
X
X
X
X
X
X
X
R
POR State
X
X
X
X
X
X
X
0
Reset Upon Read
X
X
X
X
X
X
X
Yes*
Bit
*Once flagged, these sticky registers remain flagged (logic 1) until they are read. Once read, they are reset to 0 if the source of
the flag has been removed.
The RXSTAT register is a status register for the Rx circuitry.
BIT
NAME
D0
LOS_STAT
DESCRIPTION
Copy of the LOS status.
Dual Power Control Status Register (DPCSTAT), Address: H0x1D
D7
D6
D5
(STICKY)
D4
(STICKY)
D3
(STICKY)
D2
(STICKY)
D1
(STICKY)
D0
(STICKY)
Bit Name
X
SSMODE
IBIASOVFL
IBIASUDFL
IMODOVFL
IMODUDFL
2XAPC_OVF
2XAPC_UDF
Read/Write
X
R
R
R
R
R
R
R
Bit
POR State
X
0
0
0
0
0
0
0
Reset Upon Read
X
No
Yes*
Yes*
Yes*
Yes*
Yes*
Yes*
*Once flagged these sticky registers remain flagged (logic 1) until they are read. Once read, they are reset to 0 if the source of
the flag has been removed.
The DPCSTAT register is a status register for the DPC circuitry.
BIT
NAME
D6
SSMODE
DESCRIPTION
DPC in steady state.
D5
IBIASOVFL
D4
IBIASUDFL
APC/DPC attempting to increase BIASREG[9:2] over IBIASMAX[7:0].
APC/DPC attempting to underflow BIASREG[9:0] register.
D3
IMODOVFL
DPC attempting to increase MODREG[8:1] over IMODMAX[7:0].
D2
IMODUDFL
DPC attempting to underflow MODREG[8:0] register.
D1
2XAPC_OVF
APCINC[3:0] setting attempting to overflow SET_2XAPC[7:0] register.
D0
2XAPC_UDF
APCINC[3:0] or SET_2XAPC[7:0] setting attempting to decrease SET_2XAPC[7:0] below
minimum value. If ARX_EN = 0 or {KIMD[1:0], KRMD[2:0]} = {00, 000}, minimum value is
32. If ARX_EN = 1 and {KIMD[1:0], KRMD[2:0]} ≠ {00, 000}, minimum value is 180.
43
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
Transmitter Status Register (TXSTAT1), Address: H0x1E
Bit
Bit Name
D7
(STICKY)
D6
(STICKY)
D5
(STICKY)
D4
(STICKY)
D3
(STICKY)
D2
(STICKY)
D1
(STICKY)
D0
(STICKY)
LVFLAG
LPDFLAG
BENLOS
TXINLOS
FMD
FIOUT
FTOUT
TX_FAULT
Read/Write
R
R
R
R
R
R
R
R
POR State
0
0
0
0
0
0
0
0
Yes*
Yes*
Yes*
Yes*
Yes*
Yes*
Yes*
Yes*
Reset Upon Read
*Once flagged, these sticky registers remain flagged (logic 1) until they are read. Once read, they are reset to 0 if the source of
the flag has been removed.
The TXSTAT1 register is a status register for the Tx circuitry.
BIT
NAME
D7
LVFLAG
DESCRIPTION
D6
LPDFLAG
IMD exceeds threshold during burst off (warning).
D5
BENLOS
BEN amplitude or common-mode too low (warning).
D4
TXINLOS
Indicates TIN AC signal too low during burst on (fault, maskable). When the MAX3710
senses a loss of signal at TIN, the DPC loop freezes. It resumes once a signal is
detected again at TIN.
D3
FMD
D2
FIOUT
IOUT open or shorted to GND. Fault is reported and FAULT output is set high (fault,
maskable).
D1
FTOUT
TOUT open or shorted to GND. Fault is reported and FAULT output is set high (fault,
maskable).
D0
TX_FAULT
VCCTO undervoltage detection (fault, maskable).
MDIN shorted to GND. Fault is reported, DPC is stopped, and FAULT output is set high
(fault, maskable).
A copy of FAULT.
Transmitter Status Register (TXSTAT2), Address: H0x1F
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Bit Name
X
X
X
X
X
BIASREG[1]
BIASREG[0]
MODREG[0]
Read/Write
X
X
X
X
X
R
R
R
POR State
X
X
X
X
X
0
0
0
Reset Upon Read
X
X
X
X
X
No
No
No
The TXSTAT2 register is a status register for the Tx circuitry.
BIT
NAME
D[2:1]
BIASREG[1:0]
LSBs of the BIASREG register.
DESCRIPTION
D0
MODREG[0]
LSB of the MODREG register.
44
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
Design Procedure
Global Recommendation
It is recommended to write to the MAX3710 either through
use of the block write mode or by writing to registers in
sequential order to ensure the proper register updating.
Open-Loop Control of Transmitter Average
Power and Modulation Amplitude
In this mode, the laser bias and modulation currents are
set by means of an external controller. The APC loop can
be closed externally by using the BIASINC register to
update the bias current DAC value. The laser modulation
current can be controlled by means of a lookup table
(LUT). If MD0[15:0] and MD1[15:0] are to be used by
the controller for Tx power monitoring, or to implement
a power-control loop, the MDIN gains—KIMD[1:0] and
KRMD[2:0] bits—must be set appropriately so that the
values in the MD0REGH[7:0] and MD1REGH[7:0] registers do not hit the minimum and maximum limits of 16
and 256.
To operate with open-loop control of modulation and bias
current, the registers need to be set as shown in Table 3.
Table 3. Open-Loop Setup Bits
ADDRESS
H0x08
TXCTRL3
H0x09
TXCTRL4
Hx013
TXCTRL6
BIT(S)
NAME
DESCRIPTION
VALUE
6
DPC_EN
Dual power
control enable
0
5
APC_EN
Automatic
power control
enable
0
Bias current
update
1
4
IBUPDT_EN
3
IMUPDT_EN
Modulation
current update
1
0
TX_EN
Transmitter
enable
1
Once the laser is attached and the device is powered up,
the IBIASMAX[7:0] and IMODMAX[7:0] registers should
be set to limits that prevent damage to the laser. Then the
transmitter is enabled by setting TX_EN = 1. The default
modulation and bias current is low, and it is likely that no
optical power will be detected until these currents are
increased.
The bias and modulation current can be adjusted by
either writing to the SET_IBIAS[7:0] and SET_IMOD[7:0]
registers directly or by writing to the BIASINC[4:0] and
MODINC[4:0] registers.
Closed-Loop Control of Transmitter
Average Power, Open-Loop Control
of Modulation Amplitude
To operate in APC mode, the registers need to be set as
shown in Table 4. For APC-only calibration, see Stage 1
of the Closed-Loop Control of Transmitter Average Power
and Extinction Ratio section.
Table 4. APC Setup Bits
ADDRESS
H0x08
TXCTRL3
H0x09
TXCTRL4
H0x13
TXCTRL6
BIT(S)
NAME
DESCRIPTION
VALUE
6
DPC_EN
Dual power
control enable
0
5
APC_EN
Average
power control
enable
1
4
IBUPDT_EN
Bias current
update
1
3
IMUPDT_EN
Modulation
current update
1
0
TX_EN
Transmitter
enable
1
45
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
Closed-Loop Control of Transmitter
Average Power and Extinction Ratio
4) If DPC operation, set ERSET[3:0] to target and set
CPRG[4:0] to 15.
To operate in DPC mode, the registers need to be set as
shown in Table 5.
5)Set IBIASMAX[7:0] and IMODMAX[7:0] to appropriate values according to laser’s capability.
Table 5. DPC Setup Bits
6)Set SET_IBIAS[7:0] and SET_IMOD[7:0] to 0.
ADDRESS
H0x08
TXCTRL3
H0x09
TXCTRL4
H0x13
TXCTRL6
BIT(S)
NAME
DESCRIPTION
VALUE
6
DPC_EN
Dual power
control enable
1
5
APC_EN
Average
power control
enable
1
4
IBUPDT_EN
Bias current
update
1
3
IMUPDT_EN
Modulation
current update
1
0
TX_EN
Transmitter
enable
1
Laser Calibration Procedure
This novel feature enables the customer to speed up the
calibration process and reduce the requirement on test
equipment. The customer needs to provide the following:
a) Extinction ratio and optical average power targets
b) Optical average power measurement fed back to the
testing algorithm
c)215 - 1 to 231 - 1 PRBS data pattern at data rate of
interest
d) Testing algorithm based on SPI read/write
The device automatically sets the laser bias and modulation current to satisfy the eR and PAVG targets. If transmitter operation at multiple power levels is required, calibration at each power level is recommended to guarantee
DPC loop performance.
Calibration Scheme:
Stage 1: Average laser power calibration
1) Set bits as shown in Table 4 for APC operation, or as
shown in Table 5 for DPC operation.
2) Provide
215
- 1 to
231
- 1 PRBS data at TIN.
3)Set TXCTRL4 DINT_EN = 1 and TX_POL = 1.
7)Set MODINC[3:0] and BIASINC[3:0] to nonzero values.
8)Set SET_2XAPC[7:0] to B4h (this allows for ±1.5dB
tracking error compensation range using APCINC).
9) Set TXCTRL6[7:0] to 67h.
10) Set BEN to a logic-high.
11)MDIN gain adjustment (repeat loop until average power is equal to or above the PAVG target).
a) Stop the loop by setting TXCTRL1[7] to 1.
b)Decrease MDIN stage gain (KIMD x
KRMD) 1.5dB by increasing KRMD[2:0] one
value, or by decreasing KRMD[2:0] one
value and increasing KIMD[1:0] one value.
c) Restart the loop by setting TXCTRL6[5] to 1.
12)Reduce SET_2XAPC[7:0] until average power measurement reaches the target.
13) For DPC operation, continue to Stage 2.
Stage 2: Extinction ratio calibration
1) Set DPC_STOP to 1.
2) To verify PAVG and eR, read MD0REGH[7:0] and
MD1REGH[7:0] and use the equations below to
calculate the apparent PAVG and eR at MDIN.
Averaging is recommended for improved accuracy.
2XAPC P=
=
AVG_APPARENT
MD0REGH[7 : 0]
+ MD1REGH[7 : 0]
8
IR
=
IMD1 8 × MD1REGH[7 : 0]
=
IMD0
MD0REGH[7 : 0]
3) If 2XAPC and IR are not sufficiently close to the
SET_2XAPC[7:0] and ERSET values, set DPC_
RUN = 1 and go to step 2. Otherwise, continue to
step 4.
4) Set DINT_EN = 0.
5)Read MD0REGH[7:0] and MD1REGH[7:0].
6)Adjust CPRG[4:0] until MD0REGH[7:0] and
MD1REGH[7:0] satisfy the IR equation from step 2.
46
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
If a higher IR is desired, increase CPRG[4:0]; likewise, if a lower IR is desired, decrease CPRG[4:0].
7)Set TXCTRL6[7:0] to 67h to restart the loop and
observe that MD0REGH[7:0] and MD1REGH[7:0]
are at the desired values.
Power Leveling
It is recommended to use KIMD and KRMD to obtain
different power level settings. Calibrate the DPC loop at
each power level. When switching between power levels
this procedure should be followed.
a) Stop loop by setting DPC_STOP = 1.
b) Change gain using KIMD or KRMD.
c) Run DPC by setting DPC_RUN = 1.
Applications Information
Laser Safety and IEC 825
Using the device’s laser driver alone does not ensure
that a transmitter design is compliant with IEC 825. The
entire transmitter circuit and component selections must
be considered. Each user must determine the level of
fault tolerance required by the application, recognizing
that Maxim products are neither designed nor authorized
for use as components in systems intended for surgical
implant into the body, for applications intended to support or sustain life, or for any other application in which
the failure of a Maxim product could create a situation
where personal injury or death could occur.
Tracking Error Compensation
It is recommended to use the APCINC register in autoranging mode for tracking error compensation. When
ARX_EN is set to 1, the SET_2XAPC register value is
automatically maintained within 180 to 255 by adjusting
the KRMD and KIMD registers accordingly. If {KIMD,
KRMD} = {00, 000}, the minimum SET_2XAPC value is
reduced from 180 to 32.
47
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
Register Summary
ADDR
R/W
REGISTER
NAME
BIT
NAME
H0x00
W
MODECTRL
7:0
MODECTRL
[7:0]
0h: normal mode
12h: setup mode
68h: fault clear mode
0 1
LOS_LOWBW
Set bandwidth of the LOS circuitry
0 = for 2.5Gbps
1 = for 1.25Gbps to 125Mbps
0
0
RO_EN
Enables Rx output stage
0 = disable
1 = enable
1
7
LOS_RANGE
0 = 5 to 36mVP-P
1 = 14 to 115mVP-P
0
6
LOS_EN
0 = disable
1 = enable
1
5
LOS_POL
0 = inverse
1 = normal
1
4
RX_POL
0 = inverse
1 = normal
1
3
SQ_EN
0 = disable
1 = enable
0
2
RX_EN
0 = disable complete Rx block, including
LOS
1 = enable
1
1
SLEW_RATE
0 = slow
1 = nominal
1
0
AZ_EN
0 = disable
1 = enable
1
H0x01
H0x02
RW
RW
RXCTRL1
RXCTRL2
FUNCTION/DESCRIPTION
H0x03
RW
SET_CML
3:0
SET_CML
[3:0]
Sets CML output amplitude
0d = 410mVP-P
…
10d = 800mVP-P
…
15d = 1000mVP-P
H0x04
RW
SET_LOS
5:0
SET_LOS
[5:0]
Programs the LOS threshold
DEFAULT
STATE
NOTES
1010
10d
00
1100
12d
48
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
Register Summary (continued)
ADDR
R/W
REGISTER
NAME
BIT
NAME
7:6
TRF[1:0]
5
H0x05
H0x06
RW
RW
MDOFF_DLY
TXCFG
4:2
LPD_TH[2:0]
1
LPD_POL
0
FUNCTION/DESCRIPTION
DEFAULT
STATE
Output tuning
00 = slow output edge speed
11 = fast output edge speed
00
Controls delay of MD falling edge before
LPD sampling:
0 = 50ns
1 = 150ns
0
Programs the LPD threshold in 12.5FA
steps:
000 = 12.5FA/KIMD
…
111 = 100FA/KIMD
NOTES
001
0 = inverted
1 = normal
1
LPD_MODE
0 = active on when burst off
1 = always active
0
7
DPC_STOP
0 = no action
1 = APC and ERC loops freeze and
DPC_RUN bit is reset
0
6:5
MDON_DLY
[1:0]
Controls the delay of MD rising edge
before DPC sampling in 100ns steps
00 = 0ns delay
11 = 300ns delay
00
4
MDRNG
MD range bit
0 = fast TOSA
1 = slow TOSA
0
3:1
TXSTATMSK
[2:0]
[2] = LVFLAG, FTOUT, FIOUT mask
[1] = TXINLOS mask
[0] = FMD mask
1
1
1
0
SOFTRES
Soft reset
0
TXCTRL1
49
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
Register Summary (continued)
ADDR
R/W
REGISTER
NAME
BIT
NAME
7
FAULT_POL
6
MON_SEL
5
H0x07
H0x08
RW
RW
MDMON_EN
TXCTRL2
FUNCTION/DESCRIPTION
DEFAULT
STATE
NOTES
Controls FAULT pin polarity
0 = inverted
1 = normal
1
0 = Bias current monitor output
1 = MD current monitor output
0
1 = enables MDMON output
0
When low,
bias current
monitor is
automatically selected
(overrides
MON_SEL)
0
4
AUX_RSTR
Enables restarting of APC and ERC loops
by means of the DISABLE input
0 = disabled
1 = enabled
3
DIS_MODE
0 = DISABLE pin powers down Tx output
1 = DISABLE pin acts as BEN (assuming
BEN = 1)
0
2
DIS_POL
0 = inverted
1 = normal
1
1
BEN_POL
0 = inverted
1 = normal
1
0
TX_POL
0 = inverted
1 = normal
1
7
EOB_EN
End-of-burst update enable
0 = BIAS and MOD DACs updated continuously
1 = BIAS and MOD DACs updated only
at the end of burst
0
6
DPC_EN
0 = disabled
1 = enabled
0
5
APC_EN
0 = APC loop disabled (freeze)
1 = APC loop enabled
0
KIMD[1:0]
Current gain of MD input stage
00 = x1
01 = x0.5
1X = x0.25
00
KRMD[2:0]
Voltage gain of the MD input stage
000 = 2800W
001 = 1980W
010 = 1400W
011 = 990W
1XX = 700W
000
TXCTRL3
4:3
2:0
50
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
Register Summary (continued)
ADDR
R/W
REGISTER
NAME
BIT
NAME
FUNCTION/DESCRIPTION
DEFAULT
STATE
NOTES
7
DINT_EN
0 = normal TIN routing
1 = routes internal data to Tx signal path
0
Used in calibration
6
ARX_EN
0 = auto-ranging disabled
1 = auto-ranging enabled
1
5
MDAVG_CNT
0 = 32 averages in steady state
1 = 256 averages in steady state
1
IBUPDT_EN
APC on:
0 = maintains last value of BIASREG[9:0]
in initialization (default)
1 = FAULT/POR/RESTART initializes
BIASREG[9:2] with SET_IBIAS[7:0]
APC off:
0 = BIASREG can only be changed by
writing to BIASINC[4:0] (default)
1 = if IBUPDT_EN is already set to 1
a write to SET_IBIAS[7:0] is passed to
BIASREG[9:2] (subject to EOB_EN)
0
IMUPDT_EN
ERC on:
0 = maintains last value of MODREG[8:0]
in initialization (default)
1 = FAULT/POR/RESTART initializes
MODREG[8:1] with SET_IMOD[7:0]
ERC off:
0 = MODREG[8:0] can only be changed
by writing to MODINC[4:0] (default)
1 = if IMUPDT_EN is already set to 1
a write to SET_IMOD[7:0] is passed to
MODREG[8:1] (subject to EOB_EN)
0
2:1
MDLBW[1:0]
Controls the bandwidth of the MD input
stage
00 = normal mode ( HF signal
feedthrough from the TOSA is small)
...
11 = lowest bandwidth (external filter
capacitor required on MD input to reduce
excessive HF signal feedthrough)
00
0
ERSET[3]
0 = reduced eR setting (5 to 12)
1 = normal eR setting (10 to 24)
1
4
H0x09
RW
TXCTRL4
3
51
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
Register Summary (continued)
ADDR
H0x0A
R/W
RW
REGISTER
NAME
BIT
NAME
FUNCTION/DESCRIPTION
7:5
ERSET[2:0]
Sets extinction ratio. If ERSET[3] = 1
(normal):
000 = 10 001 = 12
010 = 14 011 = 16
100 = 18 101 = 20
110 = 22 111 = 24
If ERSET[3] = 0 (reduced):
000 = 5 001 = 6
010 = 7 011 = 8
100 = 9 101 = 10
110 = 11 111 = 12
4:0
CPRG[4:0]
TXCTRL5
DEFAULT
STATE
NOTES
000
Programs the internal MD current reference filter
00000
H0x0B
RW
IBIASMAX
7:0
IBIASMAX
[7:0]
Max BIAS DAC setting allowed
0001
0010
18d H0x0C
RW
IMODMAX
7:0
IMODMAX
[7:0]
Max MOD DAC setting allowed
0011
0000
48d
H0x0D
RW
SET_IBIAS
7:0
SET_IBIAS
[7:0]
Open-loop or initial value setting
0000
0100
4d
H0x0E
RW
SET_IMOD
7:0
SET_IMOD
[7:0]
Open-loop or initial value setting
0001
0100
20d
BIASINC
[4:0]
APC enabled: Max BIAS step
(coarse acquisition max step = 2 x
BIASINC[3:0])
APC disabled: laser BIAS current setpoint inc/dec step size upon write
00000
ERC enabled: Max MOD step
(coarse acquisition max step = 2 x
MODINC[3:0])
ERC disabled: laser MOD current setpoint
inc/dec step size upon write
00000
Average laser power setting x 2
0010
0000
32d
Updates SET_2XAPC[7:0] with two’s
complement APCINC[3:0]
0000
H0x0F
RW
BIASINC
4:0
H0x10
RW
MODINC
4:0
MODINC
[4:0]
H0x11
RW
SET_2XAPC
7:0
SET_2XAPC
[7:0]
H0x12
RW
APCINC
3:0
APCINC
[3:0]
52
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
Register Summary (continued)
ADDR
R/W
REGISTER
NAME
NAME
FUNCTION/DESCRIPTION
DEFAULT
STATE
THRSHLD
Sets threshold for updating BIASREG[9:0]
in APC mode and BIASREG[9:0] and
MODREG[8:0] in DPC mode
0 = 0.125 LSB
1 = 0.75 LSB
0
DPC_RUN
Controls the APC and ERC loops
0 = no action
1 = APC and ERC loops restart from last
saved prefreeze conditions (subject to
IBUPT_EN and IMUPDT_EN) and DPC_
STOP bit is reset
1
5
RESTART
Forces loop out of steady-state mode
and enables the startup state machine
0 = disabled
1 = enabled
0
4:3
SOFT_
RSTR[1:0]
00 = fastest DPC acquisition
...
11 = slowest (least disruptive) DPC
acquisition
00
2
BIAS_EN
0 = bias DAC disabled
1 = bias DAC enabled
1
1
MOD_EN
0 = mod DAC disabled
1 = mod DAC enabled
1
0 = TX path and laser control loops disabled
1 = TX path and laser control loops
enabled
0
BIT
7
6
H0x13
RW
TXCTRL6
0
TX_EN
NOTES
H0x16
R
BIASREG
7:0
BIASREG
[9:2]
BIAS current DAC input readback
H0x17
R
MODREG
7:0
MODREG
[8:1]
MOD current DAC input readback
H0x18
R
MD1REGH
7:0
MD1REGH
[7:0]
(Averaged) MD current top peak digitized data
H0x19
R
MD1REGL
7:0
MD1REGL
[7:0]
(Averaged) MD current top peak digitized data
H0x1A
R
MD0REGH
7:0
MD0REGH
[7:0]
(Averaged) MD current bottom peak digitized data
H0x1B
R
MD0REGL
7:0
MD0REGL
[7:0]
(Averaged) MD current bottom peak digitized data
H0x1C
R
RXSTAT
0
LOS_STAT
Copy of the LOS status
sticky
53
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
Register Summary (continued)
ADDR
H0x1D
H0x1E
H0x1F
R/W
R
R
R
REGISTER
NAME
BIT
NAME
DPCSTAT
6
5
4
3
2
1
0
SSMODE
IBIASOVFL
IBIASUDFL
IMODOVFL
IMODUDFL
2XAPC_OVF
2XAPC_UDF
7
LVFLAG
6
FUNCTION/DESCRIPTION
DEFAULT
STATE
DPC in steady state
BIASREG[9:2] input over max warning
BIASREG[9:0] input underflow
MODREG[8:1] input over max warning
MODREG[8:0] input underflow
SET_2XAPC[7:0] wraparound high
SET_2XAPC[7:0] wraparound low
not sticky
sticky
sticky
sticky
sticky
sticky
sticky
VCCTO undervoltage detection
fault, sticky,
maskable
LPDFLAG
IMD exceeds threshold during burst off
warning,
sticky
5
BENLOS
BEN amplitude or common mode too low
warning,
sticky
4
TXINLOS
Indicates TXIN ac-signal too low during
burst on
fault, sticky,
maskable
3
FMD
MDIN shorted to GND. Fault is reported
and FAULT output is set high.
fault, sticky,
maskable;
stops DPC
regardless of
mask
2
FIOUT
IOUT open or shorted to GND. Fault is
reported and FAULT output is set high.
fault, sticky,
maskable
1
FTOUT
TOUT open or shorted to GND. Fault is
reported and FAULT output is set high.
fault, sticky,
maskable
TXSTAT1
TXSTAT2
NOTES
0
TX_FAULT
A copy of FAULT
fault, sticky
2:1
BIASREG[1:0]
LSBs of BIASREG[9:0]
0
MODREG[0]
LSB of MODREG[8:0]
Note: Sticky bits remain flagged even if the cause of the flag is removed. Reading the bit resets it if the source of the flag has been
removed.
54
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
Layout Considerations
The high-speed data inputs and outputs are the most
critical paths for the device, and great care should be
taken to minimize discontinuities on these transmission
lines between the connector and the IC. The following
are some suggestions for maximizing the device’s performance:
• The data inputs should be wired directly between the connector and IC without stubs.
• The data transmission lines to the laser should be kept
as short as possible, and the impedance of the transmission lines must be considered part of the laser
matching network.
Chip Information
PROCESS: SiGe BiPOLAR
Ordering Information
PART
MAX3710ETG+
• Ground path vias should be placed close to the IC
and the input/output interfaces to allow a return current path to the IC and the laser.
PIN-PACKAGE
24 TQFN-EP*
Note: Parts are guaranteed by design and characterization to
operate over the -40°C to +95°C ambient temperature range
(TA) and are tested up to +85°C.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*Exposed pad.
Package Information
• Minimize capacitance on the MDIN connection.
• An uninterrupted ground plane should be positioned
beneath the high-speed I/Os.
TEMP RANGE
-40°C to +85°C
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
• Maintain 100I differential transmission line impedance for the RIN, ROUT, TIN, and BEN I/Os.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
• Use good high-frequency layout techniques and multilayer boards with an uninterrupted ground plane to
minimize EMI and crosstalk.
24 TQFN-EP
T2444+3
21-0139
90-0021
Refer to the schematic and board layers of the MAX3710
Evaluation Kit data sheet for more information.
Exposed-Pad Package and Thermal
Considerations
The exposed pad on the MAX3710 is the only electrical
connection to ground and provides a very low-thermal
resistance path for heat removal from the IC. The pad
is also electrical ground on the device and must be soldered to the circuit board ground for proper thermal and
electrical performance. Refer to Application Note 862:
HFAN-08.1: Thermal Considerations for QFN and Other
Exposed-Paddle Packages for additional information.
55
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
Typical Application Circuit—GPON Triplexer Module
GPON TRIPLEXER MODULE
2x10 SFF GPON ONU MODULE
HOST BOARD
20-PIN
CONNECTOR
FILTER
VCC_HOST
MAX15059
FILTER
VCCD
4700pF
RLOS
4.7kΩ TO 10kΩ
VCCX
LOS
SD
1µF
RIN+
ROUT+
RIN-
ROUT-
1µF
20Ω
FR4
MICROSTRIP
1µF
ZDIFF = 100Ω
1µF
VCCTO
FR4
MICROSTRIP
TIN+
MDREF
CMDREF***
MAX3710
2.5Gbps LAM/BMLD
FERRITE
BEAD*
27Ω
100Ω
80Ω
ZDIFF = 100Ω
TINVCC
IOUT
100pF
VCC
5.1kΩ
5.1kΩ
CMDIN**
VCC
8.2kΩ
RFAULT
4.7kΩ TO 10kΩ
MDIN
BMON
39Ω
TX_EN
BEN+
TOUT
22pF
3kΩ
BEN-
8pF
SerDes
FAULT
CSEL
SCL
SDA
10Ω
3-WIRE
INTERFACE
LPD
DISABLE
SOFTWARE
3-WIRE
INTERFACE
*FERRITE BEAD: MURATA BML15HG102
**CMDIN TYPICALLY 10pF
***CMDREF TYPICALLY 100pF
RMON1
TX_FAULT
CONTROLLER
I2C
ADC
TX_SD
SCL
SDA
RMON2
56
MAX3710
125Mbps to 2.5Gbps, Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
Typical Application Circuit—EPON Triplexer Module
EPON TRIPLEXER MODULE
2x10 SFF EPON ONU MODULE
HOST BOARD
20-PIN
CONNECTOR
FILTER
VCC_HOST
FILTER
RMON1
VCCD
RLOS
4.7kΩ TO 10kΩ
VCCX
LOS
SD
1µF
RIN+
ROUT+
RIN-
ROUT-
1µF
20Ω
FR4
MICROSTRIP
1µF
ZDIFF = 100Ω
1µF
VCCTO
FR4
MICROSTRIP
TIN+
MDREF
CMDREF***
MAX3710
2.5Gbps LAM/BMLD
FERRITE
BEAD*
27Ω
100Ω
80Ω
ZDIFF = 100Ω
TINVCC
IOUT
100pF
VCC
5.1kΩ
5.1kΩ
CMDIN**
VCC
8.2kΩ
RFAULT
4.7kΩ TO 10kΩ
MDIN
BMON
39Ω
FAULT
CSEL
SCL
SDA
10Ω
TX_EN
BEN+
TOUT
22pF
3kΩ
BEN-
8pF
SerDes
3-WIRE
INTERFACE
DISABLE
TX_FAULT
TX_DISABLE
LPD
TX_SD (CMOS OUTPUT)
I2C
SCL
SDA
SOFTWARE
3-WIRE
INTERFACE
*FERRITE BEAD: MURATA BML15HG102
**CMDIN TYPICALLY 10pF
***CMDREF TYPICALLY 100pF
CONTROLLER
ADC
RMON2
57
MAX3710
125Mbps to 2.5Gbps Integrated Limiting Amplifier/
Burst Mode Laser Driver with Dual-Loop
Power Control
Revision History
REVISION
NUMBER
REVISION
DATE
0
8/11
DESCRIPTION
Initial release
PAGES
CHANGED
—
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical
Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated Products, Inc. 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
© 2011
Maxim Integrated Products 58
Maxim is a registered trademark of Maxim Integrated Products, Inc.