MAXIM MAX3798ETJ+

19-4360; Rev 0; 10/08
1.0625Gbps to 10.32Gbps, Integrated, LowPower SFP+ Limiting Amplifier and VCSEL Driver
The MAX3798 is a highly integrated limiting amplifier
and VCSEL driver designed for 1x/2x/4x/8x Fibre
Channel transmission systems at data rates up to
8.5Gbps as well as for 10GBASE-SR transmission systems at a data rate of 10.3125Gbps. Operating from a
single +3.3V supply, this low-power integrated limiting
amplifier and VCSEL driver IC enables a platform
design for SFP MSA as well as for SFP+ MSA-based
optical transceivers. The high-sensitivity limiting amplifier limits the differential input signal generated by a
transimpedance amplifier into a CML-level differential
output signal. The compact VCSEL driver provides a
modulation and a bias current for a VCSEL diode. The
optical average power is controlled by an average
power control (APC) loop implemented by a controller
that interfaces to the VCSEL driver through a 3-wire
digital interface. All differential I/Os are optimally backterminated for a 50Ω transmission line PCB design.
The use of a 3-wire digital interface reduces the pin
count while enabling advanced Rx (mode selection,
LOS threshold, LOS squelch, LOS polarity, CML output
level, signal path polarity, slew-rate control, deemphasis, and fast mode-select change time) and Tx settings
(modulation current, bias current, polarity, programmable deemphasis, eye-crossing adjustment, and eye
safety control) without the need for external components. The MAX3798 provides multiple current and voltage DACs to allow the use of low-cost controller ICs.
The MAX3798 is packaged in a lead-free, 5mm x 5mm,
32-pin TQFN package.
Applications
10GBASE-SR SFP+ Optical Transceiver
1x/2x/4x/8x SFF/SFP/SFP+ MSA Fibre Channel
(FC) Optical Transceiver
10GBASE-LR SFP+ Optical Transceiver (1310nm
VCSEL)
10GBASE-LRM SFP+ Optical Transceiver
(1310nm VCSEL)
Features
♦ Low Power Dissipation of 320mW at 3.3V Power
Supply
♦ Up to 10.32Gbps (NRZ) Operation
♦ 3mVP-P Receiver Sensitivity at 10.32Gbps
♦ 4psP-P DJ at Receiver Output at 8.5Gbps 8B/10B
♦ 4psP-P DJ at Receiver Output at 10.32Gbps
231 - 1 PRBS
♦ 26ps Rise and Fall Time at Rx/Tx Output
♦ Mode Select for High-Gain Mode and HighBandwidth Mode
♦ CML Output Slew-Rate Adjustment for High-Gain
Mode
♦ CML Output with Continuous Level Adjustment
♦ CML Output Squelch
♦ Polarity Select for Rx and Tx
♦ LOS Assert Level Adjustment
♦ LOS Polarity Select
♦ Modulation Current Up to 12mA Into 100Ω
Differential Load
♦ Bias Current Up to 15mA
♦ Integrated Eye Safety Features
♦ Selectable Deemphasis at Rx Output
♦ 3-Wire Digital Interface
♦ Eye-Crossing Adjustment of Modulation Output
♦ Programmable Deemphasis at Tx Output
♦ Fast Mode-Select Change Time of 10µs
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX3798ETJ+
-40°C to +85°C
32 TQFN-EP*
+Denotes a lead-free/RoHS-compliant package.
*EP = Exposed pad.
Typical Application Circuit and Pin Configuration appear at
end of data sheet.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAX3798
General Description
MAX3798
1.0625Gbps to 10.32Gbps, Integrated, LowPower SFP+ Limiting Amplifier and VCSEL Driver
ABSOLUTE MAXIMUM RATINGS
VCCR, VCCT, VCCD.................................................-0.3V to +4.0V
Voltage Range at DISABLE, SDA, SCL,
CSEL, MSEL, FAULT, BMON, LOS,
BMAX, MMAX, CAZ2...............................-0.3V to (VCC + 0.3V)
Voltage Range at ROUT+, ROUT- .....(VCC - 1V) to (VCC + 0.3V)
Voltage at TIN+, TIN-........................(VCC - 2.5V) to (VCC - 0.5V)
Voltage Range at TOUT+, TOUT- ......(VCC - 2V) to (VCC + 0.3V)
Voltage at BIAS...............................................................0 to VCC
Voltage at RIN+, RIN- ..........................(VCC - 2V) to (VCC - 0.2V)
Current Range into FAULT, LOS...........................-1mA to +5mA
Current Range into SDA........................................-1mA to +1mA
Current into ROUT+, ROUT- ...............................................40mA
Current into TOUT+, TOUT- ................................................60mA
Continuous Power Dissipation (TA = +70°C)
32-Pin TQFN (derate 34.5W/°C above +70°C) ...........2759mW
Operating Junction Temperature Range ...........-55°C to +150°C
Storage Temperature Range .............................-65°C to +160°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = 2.85V to 3.63V, TA = -40°C to +85°C, CML receiver output load is AC-coupled to differential 100Ω, CAZ = 1nF, transmitter output load is AC-coupled to differential 100Ω (see Figure 1), typical values are at +25°C, VCC = 3.3V, IBIAS = 6mA, IMOD = 6mA, unless
otherwise specified. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the MODE_SEL bit was used and the MSEL pin was left open.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
97
150
mA
2.85
3.63
V
1.0625
10.32
Gbps
POWER SUPPLY
Power-Supply Current
Power-Supply Voltage
ICC
Includes the CML output current;
excludes IBIAS = 6mA, IMOD = 6mA,
VDIFF_ROUT = 400mV P-P (Note 1)
VCC
GENERAL
Input Data Rate
Input/Output SNR
14.1
BER
10E-12
POWER-ON RESET
High POR Threshold
2.55
Low POR Threshold
IBIAS = IBIASOFF and IMOD = IMODOFF
2.75
2.3
2.45
75
100
125
MODE_SEL = 0 at 4.25Gbps
2
4
MODE_SEL = 1 at 8.5Gbps
3
8
V
V
Rx INPUT SPECIFICATIONS
Differential Input Resistance
RIN+/RIN-
RIN_DIFF
Input Sensitivity (Note 2)
VINMIN
Input Overload
VINMAX
Input Return Loss
SDD11
Input Return Loss
SCC11
1.2
mVP-P
VP-P
DUT is powered on, f 5GHz
14
DUT is powered on, f 16GHz
7
DUT is powered on, 1GHz < f 5GHz
8
DUT is powered on, 1GHz < f 16GHz
8
dB
dB
Rx OUTPUT SPECIFICATIONS
Differential Output Resistance
Output Return Loss
2
R OUTDIFF
SDD22
75
100
DUT is powered on, f 5GHz
11
DUT is powered on, f 16GHz
5
_______________________________________________________________________________________
125
dB
1.0625Gbps to 10.32Gbps, Integrated, LowPower SFP+ Limiting Amplifier and VCSEL Driver
(VCC = 2.85V to 3.63V, TA = -40°C to +85°C, CML receiver output load is AC-coupled to differential 100Ω, CAZ = 1nF, transmitter output load is AC-coupled to differential 100Ω (see Figure 1), typical values are at +25°C, VCC = 3.3V, IBIAS = 6mA, IMOD = 6mA, unless
otherwise specified. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the MODE_SEL bit was used and the MSEL pin was left open.)
PARAMETER
SYMBOL
Output Return Loss
SCC22
CONDITIONS
MIN
TYP
DUT is powered on, 1GHz < f 5GHz
9
DUT is powered on, 1GHz < f 16GHz
7
MAX
UNITS
dB
CML Differential Output Voltage
High
5mVP-P VIN 1200mVP-P, SET_CML[162]
595
800
1005
mVP-P
CML Differential Output Voltage
Medium
10mV P-P VIN 1200mV P-P, SET_CML[80]
300
400
515
mVP-P
Differential Output Signal When
Disabled
Outputs AC-coupled, VINMAX applied to
input VDIFF_ROUT = 800mV P-P at 8.5Gbps
(Notes 2, 3)
6
15
mVP-P
10mV P-P VIN 1200mV P-P,
MODE_SEL = 1, VDIFF_ROUT = 400mVP-P
26
35
5mVP-P VIN 1200mVP-P,
MODE_SEL = 0, SLEW_RATE = 1,
VDIFF_ROUT = 800mV P-P
28
50
5mVP-P VIN 1200mVP-P,
MODE_SEL = 0, SLEW_RATE = 0,
VDIFF_ROUT = 800mV P-P
45
60mV P-P VIN 400mVP-P at 10.32Gbps,
MODE_SEL = 1, VDIFF_ROUT = 400mVP-P
4
12
10mV P-P VIN 1200mV P-P at 8.5Gbps,
MODE _SEL = 1, VDIFF_ROUT = 400mV P-P
4
12
10mV P-P VIN 1200mV P-P at 4.25Gbps,
MODE _SEL = 1, VDIFF_ROUT = 400mV P-P
5
10mV P-P VIN 1200mV P-P at 8.5Gbps,
MODE _SEL = 0, VDIFF_ROUT = 400mV P-P
5
10
5mVP-P VIN 1200mVP-P at 4.25Gbps,
MODE _SEL = 0, SLEW_RATE = 1,
VDIFF_ROUT = 800mV P-P
6
20
5mVP-P VIN 1200mVP-P at 4.25Gbps,
MODE _SEL = 0, SLEW_RATE = 0,
VDIFF_ROUT = 800mV P-P
7
Input = 60mV P-P at 4.25Gbps,
MODE_SEL = 0, VDIFF_ROUT = 800mVP-P
0.36
0.51
Input = 60mV P-P at 8.5Gbps,
MODE _SEL = 1, VDIFF_ROUT = 400mV P-P
0.32
0.48
Data Output Transition Time
(20% to 80%)
(Notes 2, 3, 4)
tR/tF
ps
Rx TRANSFER CHARACTERISTICS
Deterministic Jitter
(Notes 2, 3, 5)
DJ
Random Jitter (Notes 2, 3)
Low-Frequency Cutoff
RJ
psP-P
psRMS
CAZ = 0.1μF
2
CAZ = open
500
kHz
Rx LOS SPECIFICATIONS
LOS Assert Sensitivity Range
LOS Hysteresis
14
10 x log (VDEASSERT/VASSERT) (Note 6)
1.25
77
2.1
mVP-P
dB
_______________________________________________________________________________________
3
MAX3798
ELECTRICAL CHARACTERISTICS (continued)
MAX3798
1.0625Gbps to 10.32Gbps, Integrated, LowPower SFP+ Limiting Amplifier and VCSEL Driver
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.85V to 3.63V, TA = -40°C to +85°C, CML receiver output load is AC-coupled to differential 100Ω, CAZ = 1nF, transmitter output load is AC-coupled to differential 100Ω (see Figure 1), typical values are at +25°C, VCC = 3.3V, IBIAS = 6mA, IMOD = 6mA, unless
otherwise specified. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the MODE_SEL bit was used and the MSEL pin was left open.)
PARAMETER
SYMBOL
CONDITIONS
MIN
LOS Assert/Deassert Time
(Note 7)
Low Assert Level
SET_LOS[7] (Notes 2, 6)
8
Low Deassert Level
SET_LOS[7] (Notes 2, 6)
14
Medium Assert Level
SET_LOS[32] (Notes 2, 6)
39
TYP
MAX
UNITS
80
μs
11
14
mVP-P
18
21
mVP-P
48
58
mVP-P
2.3
Medium Deassert Level
SET_LOS[32] (Notes 2, 6)
65
81
95
mVP-P
High Assert Level
SET_LOS[63] (Notes 2, 6)
77
94
112
mVP-P
High Deassert Level
SET_LOS[63] (Notes 2, 6)
127
158
182
mVP-P
Tx INPUT SPECIFICATIONS
Differential Input Voltage
VIN
Common-Mode Input Voltage
VINCM
Differential Input Resistance
RIN
Input Return Loss
SDD11
Input Return Loss
SCC11
Data rate = 1.0625Gbps to 4.25Gbps
0.2
2.4
Data rate = 4.25Gbps to 10.32Gbps
0.075
0.8
2.75
75
100
DUT is powered on, f 5GHz
15
DUT is powered on, f 16GHz
6
DUT is powered on, 1GHz < f 5GHz
9
DUT is powered on, 1GHz < f 16GHz
5
VP-P
V
125
dB
dB
Tx LASER MODULATOR
Maximum Modulation-On
Current into 100 Differential
Load
IMODMAX
Outputs AC-coupled, VCCTO 2.95V
Minimum Modulation-On Current
into 100 Differential Load
IMODMIN
Outputs AC-coupled
2
mA
2mA IMOD 12mA (Note 8)
4
%
ps
Modulation Current DAC
Stability
Modulation Current Rise Time/
Fall Time
Deterministic Jitter (Notes 2, 9)
4
tR/tF
DJ
12
mA
5mA IMOD 10mA, 20% to 80%,
SET_TXDE[3:0] = 10 (Notes 2, 4)
26
39
5mA IMOD 12mA, at 10.32Gbps,
250mVP-P VIN 800mV P-P,
SET_TXDE[4:1] = 0
6
12
5mA IMOD 12mA, at 10.32Gbps,
250mVP-P VIN 800mV P-P,
SET_TXDE[4:1] = 10
6
13
5mA IMOD 12mA, at 8.5Gbps,
250mVP-P VIN 800mV P-P,
SET_TXDE[4:1] = 0
6
12
5mA IMOD 12mA, at 8.5Gbps,
250mVP-P VIN 800mV P-P,
SET_TXDE[4:1] = 10
6
12
2mA IMOD 12mA, at 4.25Gbps
5
2mA IMOD 12mA, at 1.0625Gbps
5
_______________________________________________________________________________________
ps
1.0625Gbps to 10.32Gbps, Integrated, LowPower SFP+ Limiting Amplifier and VCSEL Driver
(VCC = 2.85V to 3.63V, TA = -40°C to +85°C, CML receiver output load is AC-coupled to differential 100Ω, CAZ = 1nF, transmitter output load is AC-coupled to differential 100Ω (see Figure 1), typical values are at +25°C, VCC = 3.3V, IBIAS = 6mA, IMOD = 6mA, unless
otherwise specified. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the MODE_SEL bit was used and the MSEL pin was left open.)
PARAMETER
SYMBOL
CONDITIONS
MIN
5mA IMOD 12mA, 250mV P-P VIN 800mVP-P
Random Jitter
Output Return Loss
SDD22
TYP
MAX
UNITS
0.17
0.5
psRMS
DUT is powered on, f 5GHz
12
DUT is powered on, f 16GHz
5
dB
Tx BIAS GENERATOR
Maximum Bias-On Current
IBIASMAX
Current into BIAS pin
Minimum Bias-On Current
IBIASMIN
Current into BIAS pin
15
mA
2mA IBIAS 15mA (Notes 2, 10)
BIAS Current DAC Stability
Compliance Voltage at BIAS
VBIAS
0.9
BIAS Current Monitor Current
Gain
IBMON
Compliance Voltage at BMON
VBMON
BIAS Current Monitor Current
Gain Stability
IBMON
2mA IBIAS 15mA (Note 10)
Excessive Voltage at BMAX
VBMAX
Average voltage, FAULT always occurs for
VBMAX VCC - 0.65V, FAULT never occurs
for VBMAX VCC - 0.55V
VCC 0.65V
Excessive Voltage at MMAX
VMMAX
Average voltage, FAULT always occurs for
VMMAX VCC - 0.65V, FAULT never occurs
for VMMAX VCC - 0.55V
VBMON
Average voltage, FAULT warning always
occurs for VBMON VCC - 0.55V, FAULT
warning never occurs for VBMON VCC 0.65V
External resistor to GND defines the
voltage gain
2
mA
4
%
2.1
V
16
0
mA/A
1.8
V
5
%
VCC 0.6V
VCC 0.55V
V
VCC 0.65V
VCC 0.6V
VCC 0.55V
V
VCC 0.65V
VCC 0.6V
VCC 0.55V
V
0.44
0.48
0.65
V
25
μA
Tx SAFETY FEATURES
Excessive Voltage at BMON
Excessive Voltage at BIAS
Maximum VCSEL Current in Off
State
VBIAS
I OFF
Average voltage, FAULT always occurs for
VBIAS 0.44V, FAULT never occurs for
VBIAS 0.65V
FAULT or DISABLE, VBIAS = VCC
SFP TIMING REQUIREMENTS
Mode-Select Change Time
DISABLE Assert Time
t_MODESEL
Time from rising or falling edge at MSEL
until Rx output PWD falls below 10ps
t_ OFF
Time from rising edge of DISABLE input
signal to IBIAS = IBIASOFF and IMOD =
IMODOFF
10
μs
1
μs
_______________________________________________________________________________________
5
MAX3798
ELECTRICAL CHARACTERISTICS (continued)
MAX3798
1.0625Gbps to 10.32Gbps, Integrated, LowPower SFP+ Limiting Amplifier and VCSEL Driver
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.85V to 3.63V, TA = -40°C to +85°C, CML receiver output load is AC-coupled to differential 100Ω, CAZ = 1nF, transmitter output load is AC-coupled to differential 100Ω (see Figure 1), typical values are at +25°C, VCC = 3.3V, IBIAS = 6mA, IMOD = 6mA, unless
otherwise specified. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the MODE_SEL bit was used and the MSEL pin was left open.)
PARAMETER
SYMBOL
CONDITIONS
DISABLE Negate Time
t_ ON
FAULT Reset Time of Power-On
Time
t_INIT
FAULT Reset Time
t_FAULT
MAX
UNITS
Time from falling edge of DISABLE to IBIAS
and IMOD at 90% of steady state when
FAULT = 0 before reset
500
μs
Time from power-on or negation of FAULT
using DISABLE
100
ms
Time from fault to FAULT on,
CFAULT 20pF, RFAULT = 4.7k
10
μs
Time DISABLE must be held high to reset
FAULT
DISABLE to Reset
MIN
TYP
5
μs
OUTPUT LEVEL VOLTAGE DAC (SET_CML)
Full-Scale Voltage
VFS
100 differential resistive load
Resolution
Integral Nonlinearity
INL
5mA ICML_LEVEL 20mA
1200
mVP-P
5
mVP-P
±0.9
LSB
LOS THRESHOLD VOLTAGE DAC (SET_LOS)
Full-Scale Voltage
VFS
Resolution
Integral Nonlinearity
INL
11mV P-P VTH_LOS 94mVP-P
94
mVP-P
1.5
mVP-P
±0.7
LSB
21
mA
BIAS CURRENT DAC (SET_IBIAS)
Full-Scale Current
IFS
Resolution
40
μA
Integral Nonlinearity
INL
1mA IBIAS 15mA
±1
LSB
Differential Nonlinearity
DNL
1mA IBIAS 15mA, guaranteed monotonic at 8-bit resolution (SET_IBIAS[8:1])
±1
LSB
21
mA
MODULATION CURRENT DAC (SET_IMOD)
Full-Scale Current
IFS
Resolution
40
μA
Integral Nonlinearity
INL
2mA IMOD 12mA
±1
LSB
Differential Nonlinearity
DNL
2mA IMOD 12mA, guaranteed monotonic at 8-bit resolution (SET_IMOD[8:1])
±1
LSB
CONTROL I/O SPECIFICATIONS
MSEL Input Current
IIH, I IL
150
μA
MSEL Input High Voltage
VIH
1.8
VCC
V
MSEL Input Low Voltage
VIL
0
0.8
V
MSEL Input Impedance
RPULL
75
110
k
420
800
DISABLE Input Current
DISABLE Input High Voltage
6
Internal pulldown resistor
40
I IH
I IL
VIH
12
Dependency on pullup resistance
1.8
_______________________________________________________________________________________
VCC
μA
V
1.0625Gbps to 10.32Gbps, Integrated, LowPower SFP+ Limiting Amplifier and VCSEL Driver
(VCC = 2.85V to 3.63V, TA = -40°C to +85°C, CML receiver output load is AC-coupled to differential 100Ω, CAZ = 1nF, transmitter output load is AC-coupled to differential 100Ω (see Figure 1), typical values are at +25°C, VCC = 3.3V, IBIAS = 6mA, IMOD = 6mA, unless
otherwise specified. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the MODE_SEL bit was used and the MSEL pin was left open.)
PARAMETER
SYMBOL
DISABLE Input Low Voltage
VIL
DISABLE Input Impedance
RPULL
CONDITIONS
MIN
TYP
0
Internal pullup resistor
5.5
8
MAX
UNITS
0.8
V
10.5
k
LOS, FAULT Output High Voltage
VOH
RLOS = 4.7k - 10k to VCC,
RFAULT = 4.7k - 10k to VCC
VCC 0.5
VCC
V
LOS, FAULT Output Low Voltage
VOL
RLOS = 4.7k - 10k to VCC,
RFAULT = 4.7k - 10k to VCC
0
0.4
V
2.0
VCC
V
0.8
V
3-WIRE DIGITAL I/O SPECIFICATIONS (SDA, CSEL, SCL)
Input High Voltage
VIH
Input Low Voltage
VIL
Input Hysteresis
VHYST
Input Leakage Current
I IL, IIH
0.082
VIN = 0V or VCC; internal pullup or pulldown
(75k typical)
Output High Voltage
VOH
External pullup of 4.7k to VCC
Output Low Voltage
VOL
External pullup of 4.7k to VCC
V
150
VCC 0.5
μA
V
0.4
V
1000
kHz
3-WIRE DIGITAL INTERFACE TIMING CHARACTERISTICS (see Figure 4)
SCL Clock Frequency
f SCL
SCL Pulse-Width High
tCH
0.5
400
μs
SCL Pulse-Width Low
tCL
0.5
μs
SDA Setup Time
tDS
100
ns
SDA Hold Time
tDH
100
ns
SCL Rise to SDA Propagation
Time
tD
5
ns
CSEL Pulse-Width Low
tCSW
500
ns
CSEL Leading Time Before the
First SCL Edge
tL
500
ns
CSEL Trailing Time After the
Last SCL Edge
tT
500
ns
SDA, SCL External Load
CB
Total bus capacitance on one line with
4.7k pullup to VCC
20
pF
Note 1: Supply current is measured with unterminated receiver CML output or with AC-coupled Rx output termination. The Tx output and the bias current output must be connected to a separate supply in order to remove the modulation/bias current
portion from the supply current. BIAS must be connected to 2.0V. TOUT+/- must be connected through 50Ω load resistors
to a separate supply voltage.
Note 2: Guaranteed by design and characterization, TA = -40°C to +95°C.
Note 3: The data input transition time is controlled by a 4th-order Bessel filter with -3dB frequency = 0.75 x data rate. The deterministic jitter caused by this filter is not included in the DJ generation specifications.
Note 4: Test pattern is 00001111 at 4.25Gbps for MODE_SEL = 0. Test pattern is 00001111 at 8.5Gbps for MODE_SEL = 1.
_______________________________________________________________________________________
7
MAX3798
ELECTRICAL CHARACTERISTICS (continued)
Note 5: Receiver deterministic jitter is measured with a repeating 231 - 1 PRBS equivalent pattern at 10.32Gbps. For 1.0625Gbps to
8.5Gbps, a repeating K28.5 pattern [00111110101100000101] is used. Deterministic jitter is defined as the arithmetic sum
of pulse-width distortion (PWD) and pattern-dependent jitter (PDJ).
Note 6: Measured with a k28.5 pattern from 1.0625Gbps to 8.5Gbps. Measured with 231 - 1 PRBS at 10.32Gbps.
Note 7: Measurement includes an input AC-coupling capacitor of 100nF and CCAZ of 100nF. The signal at the input is switched
between two amplitudes: Signal_ON and Signal_OFF.
1) Receiver operates at sensitivity level plus 1dB power penalty.
a) Signal_OFF = 0
Signal_ON = (+8dB) + 10log(min_assert_level)
b) Signal_ON = (+1dB) + 10log(max_deassert_level)
Signal_OFF = 0
2) Receiver operates at overload.
Signal_OFF = 0
Signal_ON = 1.2VP-P
max_deassert_level and the min_assert_level are measured for one LOS_THRESHOLD setting.
Note 8: Gain stability is defined as [(I_measured) - (I_reference)]/(I_reference) over the listed current range, temperature, and VCC
from +2.95V to +3.63V. Reference current measured at VCC = +3.2V, TA = +25°C.
Note 9: Transmitter deterministic jitter is measured with a repeating 27 - 1 PRBS, 72 0s, 27 - 1 PRBS, and 72 1s pattern at
10.32Gbps. For 1.0625Gbps to 8.5Gbps, a repeating K28.5 pattern [00111110101100000101] is used. Deterministic jitter is
defined as the arithmetic sum of PWD and PDJ.
Note 10: Gain stability is defined as [(I_measured) - (I_reference)]/(I_reference) over the listed current range, temperature, and VCC
from +2.85V to +3.63V. Reference current measured at VCC = +3.3V, TA = +25°C.
1nF
50Ω
VCCT
1000pF
50Ω
VCCR
400Ω
RIN-
RIN+
VCCR
CAZ2
CAZ1
CONTROLLER
0.1μF
LOS
VCCR
VCCT
MMAX
0.1μF
4.7kΩ
VEER
VEET
400Ω
4.7kΩ
BMAX
MSEL
FAULT
50Ω
0.1μF
50Ω
OSCILLOSCOPE
BIAS
ROUT+
50Ω
CONTROLLER
50Ω
MAX3798
0.1μF
0.1μF
50Ω
TOUT+
ROUT-
OSCILLOSCOPE
0.1μF
50Ω
CONTROLLER
DISABLE
BMON
TIN-
TIN+
CSEL
VCCD
SDA
VCCD
VCCT
1000pF
0.1μF
CONTROLLER
0.1μF
0.1μF
1kΩ
50Ω
VCCR
VCCT
0.1μF VCCD
50Ω
1μH
50Ω
VCCT
1000pF
VCC
50Ω
TOUT-
SCL
MAX3798
1.0625Gbps to 10.32Gbps, Integrated, LowPower SFP+ Limiting Amplifier and VCSEL Driver
Figure 1. Test Circuit for VCSEL Driver Characterization
8
_______________________________________________________________________________________
1.0625Gbps to 10.32Gbps, Integrated, LowPower SFP+ Limiting Amplifier and VCSEL Driver
DETERMINISTIC JITTER
vs. INPUT AMPLITUDE AT 4.25Gbps
11
AT 4.25Gbps MODE_SEL = 0
340
330
AT 8.5Gbps MODE_SEL = 1
320
9
SLEW_RATE = 0
8
7
6
SLEW_RATE = 1
5
AT 8.5Gbps
5
4
3
AT 10.32Gbps
2
310
4
3
300
200
400
600
800
1000
1
0
1200
200
400
600
1000
1200
0
200
400
600
800
1000
1200
INPUT AMPLITUDE (mVP-P)
INPUT AMPLITUDE (mVP-P)
INPUT AMPLITUDE (mVP-P)
DETERMINISTIC JITTER
vs. DATA RATE
BER
vs. INPUT AMPLITUDE
OUTPUT EYE DIAGRAM AT 10.32Gbps
PATTERN = k28.5
9
MAX3798 toc06
1.0E-01
MAX3798 toc04
10
1.0E-02
AT 8.5Gbps
MODE_SEL = 0
1.0E-03
8
AT 8.5Gbps
MODE_SEL = 1
1.0E-04
MODE_SEL = 0, SLEW_RATE = 1
1.0E-05
BER
7
800
MAX3798 toc05
0
DETERMINISTIC JITTER (ps)
10
PATTERN = PRBS, MODE_SEL = 1
6
DETERMINISTIC JITTER (ps)
350
7
MAX3798 toc02
PATTERN = k28.5, MODE_SELECT = 0
DETERMINISTIC JITTER (ps)
360
RANDOM JITTER (ps)
12
MAX3798 toc01
370
DETERMINISTIC JITTER
vs. INPUT AMPLITUDE
MAX3798 toc03
RANDOM JITTER
vs. INPUT AMPLITUDE
6
1.0E-06
50mV/div
1.0E-07
5
1.0E-08
4
1.0E-09
3
1.0E-10
MODE_SEL = 1
1.0E-11
2
0
2
4
6
8
10
0.5
12
1.0
1.5
2.0
2.5
20ps/div
INPUT AMPLITUDE (mVP-P)
DATA RATE (Gbps)
OUTPUT EYE DIAGRAM AT 8.5Gbps
OUTPUT EYE DIAGRAM AT 4.25Gbps
OUTPUT EYE DIAGRAM AT 4.25Gbps
MAX3798 toc07
MAX3798 toc09
MAX3798 toc08
MODE_SEL = 0, SLEW_RATE = 1
MODE_SEL = 1
50mV/div
100mV/div
50mV/div
20ps/div
50ps/div
50ps/div
_______________________________________________________________________________________
9
MAX3798
Typical Operating Characteristics—Limiting Amplifier
(VCC = 3.3V, TA = +25°C, unless otherwise specified. Figure 1 shows the typical setup used for measurements. Registers are set to
default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the MODE_SEL bit was
used and the MSEL pin was left open.)
Typical Operating Characteristics—Limiting Amplifier (continued)
(VCC = 3.3V, TA = +25°C, unless otherwise specified. Figure 1 shows the typical setup used for measurements. Registers are set to
default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the MODE_SEL bit was
used and the MSEL pin was left open.)
OUTPUT EYE DIAGRAM AT 4.25Gbps
TRANSITION TIME vs. INPUT AMPLITUDE
45
MODE_SEL = 0, SLEW_RATE = 0, RXDE_EN = 0
100mV/div
140
35
MODE_SEL = 0, SLEW_RATE = 0, RXDE_EN = 1
30
25
MODE_SEL = X, SLEW_RATE = 1, RXDE_EN = 0
20
MODE_SEL = X, SLEW_RATE = 1, RXDE_EN = 1
15
10
0
120
DEASSERT
100
80
60
40
PATTERN = 00001111,
DATA RATE = 8.5Gbps,
20% TO 80%
5
ASSERT
20
0
0
50ps/div
160
LOS THRESHOLD (mV)
TRANSITION TIME (ps)
40
LOS THRESHOLD vs. DAC SETTING
180
MAX3798 toc12
50
MAX3798 toc11
MAX3798 toc10
MODE_SEL = 0, SLEW_RATE = 0
200
400
600
800
1000
1200
0
7
14
21
INPUT AMPLITUDE (mVP-P)
MAX3798 toc14
-10
-5
-10
SDD11 (dB)
-15
-16
49
56
63
-15
-20
MODE_SEL = 1
42
0
SDD22 (dB)
-14
35
Rx OUTPUT RETURN LOSS
Rx INPUT RETURN LOSS
0
MAX3798 toc13
USING FINISAR ROSA
-13
28
SET_LOS[5:0]
MAX3798 toc15
SENSITIVITY vs. DATA RATE
-12
SENSITIVITY OMA (dBm)
-30
-40
-20
-25
-30
-35
MODE_SEL = 0
-40
-17
-50
-18
-60
100M
-45
2
4
6
8
10
12
1G
DATA RATE (Gbps)
100G
10G
-50
100M
1G
CML OUTPUT AMPLITUDE
vs. DAC SETTING
MAX3798 toc16
1400
1200
1000
800
600
400
200
0
0
50
100
150
200
250
300
SET_CML[7:0]
10
10G
FREQUENCY (Hz)
FREQUENCY (Hz)
CML OUTPUT AMPLITUDE (mVP-P)
MAX3798
1.0625Gbps to 10.32Gbps, Integrated, LowPower SFP+ Limiting Amplifier and VCSEL Driver
______________________________________________________________________________________
100G
1.0625Gbps to 10.32Gbps, Integrated, LowPower SFP+ Limiting Amplifier and VCSEL Driver
TOTAL SUPPLY CURRENT
vs. TEMPERATURE
TOTAL SUPPLY CURRENT
vs. TEMPERATURE
IBIAS = 12mA
SUPPLY CURRENT (mA)
110
100
90
IBIAS = 9mA
IBIAS = 2mA
70
60
IMOD = 2mA; RECEIVER OUTPUT = 400mVP-P;
TOTAL SUPPLY MEASURED USING THE SETUP
IN FIGURE 1.
50
40
-40 -25 -10
5
20
35
50
65
80
IMOD = 9mA
130
120
110
100
90
IMOD = 2mA
80
70
60
IBIAS = 2mA; RECEIVER OUTPUT = 400mVP-P;
TOTAL SUPPLY MEASURED USING THE SETUP
IN FIGURE 1.
50
40
95
-40 -25 -10
TEMPERATURE (°C)
5
20
35
50
OPTICAL EYE DIAGRAM
95
14ps/div
OPTICAL EYE DIAGRAM
MAX3798 toc22
MAX3798 toc21
8.5Gbps, SET_IMOD = 60, 27 - 1 PRBS,
4.25Gbps, SET_IMOD = 60, 27 - 1 PRBS,
850nm VCSEL, MASK WITH 54%
850nm VCSEL, MASK WITH 46%
2.125Gbps, SET_IMOD = 60, 27 - 1 PRBS,
850nm VCSEL, MASK WITH 50%
17ps/div
34ps/div
68ps/div
DETERMINISTIC JITTER
vs. MODULATION CURRENT
TRANSITION TIME
vs. MODULATION CURRENT
TRANSITION TIME
vs. DEEMPHASIS SETTING
7.0
6.5
6.0
5.5
5.0
FALL TIME
33
TRANSITION TIME (ps)
7.5
38
28
RISE TIME
23
18
13
6
8
10
MODULATION CURRENT (mAP-P)
12
37
35
FALL TIME
33
31
RISE TIME
27
PATTERN = 11110000,
DATA RATE = 8.5Gbps
3
4
PATTERN = 11110000,
DATA RATE = 8.5Gbps,
IMOD = 10mAP-P
39
29
8
4.5
41
MAX3798 toc24
PATTERN = PRBS, DATA RATE = 10.32Gbps
MAX3798 toc23
8.0
DETERMINISTIC JITTER (ps)
80
OPTICAL EYE DIAGRAM
MAX3798 toc20
2
65
TEMPERATURE (°C)
MAX3798 toc25
80
IMOD = 12mA
10.3Gbps, SET_IMOD = 60, 27 - 1 PRBS,
850nm VCSEL, MASK WITH 44%
TRANSITION TIME (ps)
SUPPLY CURRENT (mA)
120
MAX3798 toc18
130
OPTICAL EYE DIAGRAM
MAX3798 toc19
160
150
140
MAX3798 toc17
140
25
2
4
6
8
10
MODULATION CURRENT (mAP-P)
12
0
1
2
3
4
5
6
7
8
9 10 11
SET_TXDE[3:0]
______________________________________________________________________________________
11
MAX3798
Typical Operating Characteristics—VCSEL Driver
(VCC = 3.3V, TA = +25°C, unless otherwise specified. Figure 1 shows the typical setup used for measurements. Registers are set to
default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the MODE_SEL bit was
used and the MSEL pin was left open.)
Typical Operating Characteristics—VCSEL Driver (continued)
(VCC = 3.3V, TA = +25°C, unless otherwise specified. Figure 1 shows the typical setup used for measurements. Registers are set to
default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the MODE_SEL bit was
used and the MSEL pin was left open.)
MODULATION CURRENT
vs. DAC SETTING
BIAS CURRENT
vs. DAC SETTING
RLOAD = 50Ω
8
6
RLOAD = 100Ω
4
12
BIAS CURRENT (mA)
10
MAX3798 toc28
MAX3798 toc27
RLOAD = 75Ω
12
TRANSMITTER DISABLE
14
MAX3798 toc26
14
10
8
6
LOW
OUTPUT
50
100
150
200
250
300
0
50
SET_IMOD[8:0]
100
150
200
250
300
RESPONSE TO FAULT
MAX3798 toc29
3.3V
EXTERNALLY
FORCED FAULT
VBIAS
tON = 420ns
FAULT
LOW
HIGH
LOW
OUTPUT
EXTERNAL
FAULT
HIGH
DISABLE
LOW
DISABLE
MAX3798 toc31
VBIAS
HIGH
FAULT
LOW
FAULT RECOVERY
MAX3798 toc30
VCC
LOW
HIGH
LOW
OUTPUT
OUTPUT
1μs/div
1μs/div
4μs/div
Tx OUTPUT RETURN LOSS
Tx INPUT RETURN LOSS
FREQUENCY ASSERTION OF DISABLE
MAX3798 toc32
0
MAX3798 toc33
0
EXTERNALLY
FORCED FAULT
-10
-5
-10
-15
LOW
HIGH
LOW
SDD22 (dB)
-20
HIGH
SDD11 (dB)
VBIAS
100ns/div
SET_IBIAS[8:0]
TRANSMITTER ENABLE
DISABLE
HIGH
DISABLE
0
0
FAULT
LOW
FAULT
2
0
DISABLE
3.3V
4
2
FAULT
VCC
MAX3798 toc34
MODULATION CURRENT (mA)
MAX3798
1.0625Gbps to 10.32Gbps, Integrated, LowPower SFP+ Limiting Amplifier and VCSEL Driver
-30
-20
-25
-30
-40
-35
-50
OUTPUT
-40
4μs/div
-60
100M
1G
10G
FREQUENCY (Hz)
12
100G
-45
100M
1G
10G
FREQUENCY (Hz)
______________________________________________________________________________________
100G
1.0625Gbps to 10.32Gbps, Integrated, LowPower SFP+ Limiting Amplifier and VCSEL Driver
DETERMINISTIC JITTER
vs. PULSE-WIDTH SETTING
8
7
6
5
4
DOWN
EYE CROSSING
3
700
IBIAS = 12mA
MONITOR CURRENT (μA)
DETERMINISTIC JITTER (ps)
9
MAX3798 toc36
PATTERN = PRBS, DATA RATE = 10.32Gbps
UP
800
MAX3798 toc35
10
BIAS MONITOR CURRENT
vs. TEMPERATURE
600
500
400
IBIAS = 8mA
300
IBIAS = 2mA
200
100
2
0
-7
-5
-3
-1
1
3
5
7
-40 -25 -10
SET_PWCTRL[3:0]
5
20
35
50
65
80
95
TEMPERATURE (°C)
Pin Description
PIN
NAME
FUNCTION
1
LOS
2
MSEL
Mode-Select Input, TTL/CMOS. Set the MSEL pin or MODE_SEL bit (set by the 3-wire digital interface)
to logic-high for high-bandwidth mode. Setting MSEL and MODE_SEL logic-low for high-gain mode.
The MSEL pin is internally pulled down by a 75k resistor to ground.
3, 6, 27, 30
VCCR
Power Supply. Provides supply voltage to the receiver block.
4
ROUT+
5
ROUT-
7
VCCD
8
DISABLE
9
SCL
Serial Clock Input, TTL/CMOS. This pin has a 75k internal pulldown.
10
SDA
Serial Data Bidirectional Input, TTL/CMOS. Open-drain output. This pin has a 75k internal pullup,
but it requires an external 4.7k pullup resistor to meet the 3-wire digital timing specification. (Data
line collision protection is implemented.)
11
CSEL
Chip-Select Input, TTL/CMOS. Setting CSEL to logic-high starts a cycle. Setting CSEL to logic-low
ends the cycle and resets the control state machine. Internally pulled down by a 75k resistor to
ground.
12, 15, 18,
21
VCCT
Power Supply. Provides supply voltage to the transmitter block.
13
TIN+
Noninverted Transmit Data Input, CML
Loss-of-Signal Output, Open Drain. The default polarity of LOS is high when the level of the input
signal is below the preset threshold set by the SET_LOS DAC. Polarity of the LOS function can be
inverted by setting LOS_POL = 0. The LOS circuitry can be disabled by setting the bit LOS_EN = 0.
Noninverted Receive Data Output, CML. Back-terminated for 50 load.
Inverted Receive Data Output, CML. Back-terminated for 50 load.
Power Supply. Provides supply voltage for the digital block.
Transmitter Disable Input, TTL/CMOS. Set to logic-low for normal operation. Logic-high or open
disables both the modulation and bias current. Internally pulled up by an 8k resistor to VCC.
______________________________________________________________________________________
13
MAX3798
Typical Operating Characteristics—VCSEL Driver (continued)
(VCC = 3.3V, TA = +25°C, unless otherwise specified. Figure 1 shows the typical setup used for measurements. Registers are set to
default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the MODE_SEL bit was
used and the MSEL pin was left open.)
1.0625Gbps to 10.32Gbps, Integrated, LowPower SFP+ Limiting Amplifier and VCSEL Driver
MAX3798
Pin Description (continued)
PIN
NAME
14
TIN-
16
BMON
17
VEET
FUNCTION
Inverted Transmit Data Input, CML
Bias Current Monitor Output. Current out of this pin develops a ground-referenced voltage across an
external resistor that is proportional to the laser bias current.
Ground. Provides ground for the transmitter block.
19
TOUT-
Inverted Modulation Current Output. Back-termination of 50 to VCCT.
20
TOUT+
Noninverted Modulation Current Output. Back-termination of 50 to VCCT.
22
BIAS
23
FAULT
Transmitter Fault Output, Open Drain. Logic-high indicates a fault condition. Fault remains high
even after the fault condition has been removed. A logic-low occurs when the fault condition has
been removed and the fault latch has been cleared by the DISABLE signal.
24
BMAX
Analog VCSEL Bias Current Limit. A resistor connected between BMAX and VCCT sets the maximum
allowed VCSEL bias current.
25
MMAX
Analog VCSEL Modulation Current Limit. A resistor connected between MMAX and VCCT sets the
maximum allowed VCSEL modulation current.
26
VEER
Ground. Provides ground for the receiver block.
28
RIN-
Inverted Receive Data Input, CML
29
RIN+
Noninverted Receive Data Input, CML
31
CAZ2
Offset Correction Loop Capacitor. A capacitor connected between this pin and CAZ1 sets the time
constant of the offset correction loop. The offset correction can be disabled through the digital
interface by setting the bit AZ_EN = 0.
32
CAZ1
Offset Correction Loop Capacitor. Counterpart to CAZ2, internally connected to VEER .
—
EP
VCSEL Bias Current Output
Exposed Pad. Ground. Must be soldered to circuit board ground for proper thermal and electrical
performance (see the Exposed-Pad Package section).
Detail Description
The MAX3798 SFP+ transceiver combines a limiting
amplifier receiver with loss-of-signal detection and a
VCSEL laser driver transmitter with fault protection.
Configuration of the advanced Rx and Tx settings of the
MAX3798 is performed by a controller through the
3-wire interface. The MAX3798 provides multiple current and voltage DACs to allow the use of low-cost controller ICs.
14
Limiting Amplifier Receiver
The limiting amplifier receiver inside the MAX3798 is
designed to operate from 1.0625Gbps to 10.32Gbps.
The receiver includes a dual path limiter, offset correction circuitry, CML output stage with deemphasis, and
loss-of-signal circuitry. The functions of the receiver can
be controlled through the on-chip 3-wire interface. The
registers that control the receiver functionality are
RXCTRL1, RXCTRL2, RXSTAT, MODECTRL, SET_CML,
and SET_LOS.
______________________________________________________________________________________
1.0625Gbps to 10.32Gbps, Integrated, LowPower SFP+ Limiting Amplifier and VCSEL Driver
MAX3798
CAZ2
CAZ1
OFFSET
CORRECTION
10.32Gbps LIMITING AMPIFIER
AZ_EN
CAZX
GMEN
SLEW_RATE
RXDE_EN
0
1
0
RIN+
ROUT+
SLEW-RATE
CONTROL
ROUT-
1
RIN-
RX_POL
LOS_POL
LOS_EN
MSEL
MODE_SEL
RPULL
LOS
OUTPUT
CONTROL
LOGIC
SQ_EN
LOS
VEER
VCCD
SCL
SDA
CSEL
3-WIRE
INTERFACE
RPULL
RPULL
INTERNAL REGISTER
6b DAC SET_LOS
RPULL
CONTROL
LOGIC
8b DAC SET_CML
9b DAC SET_IMOD
9b DAC SET_IBIAS
4b DAC SET_PWCTRL
4b DAC SET_TXDE
BMON
IBIAS
BIAS
BIAS
MONITOR
IMOD
IDE
TX_POL
IVCSEL = IMOD - IDE
TOUT+
PULSEWIDTH
CONTROL
TOUT-
1
TIN+
0
TINVCCT
RPULL
FAULT
EYE SAFETY AND
OUTPUT CONTROL
TX_EN
DISABLE
POWER-ON RESET
BMAX
VCSEL BIAS
CURRENT LIMITER
MMAX
VCSEL MOD
CURRENT LIMITER
MAX3798
10.32Gbps VCSEL DRIVER
Figure 2. Functional Diagram
______________________________________________________________________________________
15
MAX3798
1.0625Gbps to 10.32Gbps, Integrated, LowPower SFP+ Limiting Amplifier and VCSEL Driver
Dual Path Limiter
The limiting amplifier features a high-gain mode and a
high-bandwidth mode allowing for overall system optimization. Either the MSEL pin or the MODE_SEL bit can
perform the mode selection. For operating up to
4.25Gbps, the high-gain mode (MODE_SEL = 0) is recommended. For operating above 8.5Gbps, the highbandwidth mode (MODE_SEL = 1) is recommended.
For operations at 8.5Gbps, the mode selection is
dependent on the performance of the receiver optical
subassembly. The polarity of ROUT+/ROUT- relative to
RIN+/RIN- is programmed by the RX_POL bit.
Offset Correction Circuitry
The offset correction circuit is enabled to remove pulsewidth distortion caused by intrinsic offset voltages within the differential amplifier stages. An external capacitor
(CAZ) connected between the CAZ1 and CAZ2 pins is
used to set the offset correction loop cutoff frequency.
The offset loop can be disabled using the AZ_EN bit.
The MAX3798 contains a feature that allows the part to
meet a 10μs mode-select switching time. The modeselect switching time can be adjusted using the GMEN
and CAZX bits.
CML Output Stage with Deemphasis and
Slew-Rate Control
The CML output stage is optimized for differential 100Ω
loads. The RXDE_EN bit adds analog deemphasis
compensation to the limited differential output signal for
SFP connector losses. The output stage is controlled by
a combination of the RX_EN and SQ_EN bits and the
LOS pin. See Table 1.
Amplitude of the CML output stage is controlled by an
8-bit DAC register (SET_CML). The differential output
amplitude range is from 40mVP-P up to 1200mVP-P with
Table 1. CML Output Stage Operation Mode
OPERATION MODE
DESCRIPTION
RX_EN
SQ_EN
LOS
0
X
X
CML output disabled.
1
0
X
CML output enabled.
1
1
0
CML output enabled.
1
1
1
CML output disabled.
16
4.6mVP-P resolution (assuming an ideal 100Ω differential load).
The lower bandwidth data path allows for reduction of
output edge speed in order to enhance EMI performance. The SLEW_RATE bit controls the slew rate of
the output stage (see Table 2).
Loss-of-Signal (LOS) Circuitry
The input data amplitude is compared to a preset
threshold controlled by the 6-bit DAC register
SET_LOS. The LOS assert level can be programmed
from 14mVP-P up to 77mVP-P with 1.5mVP-P resolution
(assuming an ideal 100Ω differential source). LOS is
enabled through the LOS_EN bit and the polarity of the
LOS is controlled with the LOS_POL bit.
VCSEL Driver
The VCSEL driver inside the MAX3798 is designed to
operate from 1.0625Gbps to 10.32Gbps. The transmitter contains a differential data path with pulse-width
adjustment, bias current and modulation current DACs,
output driver with programmable deemphasis, poweron reset circuitry, BIAS monitor, VCSEL current limiter,
and eye safety circuitry. A 3-wire digital interface is
used to control the transmitter functions. The registers
that control the transmitter functionality are TXCTRL,
TXSTAT1, TXSTAT2, SET_IBIAS, SET_IMOD, IMODMAX, IBIASMAX, MODINC, BIASINC, MODECTRL,
SET_PWCTRL, and SET_TXDE.
Differential Data Path
The CML input buffer is optimized for AC-coupled signals and is internally terminated with a differential 100Ω.
Differential input data is equalized for high-frequency
losses due to SFP connectors. The TX_POL bit in the
TXCTRL register controls the polarity of TOUT+ and
TOUT- vs. TIN+ and TIN-. The SET_PWCTRL register
Table 2. Slew-Rate Control for CML
Output Stage
OPERATION MODE
DESCRIPTION
MODE_SEL
SLEW_RATE
0
0
4.25Gbps operation with
reduced output edge speed.
0
1
4.25Gbps operation with full
edge speed; 8.5Gbps
operation with high bandwidth
ROSA.
1
X
8.5Gbps with lower bandwidth
ROSA; 10.32Gbps operation.
______________________________________________________________________________________
1.0625Gbps to 10.32Gbps, Integrated, LowPower SFP+ Limiting Amplifier and VCSEL Driver
Bias Current DAC
The bias current from the MAX3798 is optimized to provide up to 15mA of bias current into a 50Ω to 75Ω
VCSEL load with 40μA resolution. The bias current is
controlled through the 3-wire digital interface using the
SET_IBIAS, IBIASMAX, and BIASINC registers.
For VCSEL operation, the IBASMAX register is first programmed to a desired maximum bias current value (up
to 15mA). The bias current to the VCSEL then can
range from zero to the value programmed into the
IBIASMAX register. The bias current level is stored in
the 9-bit SET_IBIAS register. Only bits 1 to 8 are written
to. The LSB (bit 0) of SET_IBIAS is initialized to zero
and is updated through the BIASINC register.
The value of the SET_IBIAS DAC register is updated
when the BIASINC register is addressed through the
3-wire interface. The BIASINC register is an 8-bit register where the first 5 bits contain the increment information in two’s complement notation. Increment values
range from -8 to +7 LSBs. If the updated value of
SET_IBIAS[8:1] exceeds IBIASMAX[7:0], the IBIASERR
warning flag is set and SET_IBIAS[8:0] remains
unchanged.
Modulation Current DAC
The modulation current from the MAX3798 is optimized
to provide up to 12mA of modulation current into a
100Ω differential load with 40μA resolution. The modulation current is controlled through the 3-wire digital
interface using the SET_IMOD, IMODMAX, MODINC,
and SET_TXDE registers.
For VCSEL operation, the IMODMAX register is first programmed to a desired maximum modulation current
value (up to 12mA into a 100Ω differential load). The
modulation current to the VCSEL then can range from
zero to the value programmed into the IMODMAX register. The modulation current level is stored in the 9-bit
SET_IMOD register. Only bits 1 to 8 are written to. The
LSB (bit 0) of SET_IMOD is initialized to zero and is
updated through the MODINC register.
The value of the SET_IMOD DAC register is updated
when the MODINC register is addressed through the
3-wire interface. The MODINC register is an 8-bit register where the first 5 bits contain the increment information in two’s complement notation. Increment values
range from -8 to +7 LSBs. If the updated value of
SET_IMOD[8:1] exceeds IMODMAX[7:0], the IMODERR
warning flag is set and SET_IMOD[8:0] remains
unchanged.
Output Driver
The output driver is optimized for an AC-coupled 100Ω
differential load. The output stage also features programmable deemphasis that allows the deemphasis amplitude to be set as a percentage of the modulation current.
The deemphasis function is enabled by the TXDE_EN
bit. At initial setup the required amount of deemphasis
can be set using the SET_TXDE register. During the
system operation, it is advised to use the incremental
mode that updates the deemphasis (SET_TXDE) and
the modulation current DAC (SET_IMOD) simultaneously through the MODINC register.
Power-On Reset (POR)
Power-on reset ensures that the laser is off until supply
voltage has reached a specified threshold (2.55V).
After power-on reset, bias current and modulation current ramp up slowly to avoid an overshoot. In the case
of a POR, all registers are reset to their default values.
Bias Current Monitor
Current out of the BMON pin is typically 1/16th the
value of IBIAS. A resistor to ground at BMON sets the
voltage gain. An internal comparator latches a SOFT
FAULT if the voltage on BMON exceeds the value of
VCC - 0.55V.
VCSEL Current Limiter
To ensure an enhanced eye safety, an external analog
VCSEL current limitation can be used in addition to the
digital one. An external resistor at BMAX and MMAX
limits the maximum bias and modulation currents,
respectively. A HARD FAULT condition is latched if the
VCSEL current exceeds this threshold.
Eye Safety and Output Control Circuitry
The safety and output control circuitry contains a disable pin (DISABLE) and disable bit (TX_EN), along with
a FAULT indicator and fault detectors (Figure 3). The
MAX3798 has two types of faults, HARD FAULT and
SOFT FAULT. A HARD FAULT triggers the FAULT pin
and the output to the VCSEL is disabled. A SOFT
FAULT operates more like a warning and the outputs
are not disabled. Both types of faults are stored in the
TXSTAT1 and TXSTAT2 registers.
The FAULT pin is a latched output that can be cleared by
toggling the DISABLE pin. Toggling the DISABLE pin also
clears the TXSTAT1 and TXSTAT2 registers. A singlepoint fault can be a short to VCC or GND. Table 3 shows
the circuit response to various single-point failures.
______________________________________________________________________________________
17
MAX3798
controls the output eye-crossing adjustment. A status
indicator bit (TXED) monitors the presence of an AC
input signal.
MAX3798
1.0625Gbps to 10.32Gbps, Integrated, LowPower SFP+ Limiting Amplifier and VCSEL Driver
VCCT
FAULT REGISTER TX_STAT1
TOUT-
TOUT+
<0> FAULT
BIAS
<1>
BMAX
0.72V
IMOD
VCCT
<2>
0.8V
IBIAS
<3>
1.5V
VCCT
IBIAS
16
MMAX
FAULT REGISTER
TX_STAT1
VCC - 0.65V
<4>
<5>
VCC - 0.65V
<6>
VCC - 0.55V
BMON
<7>
VCCT
POR
POR
RESET
8kΩ
DISABLE
UNUSED
LOSS-OF-SIGNAL
CIRCUIT
WARNING REGISTER
TX_STAT2
<0>
ADDR7
<1>
TX_LOS
BIAS INCREMENT
<2>
BIASMAX
MOD INCREMENT
<3>
MODMAX
Figure 3. Eye Safety Circuitry
18
______________________________________________________________________________________
1.0625Gbps to 10.32Gbps, Integrated, LowPower SFP+ Limiting Amplifier and VCSEL Driver
PIN
NAME
1
LOS
Normal (Note 1)
SHORT TO VCC
2
MSEL
SHORT TO GND
OPEN
Normal (Note 1)
Normal (Note 1)
Normal (Note 1)
Normal (Note 1)
Normal (Note 1)
Normal
Disabled—HARD FAULT (external
Normal (Note 3)—Redundant path
supply shorted) (Note 2)
3
VCCR
4
ROUT+
Normal (Note 1)
Normal (Note 1)
Normal (Note 1)
5
ROUT-
Normal (Note 1)
Normal (Note 1)
Normal (Note 1)
6
VCCR
Normal
Disabled—HARD FAULT (external
Normal (Note 3)—Redundant path
supply shorted) (Note 2)
7
VCCD
Normal
Disabled—HARD FAULT
Disabled—HARD FAULT
Normal (Note 1). Can only be
disabled with other means.
Disabled
8
DISABLE Disabled
9
SCL
Normal (Note 1)
Normal (Note 1)
Normal (Note 1)
10
SDA
Normal (Note 1)
Normal (Note 1)
Normal (Note 1)
11
CSEL
Normal (Note 1)
Normal (Note 1)
Normal (Note 1)
Normal
Disabled—Fault (external supply
shorted) (Note 2)
Normal (Note 3)—Redundant path
12
VCCT
13
TIN+
SOFT FAULT
SOFT FAULT
Normal (Note 1)
14
TIN-
SOFT FAULT
SOFT FAULT
Normal (Note 1)
15
VCCT
Normal
Disabled—Fault (external supply
shorted) (Note 2)
Normal (Note 3)—Redundant path
16
BMON
Disabled—HARD FAULT
Normal (Note 1)
Disabled—HARD FAULT
17
VEET
Disabled—Fault (external supply
shorted) (Note 2)
Normal
Disabled—HARD FAULT
18
VCCT
Normal
Disabled—Fault (external supply
shorted) (Note 2)
Normal (Note 3)—Redundant path
19
TOUT-
IMOD is reduced
Disabled—HARD FAULT
IMOD is reduced
20
TOUT+
IMOD is reduced
Disabled—HARD FAULT
IMOD is reduced
21
VCCT
Normal
Disabled—Fault (external supply
shorted) (Note 2)
Normal (Note 3)—Redundant path
22
BIAS
IBIAS is on—No Fault
Disabled—HARD FAULT
Disabled—HARD FAULT
23
FAULT
Normal (Note 1)
Normal (Note 1)
Normal (Note 1)
24
BMAX
Normal (Note 1)
Disabled—HARD FAULT
Disabled—HARD FAULT
25
MMAX
Normal (Note 1)
Disabled—HARD FAULT
Disabled—HARD FAULT
26
VEER
Disabled—Fault (external supply
shorted) (Note 2)
Normal
Normal (Note 3)—Redundant path
27
VCCR
Normal
Disabled—HARD FAULT (external
Normal (Note 3)—Redundant path
supply shorted) (Note 2)
28
RIN-
Normal (Note 1)
Normal (Note 1)
Normal (Note 1)
29
RIN+
Normal (Note 1)
Normal (Note 1)
Normal (Note 1)
30
VCCR
Normal
Disabled—Fault (external supply
shorted) (Note 2)
Normal (Note 3)—Redundant path
______________________________________________________________________________________
19
MAX3798
Table 3. Circuit Response to Single-Point Faults
MAX3798
1.0625Gbps to 10.32Gbps, Integrated, LowPower SFP+ Limiting Amplifier and VCSEL Driver
Table 3. Circuit Response to Single-Point Faults (continued)
PIN
NAME
31
CAZ2
Normal (Note 1)
SHORT TO VCC
Normal (Note 1)
SHORT TO GND
Normal (Note 1)
OPEN
32
CAZ1
(VEER)
Disabled—Fault (external supply
shorted) (Note 2)
Normal (Note 3)—Redundant path
Normal (Note 3)—Redundant path
*Exposed pad (connected to GND).
Note 1: Normal—Does not affect laser power.
Note 2: Supply-shorted current is assumed to be primarily on the circuit board (outside this device) and the main supply is
collapsed by the short.
Note 3: Normal in functionality, but performance could be affected.
Warning: Shorted to VCC or shorted to ground on some pins can violate the Absolute Maximum Ratings.
Read Mode (RWN = 1)
The master generates 16 clock cycles at SCL in total.
The master outputs a total of 8 bits (MSB first) to the
SDA line at the falling edge of the clock. The SDA line is
released after the RWN bit has been transmitted. The
slave outputs 8 bits of data (MSB first) at the rising edge
of the clock. The master closes the transmission by setting CSEL to 0. Figure 4 shows the interface timing.
3-Wire Digital Communication
The MAX3798 implements a proprietary 3-wire digital
interface. An external controller generates the clock. The
3-wire interface consists of an SDA bidirectional data
line, an SCL clock signal input, and a CSEL chip-select
input (active high). The external master initiates a data
transfer by asserting the CSEL pin. The master starts to
generate a clock signal after the CSEL pin has been set
to 1. All data transfers are most significant bit (MSB) first.
Mode Control
Normal mode allows read-only instruction for all registers except MODINC and BIASINC. The MODINC and
BIASINC registers can be updated during normal
mode. Doing so speeds up the laser control update
through the 3-wire interface by a factor of two. The normal mode is the default mode.
Setup mode allows the master to write unrestricted data
into any register except the status (TXSTAT1, TXSTAT2,
and RXSTAT) registers. To enter the setup mode, the
MODECTRL register (address = H0x0E) must be set to
H0x12. After the MODECTRL register has been set to
H0x12, the next operation is unrestricted. The setup
mode is automatically exited after the next operation is
finished. This sequence must be repeated if further
unrestricted settings are necessary.
Protocol
Each operation consists of 16-bit transfers (15-bit
address/data, 1-bit RWN). The bus master generates
16 clock cycles to SCL. All operations transfer 8 bits to
the MAX3798. The RWN bit determines if the cycle is
read or write. See Table 4.
Register Addresses
The MAX3798 contains 17 registers available for programming. Table 5 shows the registers and addresses.
Write Mode (RWN = 0)
The master generates 16 clock cycles at SCL in total.
The master outputs a total of 16 bits (MSB first) to the
SDA line at the falling edge of the clock. The master
closes the transmission by setting CSEL to 0. Figure 4
shows the interface timing.
Table 4. Digital Communication Word Structure
BIT
15
14
13
12
11
Register Address
20
10
9
8
RWN
7
6
5
4
3
2
Data that is written or read.
______________________________________________________________________________________
1
0
1.0625Gbps to 10.32Gbps, Integrated, LowPower SFP+ Limiting Amplifier and VCSEL Driver
ADDRESS
NAME
H0x00
RXCTRL1
Receiver Control Register 1
H0x01
RXCTRL2
Receiver Control Register 2
H0x02
RXSTAT
H0x03
SET_CML
Output CML Level Setting Register
H0x04
SET_LOS
LOS Threshold Level Setting Register
H0x05
TXCTRL
Transmitter Control Register
H0x06
TXSTAT1
Transmitter Status Register 1
H0x07
TXSTAT2
Transmitter Status Register 2
H0x08
SET_IBIAS
Bias Current Setting Register
Modulation Current Setting Register
MAX3798
Table 5. Register Descriptions and Addresses
FUNCTION
Receiver Status Register
H0x09
SET_IMOD
H0x0A
IMODMAX
Maximum Modulation Current Setting Register
H0x0B
IBIASMAX
Maximum Bias Current Setting Register
H0x0C
MODINC
Modulation Current Increment Setting Register
H0x0D
BIASINC
Bias Current Increment Setting Register
H0x0E
MODECTRL
H0x0F
SET_PWCTRL
Transmitter Pulse-Width Control Register
H0x10
SET_TXDE
Transmitter Deemphasis Control Register
Mode Control Register
WRITE MODE
CSEL
tL
tT
tCH tCL
SCL
0
1
2
3
4
5
6
7
8
9
A4
A3
A2
A1
A0
RWN
D7
D6
10
11
12
13
14
15
tDS
SDA
A6
A5
D5
D4
D3
D2
D1
D0
tDH
READ MODE
CSEL
tL
tT
tCH tCL
SCL
0
1
2
3
4
5
6
7
8
9
tDS
SDA
A6
A5
A4
10
11
12
13
14
15
tD
A3
A2
A1
A0
RWN
D7
D6
D5
D4
D3
D2
D1
D0
tDH
Figure 4. Timing for 3-Wire Digital Interface
______________________________________________________________________________________
21
MAX3798
1.0625Gbps to 10.32Gbps, Integrated, LowPower SFP+ Limiting Amplifier and VCSEL Driver
Register Descriptions
Receiver Control Register 1 (RXCTRL1)
Bit #
7
6
5
4
3
2
Name
X
X
X
X
CAZX
GMEN
Default Value
X
X
X
X
1
1
1
0
MODE_SEL SLEW_RATE
0
0
ADDRESS
H0x00
Bit 3: CAZX. When CAZX is set to 0, no external capacitor is required (CAZ1 and CAZ2). When CAZX is set to 1, an
external capacitor with a minimum value of 2nF is required between CAZ1 and CAZ2.
0 = no capacitor
1 = capacitor connected
Bit 2: GMEN. Allows faster switching between data paths.
0 = disabled
1 = enabled
Bit 1: MODE_SEL. MODE_SEL combined with the MSEL pin through a logic-OR function selects between the highgain mode (1.0625Gbps to 8.5Gbps) or high-bandwidth mode (1.0625Gbps to 10.32Gbps).
Logic-OR output 0 = high-gain mode
Logic-OR output 1 = high-bandwidth mode
Bit 0: SLEW_RATE. Controls the slew rate of the output stage to reduce the effects of EMI at slower data rates.
Effective when MODE_SEL = 0 and MODE = GND only.
0 = 50ps
1 = 30ps
Receiver Control Register 2 (RXCTRL2)
Bit #
7
6
5
4
3
2
1
0
Name
X
LOS_EN
LOS_POL
RX_POL
SQ_EN
RX_EN
RXDE_EN
AZ_EN
Default Value
X
1
1
1
0
1
0
1
Bit 6: LOS_EN. Controls the LOS circuitry. When RX_EN is set to 0 the LOS detector is also disabled.
0 = disabled
1 = enabled
Bit 5: LOS_POL. Controls the output polarity of the LOS pin.
0 = inverse
1 = normal
Bit 4: RX_POL. Controls the polarity of the receiver signal path.
0 = inverse
1 = normal
Bit 3: SQ_EN: When SQ_EN = 1, the LOS controls the output circuitry.
0 = disabled
1 = enabled
22
______________________________________________________________________________________
ADDRESS
H0x01
1.0625Gbps to 10.32Gbps, Integrated, LowPower SFP+ Limiting Amplifier and VCSEL Driver
Bit 1: RXDE_EN. Enables or disables the deemphasis on the receiver output.
0 = disabled
1 = enabled
Bit 0: AZ_EN. Enables or disables the autozero circuitry. When RX_EN is set to 0, the autozero circuitry is also disabled.
0 = disabled
1 = enabled
Receiver Status Register (RXSTAT)
Bit #
7
6
5
4
3
2
1
0
(STICKY)
Name
X
X
X
X
X
X
X
LOS
Default Value
X
X
X
X
X
X
X
X
ADDRESS
H0x02
Bit 0: LOS. Copy of the LOS output circuitry. This is a sticky bit, which means that it is cleared on a read. The first 0to-1 transition gets latched until the bit is read by the master or POR occurs.
Output CML Level Setting Register (SET_CML)
Bit #
Name
Default Value
7
6
5
4
3
2
1
0
SET_CML[0]
SET_CML[7]
SET_CML[6] SET_CML[5] SET_CML[4] SET_CML[3] SET_CML[2] SET_CML[1]
(LSB)
(MSB)
0
1
0
1
0
0
1
ADDRESS
H0x03
1
Bits 7 to 0: SET_CML[7:0]. The SET_CML register is an 8-bit register that can be set to range from 0 to 255, corresponding from 40mVP-P to 1200mVP-P. See the Typical Operating Characteristics section for a typical CML output
voltage vs. DAC code graph.
LOS Threshold Level Setting Register (SET_LOS)
Bit #
7
6
5
4
3
2
1
0
ADDRESS
Name
X
X
SET_LOS[5]
(MSB)
SET_LOS[4]
SET_LOS[3]
SET_LOS[2]
SET_LOS[1]
SET_LOS[0]
(LSB)
H0x04
Default Value
X
X
0
0
1
1
1
0
Bits 5 to 0: SET_LOS[5:0]. The SET_LOS register is a 6-bit register used to program the LOS threshold. See the
Typical Operating Characteristics section for a typical LOS threshold voltage vs. DAC code graph.
______________________________________________________________________________________
23
MAX3798
Bit 2: RX_EN. Enables or disables the receive circuitry.
0 = disabled
1 = enabled
MAX3798
1.0625Gbps to 10.32Gbps, Integrated, LowPower SFP+ Limiting Amplifier and VCSEL Driver
Transmitter Control Register (TXCTRL)
Bit #
7
6
5
4
3
2
1
0
Name
X
X
X
X
TXDE_EN
SOFTRES
TX_POL
TX_EN
Default Value
X
X
X
X
0
0
1
1
ADDRESS
H0x05
Bit 3: TXDE_EN. Enables or disables the transmit output deemphasis circuitry.
0 = disabled
1 = enabled
Bit 2: SOFTRES. Resets all registers to their default values.
0 = normal
1 = reset
Bit 1: TX_POL. Controls the polarity of the transmit signal path.
0 = inverse
1 = normal
Bit 0: TX_EN. Enables or disables the transmit circuitry.
0 = disabled
1 = enabled
Transmitter Status Register 1 (TXSTAT1)
Bit #
7
(STICKY)
6
(STICKY)
5
(STICKY)
4
(STICKY)
3
(STICKY)
2
(STICKY)
1
(STICKY)
0
(STICKY)
Name
FST[7]
FST[6]
FST[5]
FST[5]
FST[3]
FST[2]
FST[1]
TX_FAULT
X
X
X
X
X
X
X
X
Default Value
ADDRESS
H0x06
Bit 7: FST[7]. When the VCCT supply voltage is below 2.45V, the POR circuitry reports a FAULT. Once the VCCT
supply voltage is above 2.55V, the POR resets all registers to their default values and the FAULT is cleared.
Bit 6: FST[6]. When the voltage at BMON is above VCC - 0.55V, a SOFT FAULT is reported.
Bit 5: FST[5]. When the voltage at MMAX goes below VCC - 0.65V, a HARD FAULT is reported.
Bit 4: FST[4]. When the voltage at BMAX goes below VCC - 0.65V, a HARD FAULT is reported.
Bit 3: FST[3]. When the common-mode voltage at VTOUT+/- goes below 1.5V, a SOFT FAULT is reported.
Bit 2: FST[2]. When the voltage at VTOUT+/- goes below 0.8V, a HARD FAULT is reported.
Bit 1: FST[1]. When the BIAS voltage goes below 0.44V, a HARD FAULT is reported.
Bit 0: TX_FAULT. Copy of a FAULT signal in FST[7] to FST[1]. A POR resets FST[7:1] to 0.
Transmitter Status Register 2 (TXSTAT2)
Bit #
7
6
5
4
3
(STICKY)
2
(STICKY)
1
(STICKY)
0
(STICKY)
Name
X
X
X
X
IMODERR
IBIASERR
TXED
X
Default Value
X
X
X
X
X
X
X
X
ADDRESS
H0x07
Bit 3: IMODERR. When the modulation-incremented result is greater than IMODMAX, a SOFT FAULT is reported.
(See the Programming Modulation Current section.)
24
______________________________________________________________________________________
1.0625Gbps to 10.32Gbps, Integrated, LowPower SFP+ Limiting Amplifier and VCSEL Driver
Bias Current Setting Register (SET_IBIAS)
Bit #
Name
Default Value
7
6
5
4
3
SET_IBIAS SET_IBIAS SET_IBIAS SET_IBIAS SET_IBIAS
[8] (MSB)
[7]
[6]
[5]
[4]
0
0
0
0
0
2
1
0
SET_IBIAS SET_IBIAS SET_IBIAS
[3]
[2]
[1]
1
0
ADDRESS
H0x08
0
Bits 7 to 0: SET_IBIAS[8:1]. The bias current DAC is controlled by a total of 9 bits. The SET_IBIAS[8:1] bits are
used to set the bias current with even denominations from 0 to 510 bits. The LSB (SET_IBIAS[0]) bit is controlled by
the BIASINC register and is used to set the odd denominations in the SET_IBIAS[8:0].
Modulation Current Setting Register (SET_IMOD)
Bit #
Name
Default Value
7
6
5
4
3
2
1
0
SET_IMOD SET_IMOD SET_IMOD SET_IMOD SET_IMOD SET_IMOD SET_IMOD SET_IMOD
[8] (MSB)
[7]
[6]
[5]
[4]
[3]
[2]
[1]
0
0
0
1
0
0
1
ADDRESS
H0x09
0
Bits 7 to 0: SET_IMOD[8:1]. The modulation current DAC is controlled by a total of 9 bits. The SET_IMOD[8:1] bits
are used to set the modulation current with even denominations from 0 to 510 bits. The LSB (SET_IMOD[0]) bit is
controlled by the MODINC register and is used to set the odd denominations in the SET_IMOD[8:0].
Maximum Modulation Current Setting Register (IMODMAX)
Bit #
7
6
5
4
3
2
1
0
ADDRESS
Name
IMODMAX
[7] (MSB)
IMODMAX
[6]
IMODMAX
[5]
IMODMAX
[4]
IMODMAX
[3]
IMODMAX
[2]
IMODMAX
[1]
IMODMAX
[0] (LSB)
H0x0A
0
0
1
1
0
0
0
0
Default Value
Bits 7 to 0: IMODMAX[7:0]. The IMODMAX register is an 8-bit register that can be used to limit the maximum modulation current. IMODMAX[7:0] is continuously compared to the SET_IMOD[8:1].
Maximum Bias Current Setting Register (IBIASMAX)
Bit #
7
6
5
4
3
2
1
0
ADDRESS
Name
IBIASMAX
[7] (MSB)
IBIASMAX
[6]
IBIASMAX
[5]
IBIASMAX
[4]
IBIASMAX
[3]
IBIASMAX
[2]
IBIASMAX
[1]
IBIASMAX
[0] (LSB)
H0x0B
0
0
0
1
0
0
1
0
Default Value
Bits 7 to 0: IBIASMAX[7:0]. The IBIASMAX register is an 8-bit register that can be used to limit the maximum bias
current. IBIASMAX[7:0] is continuously compared to the SET_IBAS[8:1].
______________________________________________________________________________________
25
MAX3798
Bit 2: IBIASERR. When the bias incremented result is greater than IBIASMAX, then a SOFT FAULT is reported. (See
the Programming Bias Current section.)
Bit 1: TXED. This only indicates the absence of an AC signal at the transmit input. This is not an LOS indicator.
MAX3798
1.0625Gbps to 10.32Gbps, Integrated, LowPower SFP+ Limiting Amplifier and VCSEL Driver
Modulation Current Increment Setting Register (MODINC)
Bit #
7
6
5
Name
SET_IMOD
[0]
X
DE_INC
0
0
0
Default Value
4
3
2
1
0
MODINC[0]
MODINC[4]
MODINC[3] MODINC[2] MODINC[1]
(LSB)
(MSB)
0
0
0
0
ADDRESS
H0x0C
0
Bit 7: SET_IMOD[0]. This is the LSB of the SET_IMOD[8:0] bits. This bit can only be updated by the use of
MODINC[4:0].
Bit 5: DE_INC. When this bit is set to 1 and the deemphasis on the transmit output is enabled, the SET_TXDE[3:0] is
incremented or decremented by 1 LSB. The increment or decrement is determined by the sign bit of the MODINC[4:0]
string of bits.
Bits 4 to 0: MODINC[4:0]. This string of bits is used to increment or decrement the modulation current. When written
to, the SET_IMOD[8:0] bits are updated. MODINC[4:0] are a two’s complement string.
Bias Current Increment Setting Register (BIASINC)
Bit #
7
Name
SET_IBIAS
[0]
X
X
0
0
0
Default Value
6
5
4
3
2
1
0
BIASINC[0]
BIASINC[4]
BIASINC[3] BIASINC[2] BIASINC[1]
(LSB)
(MSB)
0
0
0
0
ADDRESS
H0x0D
0
Bit 7: SET_IBIAS[0]. This is the LSB of the SET_IBIAS[8:0] bits. This bit can only be updated by the use of BIASINC[4:0].
Bits 4 to 0: BIASINC[4:0]. This string of bits is used to increment or decrement the bias current. When written to, the
SET_IBIAS[8:0] bits are updated. BIASINC[4:0] are a two’s complement string.
Mode Control Register (MODECTRL)
Bit #
7
Name
Default Value
6
5
4
3
2
1
0
MODECTRL MODECTRL MODECTRL MODECTRL MODECTRL MODECTRL MODECTRL MODECTRL
[7] MSB)
[6]
[5]
[4]
[3]
[2]
[1]
[0] (LSB)
0
0
0
0
0
0
0
ADDRESS
H0x0E
0
Bits 7 to 0: MODECTRL[7:0]. The MODECTRL register enables a switch between normal and setup modes. The
setup mode is achieved by setting this register to H0x12. MODECTRL must be updated before each write operation.
Exceptions are MODINC and BIASINC, which can be updated in normal mode.
Transmitter Pulse-Width Control Register (SET_PWCTRL)
Bit #
7
6
5
4
Name
X
X
X
X
Default Value
X
X
X
X
3
2
1
0
SET_
SET_
SET_
SET_
PWCTRL[3]
PWCTRL[0]
PWCTRL[2] PWCTRL[1]
(MSB)
(LSB)
0
0
0
ADDRESS
H0x0F
0
Bits 3 to 0: SET_PWCTRL[3:0]. This is a 4-bit register used to control the eye crossing by adjusting the pulse width.
26
______________________________________________________________________________________
1.0625Gbps to 10.32Gbps, Integrated, LowPower SFP+ Limiting Amplifier and VCSEL Driver
Bit #
7
6
5
4
3
2
1
0
ADDRESS
Name
X
X
X
X
SET_TXDE
[3] (MSB)
SET_TXDE
[2]
SET_TXDE
[1]
SET_TXDE
[0] (LSB)
H0x10
Default Value
X
X
X
X
0
0
0
0
Bits 3 to 0: SET_TXDE[3:0]. This is a 4-bit register used to control the amount of deemphasis on the transmitter output. When calculating the total modulation current, the amount of deemphasis must be taken into account. The
deemphasis is set as a percentage of modulation current.
Design Procedure
Programming Bias Current
1) IBIASMAX[7:0] = Maximum_Bias_Current_Value
2) SET_IBIASi[8:1] = Initial_Bias_Current_Value
Note: The total bias current value is calculated using
the SET_IBIAS[8:0] register. SET_IBIAS[8:1] are the bits
that can be manually written. SET_IBIAS[0] can only be
updated using the BIASINC[7:0] register.
When implementing an APC loop it is recommended to
use the BIASINC[7:0] register, which guarantees the
fastest bias current update.
3) BIASINCi[4:0] = New_Increment_Value
4) If (SET_IBIASi[8:1] ≤ IBIASMAX[7:0]),
then (SET_IBIASi[8:0] = SET_IBIASi-1[8:0] + BIASINCi[4:0])
5) Else (SET_IBIASi[8:0] = SET_IBIASi-1[8:0])
The total bias current can be calculated as follows:
6) IBIAS = [SET_IBIASi[8:0] + 20] x 40μA
Programming Modulation Current
1) IMODMAX[7:0] = Maximum_Modulation_Current_Value
2) SET_IMODi[8:1] = Initial_Modulation_Current_Value
Note: The total modulation current value is calculated
using the SET_IMOD[8:0] register. SET_IMOD[8:1] are
the bits that can be manually written. SET_IMOD[0] can
only be updated using the MODINC[7:0] register.
When implementing modulation compensation, it is recommended to use the MODINC[7:0] register, which
guarantees the fastest bias current update.
3) MODINCi[4:0] = New_Increment_Value
4) If (SET_IMODi[8:1] ≤ IMODMAX[7:0]),
then (SET_IMODi[8:0] = SET_IMODi-1[8:0] + MODINCi[4:0])
5) Else (SET_IMODi[8:0] = SET_IMODi-1[8:0])
The following equation is valid with assumption of 100Ω
on-chip and 100Ω external differential load (Rextd). The
maximum value that can be set for SET_TXDE[3:0] = 11.
6)
IMOD(Rextd=100Ω) = [(20 + SET_IMODi[8:0]) x 40μA]
2 + SET _ TXDE[3 : 0] ⎤
⎡
× ⎢1 −
⎥
64
⎣
⎦
For general Rextd, the modulation current that is
achieved using the same setting of SET_IMODi[8:0] as
for Rextd = 100Ω is shown below. It can be written as a
function of IMOD(Rextd=100Ω), still assuming a 100Ω onchip load.
⎡ Re xt
⎤
7) IMOD(Re xtd) = 2 × IMOD (Re xtd=100Ω) ⎢
⎥
⎣ Re xt + 100 ⎦
Programming LOS Threshold
LOSTH = (SET_LOS[7:0] x 1.5mVP-P)
Programming Transmit Output
Deemphasis
The TXDE_EN bit must be set to 1 to enable the deemphasis function. The SET_TXDE register value is used
to set the amount of deemphasis, which is a percentage of the modulation current. Deemphasis percentage
is determined as:
DE(%) =
100 × ( 2 + SET _ TXDE[3 : 0] )
64
Where the maximum SET_TXDE[3:0] = 11.
For an IMOD value of 10mA, the maximum achievable
deemphasis value is approximately 20%. Maximum
deemphasis achievable for full IMOD range of 12mA is
limited to 15%.
With deemphasis enabled, the value of the modulation
current amplitude is reduced by the calculated deemphasis percentage. To maintain the modulation current
amplitude constant, the SET_IMOD[8:0] register must
be increased by the deemphasis percentage. If the system conditions like temperature, required IMOD value,
etc., change during the transmit operation, the deemphasis setting might need to be readjusted. For such an
______________________________________________________________________________________
27
MAX3798
Transmitter Deemphasis Control Register (SET_TXDE)
MAX3798
1.0625Gbps to 10.32Gbps, Integrated, LowPower SFP+ Limiting Amplifier and VCSEL Driver
impromptu deemphasis adjustment, it is recommended
that the DE_INC (MODINC[5]) bit is used. Use of this bit
increments or decrements the deemphasis code setting
by 1 LSB based on the sign of increment in the
MODINC[4:0] and, hence, the SET_IMOD[8:0] setting.
This helps maintain the BER while having the flexibility to
improve signal quality by adjusting deemphasis while
the transmit operation continues. This feature enables
glitchless deemphasis adjustment while maintaining
excellent BER performance.
Programming Pulse-Width Control
The eye crossing at the Tx output can be adjusted
using the SET_PWCTRL register. Table 6 shows these
settings.
The sign of the number specifies the direction of pulsewidth distortion. The code of 1111 corresponds to a
balanced state for differential output. The pulse-width
distortion is bidirectional around the balanced state
(see the Typical Operating Characteristics section).
Table 6. Eye-Crossing Settings for
SET_PWCRTL
SET_PWCRTL[3:0]
PWD
SET_PWCRTL[3:0]
PWD
1000
-7
0111
8
1001
-6
0110
7
1010
-5
0101
6
1011
-4
0100
5
1100
-3
0011
4
1101
-2
0010
3
1110
-1
0001
2
1111
0
0000
1
Programming CML Output Settings
Amplitude of the CML output stage is controlled by an
8-bit DAC register (SET_CML). The differential output
amplitude range is from 40mVP-P up to 1200mVP-P with
4.6mVP-P resolution (assuming an ideal 100Ω differential load).
Output Voltage ROUT (mVP-P) = 40 + 4.55 (SET_CML)
Select the Coupling Capacitor
For AC-coupling, the coupling capacitors C IN and
COUT should be selected to minimize the receiver’s
28
deterministic jitter. Jitter is decreased as the input lowfrequency cutoff (fIN) is decreased.
fIN = 1/[2π(50)(CIN)]
The recommended C IN and C OUT is 0.1μF for the
MAX3798.
Select the Offset-Correction Capacitor
The capacitor between CAZ1 and CAZ2 determines the
time constant of the signal path DC-offset cancellation
loop. To maintain stability, it is important to keep at
least a one-decade separation between fIN and the
low-frequency cutoff (fOC) associated with the DC-offset cancellation circuit. A 1nF capacitor between CAZ1
and CAZ2 is recommended for the MAX3798.
Applications Information
Layout Considerations
To minimize inductance, keep the connections between
the MAX3798 output pins and laser diode as close as
possible. Optimize the laser diode performance by
placing a bypass capacitor as close as possible to the
laser anode. Use good high-frequency layout techniques and multiple-layer boards with uninterrupted
ground planes to minimize EMI and crosstalk.
Exposed-Pad Package
The exposed pad on the 32-pin TQFN provides a very
low-thermal resistance path for heat removal from the IC.
The pad is also electrical ground on the MAX3798 and
must be soldered to the circuit board ground for proper
thermal and electrical performance. Refer to Application
Note 862: HFAN-08.1: Thermal Considerations of QFN
and Other Exposed-Paddle Packages for additional
information.
Laser Safety and IEC 825
Using the MAX3798 laser driver alone does not ensure
that a transmitter design is compliant with IEC 825. The
entire transmitter circuit and component selections
must be considered. Each user must determine the
level of fault tolerance required by the application, recognizing that Maxim products are neither designed nor
authorized for use as components in systems intended
for surgical implant into the body, for applications
intended to support or sustain life, or for any other
application in which the failure of a Maxim product
could create a situation where personal injury or death
could occur.
______________________________________________________________________________________
1.0625Gbps to 10.32Gbps, Integrated, LowPower SFP+ Limiting Amplifier and VCSEL Driver
REGISTER
FUNCTION/
ADDRESS
Receiver Control
Register 1
Address = H0x00
Receiver Control
Register 2
Address = H0x01
Receiver Status
Register
Address = H0x02
Output CML Level
Setting Register
Address = H0x03
REGISTER
NAME
NORMAL
MODE
SETUP
MODE
BIT
NUMBER
/TYPE
BIT NAME
DEFAULT
VALUE
NOTES
R
RW
3
CAZX
1
External autozero capacitor
0: disconnected, 1:
connected
R
RW
2
GMEN
1
Mode-select switching time
boost
0: off, 1: on
R
RW
1
MODE_SEL
0
Mode-select
0: high-gain mode, 1: highbandwidth mode
R
RW
0
SLEW_RATE
0
Slew-rate select
0: slow mode, 1: fast mode
R
RW
6
LOS_EN
1
LOS control
0: disable, 1: enable
(always 0 when RX_EN = 0)
R
RW
5
LOS_POL
1
LOS polarity
0: inverse, 1: normal
R
RW
4
RX_POL
1
Rx polarity
0: inverse, 1: normal
R
RW
3
SQ_EN
0
Squelch
0: disable, 1: enable
R
RW
2
RX_EN
1
Rx control
0: disable, 1: enable
R
RW
1
RXDE_EN
0
Rx deemphasis
0: disable, 1: enable
R
RW
0
AZ_EN
1
Rx autozero control
0: disable, 1: enable
(always 0 when RX_EN = 0)
R
R
0 (sticky)
LOS
X
Copy of LOS output signal
MSB output level DAC
RXCTRL1
RXCTRL2
RXSTAT
SET_CML
R
RW
7
SET_CML[7]
0
R
RW
6
SET_CML[6]
1
R
RW
5
SET_CML[5]
0
R
RW
4
SET_CML[4]
1
R
RW
3
SET_CML[3]
0
R
RW
2
SET_CML[2]
0
R
RW
1
SET_CML[1]
1
R
RW
0
SET_CML[0]
1
LSB output level DAC
______________________________________________________________________________________
29
MAX3798
Table 7. Register Summary
MAX3798
1.0625Gbps to 10.32Gbps, Integrated, LowPower SFP+ Limiting Amplifier and VCSEL Driver
Table 7. Register Summary (continued)
REGISTER
FUNCTION/
ADDRESS
LOS Threshold
Level Setting
Register
Address = H0x04
Transmitter
Control Register
Address = H0x05
Transmitter Status
Register 1
Address = H0x06
Transmitter Status
Register 2
Address = H0x07
30
REGISTER
NAME
SET_LOS
TXCTRL
NORMAL
MODE
SETUP
MODE
BIT
NUMBER
/TYPE
BIT NAME
DEFAULT
VALUE
R
RW
5
SET_LOS[5]
0
R
RW
4
SET_LOS[4]
0
R
RW
3
SET_LOS[3]
1
R
RW
2
SET_LOS[2]
1
R
RW
1
SET_LOS[1]
0
R
RW
0
SET_LOS[0]
0
LSB LOS threshold DAC
Tx deemphasis
0: disable, 1: enable
MSB LOS threshold DAC
R
RW
3
TXDE_EN
0
R
RW
2
SOFTRES
0
Global digital reset
R
RW
1
TX_POL
1
Tx polarity
0: inverse, 1: normal
R
RW
0
TX_EN
1
Tx control
0: disable, 1: enable
R
R
7 (sticky)
FST[7]
X
TX_POR TX_VCC lowlimit violation
R
R
6 (sticky)
FST[6]
X
BMON open/shorted to VCC
R
R
5 (sticky)
FST[5]
X
MMAX current exceeded or
open/shorted to GND
R
R
4 (sticky)
FST[4]
X
BMAX current exceeded or
open/shorted to GND
R
R
3 (sticky)
FST3]
X
VTOUT+/- common-mode
low-limit violation
R
R
2 (sticky)
FST[2]
X
VTOUT+/- low-limit violation
R
R
1 (sticky)
FST[1]
X
BIAS open or shorted to GND
R
R
0 (sticky)
TX_FAULT
X
Copy of FAULT signal in
case POR bits 6 to 1 reset
to 0
R
R
3 (sticky)
IMODERR
X
Warning increment result >
IMODMAX
R
R
2 (sticky)
IBIASERR
X
Warning increment result >
IBIASMAX
R
R
1 (sticky)
TXED
X
Tx edge detection
R
R
0 (sticky)
Unused
X
Unused
TXSTAT1
TXSTAT2
NOTES
______________________________________________________________________________________
1.0625Gbps to 10.32Gbps, Integrated, LowPower SFP+ Limiting Amplifier and VCSEL Driver
REGISTER
FUNCTION/
ADDRESS
Bias Current
Setting Register
Address = H0x08
REGISTER
NAME
SET_IBIAS
NORMAL
MODE
SETUP
MODE
SET_IMOD
Maximum Bias
Current Setting
Register
Address = H0x0B
IMODMAX
IBIASMAX
DEFAULT
VALUE
NOTES
RW
8
SET_IBIAS[8]
0
R
RW
7
SET_IBIAS[7]
0
R
RW
6
SET_IBIAS[6]
0
R
RW
5
SET_IBIAS[5]
0
R
RW
4
SET_IBIAS[4]
0
R
RW
3
SET_IBIAS[3]
1
R
RW
2
SET_IBIAS[2]
0
R
RW
1
SET_IBIAS[1]
0
0
SET_IBIAS[0]
0
LSB bias DAC
MSB bias DAC
MSB modulation DAC
R
RW
8
SET_IMOD[8]
0
R
RW
7
SET_IMOD[7]
0
R
RW
6
SET_IMOD[6]
0
R
RW
5
SET_IMOD[5]
1
R
RW
4
SET_IMOD[4]
0
R
RW
3
SET_IMOD[3]
0
R
RW
2
SET_IMOD[2]
1
R
RW
1
SET_IMOD[1]
0
0
SET_IMOD[0]
0
LSB modulation DAC
MSB modulation limit
Accessible through
REG_ADDR = 12
Maximum
Modulation
Current Setting
Register
Address = H0x0A
BIT NAME
R
Accessible through
REG_ADDR = 13
Modulation
Current Setting
Register
Address = H0x09
BIT
NUMBER
/TYPE
MAX3798
Table 7. Register Summary (continued)
R
RW
7
IMODMAX[7]
0
R
RW
6
IMODMAX[6]
0
R
RW
5
IMODMAX[5]
1
R
RW
4
IMODMAX[4]
1
R
RW
3
IMODMAX[3]
0
R
RW
2
IMODMAX[2]
0
R
RW
1
IMODMAX[1]
0
R
RW
0
IMODMAX[0]
0
LSB modulation limit
R
RW
7
IBIASMAX[7]
0
MSB bias limit
R
RW
6
IBIASMAX[6]
0
R
RW
5
IBIASMAX[5]
0
R
RW
4
IBIASMAX[4]
1
R
RW
3
IBIASMAX[3]
0
R
RW
2
IBIASMAX[2]
0
R
RW
1
IBIASMAX[1]
1
R
RW
0
IBIASMAX[0]
0
LSB bias limit
______________________________________________________________________________________
31
MAX3798
1.0625Gbps to 10.32Gbps, Integrated, LowPower SFP+ Limiting Amplifier and VCSEL Driver
Table 7. Register Summary (continued)
REGISTER
FUNCTION/
ADDRESS
Modulation
Current Increment
Setting Register
Address = H0x0C
Bias Current
Increment Setting
Register
Address = H0x0D
Mode Control
Register
Address = H0x0E
Transmitter PulseWidth Control
Register
Address = H0x0F
Transmitter
Deemphasis
Control Register
Address = H0x10
32
REGISTER
NAME
MODINC
BIASINC
MODECTRL
SET_
PWCTRL
SET_TXDE
NORMAL
MODE
SETUP
MODE
BIT
NUMBER
/TYPE
BIT NAME
DEFAULT
VALUE
R
R
7
SET_IMOD[0]
0
R
R
6
X
0
R
R
5
DE_INC
0
Deemphasis increment
0: no update, 1: SET_TXDE
updates ±1 LSB
RW
RW
4
MODINC[4]
0
MSB MOD DAC two’s
complement
RW
RW
3
MODINC[3]
0
RW
RW
2
MODINC[2]
0
RW
RW
1
MODINC[1]
0
RW
RW
0
MODINC[0]
0
LSB MOD DAC two’s
complement
R
R
7
SET_IBIAS[0]
0
LSB of SET_IBIAS DAC
register address = H0x08
R
R
6
X
0
R
R
5
X
0
RW
RW
4
BIASINC[4]
0
RW
RW
3
BIASINC[3]
0
RW
RW
2
BIASINC[2]
0
RW
RW
1
BIASINC[1]
0
RW
RW
0
BIASINC[0]
0
LSB bias DAC two’s
complement
RW
RW
7
MODECTRL[7]
0
MSB mode control
RW
RW
6
MODECTRL[6]
0
RW
RW
5
MODECTRL[5]
0
RW
RW
4
MODECTRL[4]
0
RW
RW
3
MODECTRL[3]
0
RW
RW
2
MODECTRL[2]
0
RW
RW
1
MODECTRL[1]
0
RW
RW
0
MODECTRL[0]
0
LSB mode control
R
RW
3
SET_PWCTRL[3]
0
MSB Tx pulse-width control
R
RW
2
SET_PWCTRL[2]
0
R
RW
1
SET_PWCTRL[1]
0
R
RW
0
SET_PWCTRL[0]
0
LSB Tx pulse-width control
MSB Tx deemphasis
R
RW
3
SET_TXDE[3]
0
R
RW
2
SET_TXDE[2]
0
R
RW
1
SET_TXDE[1]
0
R
RW
0
SET_TXDE[0]
0
NOTES
LSB of SET_IMOD DAC
register address = H0x09
MSB bias DAC two’s
complement
LSB Tx deemphasis
______________________________________________________________________________________
1.0625Gbps to 10.32Gbps, Integrated, LowPower SFP+ Limiting Amplifier and VCSEL Driver
MAX3798
VCCR
VCCR
DEEMPHASIS
CONTROL
50Ω
50Ω
ROUT+
RIN+
ROUT50Ω
CONTROL
LOOP
50Ω
RIN-
VEER
VEER
VCCT
VCCT
DEEMPHASIS
CONTROL
50Ω
50Ω
TOUT+
TIN+
TOUT50Ω
CONTROL
LOOP
50Ω
TIN-
VCCT
VCCD
VEET
VEET
8kΩ
75kΩ
SDA
DISABLE
VEET
VCCR
VCCD
VEED
FAULT, LOS
376Ω
CLAMP
MSEL
SCL, CSEL
75kΩ
75kΩ
VEET
VEER
VEED
Figure 5. Simplified I/O Structures
______________________________________________________________________________________
33
1.0625Gbps to 10.32Gbps, Integrated, LowPower SFP+ Limiting Amplifier and VCSEL Driver
MAX3798
Typical Application Circuit
SFP
CONNECTOR
SFP OPTICAL TRANSCEIVER
+3.3V
SUPPLY
FILTER
HOST BOARD
HOST
FILTER
VCC_RX
+3.3V
1nF
CAZ2
CAZ1
VEER
RIN+
VCCR
4.7Ω
0.1μF
LOS
0.1μF
RINIMON
ROUT+
0.1μF
RECEIVER
ROUT0.1μF
10G PIN FLEX ROSA
+3.3V
RMON
MSEL
+3.3V
VCCD
SCL
SDA
CSEL
SERDES
10G VCSEL FLEX TOSA
ZDIFF = 100Ω
3-WIRE
INTERFACE
VCCT
BIAS
MAX3798
0.1μF
VSEL
0.1μF
TOUT-
TIN+
0.1μF
TOUT+
MD
TRANSMITTER
TIN0.1μF
400Ω
ZDIFF = 100Ω
MMAX
+3.3V
400Ω
DISABLE
EP
FAULT
BMON
VEET
BMAX
+3.3V
4.7Ω
IMON
3-WIRE
INTERFACE
ADC
TX_FAULT
SFP+
CONTROLLER
I2C
MODE_DEF2 (SD)
MODE_DEF1 (SCLK)
TX_DISABLE
RPD
2kΩ
VCC_TX
SUPPLY
FILTER
34
HOST
FILTER
______________________________________________________________________________________
1.0625Gbps to 10.32Gbps, Integrated, LowPower SFP+ Limiting Amplifier and VCSEL Driver
Chip Information
24
23
21
20
19
18
Package Information
VEET
VCCT
TOUT-
TOUT+
BIAS
22
VCCT
FAULT
BMAX
PROCESS: SiGe BiPOLAR
TOP VIEW
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages.
17
MMAX 25
16
BMON
VEER 26
15
VCCT
VCCR 27
RIN- 28
MAX3798
RIN+ 29
VCCR 30
CAZ2 31
*EP
+
6
7
8
VCCR
DISABLE
5
VCCD
4
ROUT-
MSEL
3
VCCR
2
ROUT+
1
LOS
CAZ1 32
14
TIN-
13
TIN+
12
VCCT
11
CSEL
10
SDA
9
SCL
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
32 TQFN-EP
T3255+3
21-0140
THIN QFN
(5mm × 5mm)
*THE EXPOSED PAD MUST BE CONNECTED TO GROUND.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 35
© 2008 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
MAX3798
Pin Configuration