Sitronix 矽創電子股份有限公司 SITRONIX CORPORATION 1/9 ST20P18 based on 21xx EV-BOARD descriptions A、 、4 Jumpers,1 cutter and 1 short for Hardware descriptions B、 、The pin define descriptions In EVB and daughter Board C、 、Return to the original 21xx EVB condition descriptions D、 、ST20P18 Demo board with read IC descriptions Fig.1 pin locations A、 、4 Jumpers, 1 cutter and 1 short for ST20P18 descriptions Hardware setup STEP1: Header Name U11 U5 U3 U12 U11 J12 Pin Location 40 24 10 19 40 9 Pin Name w65c02resb --STOPB w65c02resb cpureset Jumper Jumper Jumper Jumper Cutter Short Header Name J12 J19 J19 J19 J1 J12 Pin Location 10 2 3 4 2 10 Pin Name w65c02resb ---sysresetb w65c02resb Sitronix 矽創電子股份有限公司 SITRONIX CORPORATION 4 Jumpers， ， 1 cutter and 1 short figure descriptions Fig. 2 4 Jumpers descriptions Fig. 3 1 cutter and 1 short 2/9 Sitronix 矽創電子股份有限公司 SITRONIX CORPORATION Fig. 4 1 cutter zoom in Fig. 5 1 short zoom in 3/9 Sitronix 矽創電子股份有限公司 SITRONIX CORPORATION STEP2: ST20P18 daughter board with LCD EV-chip function connect to 21xx EVB Fig. 6 Daughter board with connect with 21xx EV-Board cross-sectional view Fig. 7 hardware setup finish 4/9 Sitronix 矽創電子股份有限公司 SITRONIX CORPORATION 5/9 Note: 1.In Fig.6，the blue line means WDTEN of J4 first pin need to connect with GND and it will be disable WDT(Real IC is Option Word) ,and WDT reset doesn’t occur ，if you want to use WDT function， please leave it floating. 2.yellow line is daughter board power ，please connect to 21xx FPGA VDD=3V. 3.ST20P18 and ST2016A/B Program ROM can choice EPROM or ROM Emulator ， in memory arrange，the Program ROM is $C000 ~ $FFFF ，and mapping to E.V.B address is $4000 ~$7FFF ， when use Program ROM with assembler and linker；the HEX file need to transfer to Binary file and OFFSET value is 0800 。 Example ：HEXBIN2 filename.hex filename.bin I 0800 FFFF Sitronix 矽創電子股份有限公司 SITRONIX CORPORATION B ：The pin define descriptions in EVB and daughter Board Fig. 8 EVB pin descriptions In Fig. 9 ，pin defines as below： J2：PA0~7, PB0~7, PC0~7 J4：Pin123 separately simulate pin option WDTEN, WDTSTP, PWRTEN. J7：pin3, 4 is simulation pin option PD [0~1] J9：Pin [2~5] is simulation COM [0~3] output port J12：pin7=>PSGO，pin8=> PSGOB；Pin9 short to pin10 is simulation reset CPU 6/9 Sitronix 矽創電子股份有限公司 SITRONIX CORPORATION 7/9 J4 RFC capacitors U2 JP1~JP5 RFC 4SENSORS J5 U1 ST2016/ST20P18 LCD-EV CHIP J11 Fig. 10 daughter pin descriptions In Fig. 10 pin define as below: J4：FPE0~3=>FPGA simulates PE[0~3] J4：FSEG4~23=> FPGA simulates SEGMENT [4~23] output PORT J4：FCOM4~7=> FPGA simulates COMMON [4~7] output PORT J5：Power=>LCD Daughter Board connect to FPGA VDD=3V JP1~JP5：OPEN =>RFC function simulate in FPGA J11：LCD waveform signal COM [0~7], SEG [0~39] U1：CD40106BE=>Schmitt trigger simulate in FPGA U2：74HC125=> TRI-STATE BUFFER simulate in FPGA Sitronix 矽創電子股份有限公司 SITRONIX CORPORATION C、 、Return to the original 21xx EVB condition descriptions Fig. 11 Return to the original 21xx EVB J12 ：pin9, pin10 open. J12 ：Pin 10 connect to J1 pin2 and it will reset all. Change BIOS for 21xx-EVB 8/9 Sitronix 矽創電子股份有限公司 SITRONIX CORPORATION 9/9 D、 、ST20P18 Demo board with read IC descriptions J7:PWRT RFC capacitor RFC 4SENSORS U1 JP1~JP5 J5 J12 U2 J6 J10 OSCI OSCXI J13 J11 Fig. 12：ST20P18 real IC on demo board JP1~JP5：Short all of this jumpers JP1~JP5 in Real IC modes J5：VCC, GND J6: OTP Writer Interface J7：Pin option in ST20P18 open=>enable, short=<disable J10:ST20P18 IO test pins=>PE [3~0], PA [7~0], SCXI, OSCXO, PSGO, PSGOB, RESET J11: Port B [7~0] share with SEG [39~32], Port C [7:0] with SEG [31~24] and LCD COM [7~0] J12: PA [7~4] ST2024C on-line connect header J13：Reset 1-2 =>ST20P18/ST2016, 3-4=> ST2024C U1：CD40106BE=>Remove Schmitt trigger simulate in Real IC U2：74HC125=> Remove TRI-STATE BUFFER simulate in Real IC OSCXI/PD0：FOR 32768HZ INPUT /Port-D input OSCI：OSC input pin with external resistor