Rev 3; 3/07 Triple 128-Position Nonvolatile Digital Variable Resistor/Switch The DS3904/DS3905 contain three nonvolatile (NV) low temperature coefficient, variable digital resistors. Each resistor has 128 user-selectable positions. Additionally, the DS3904/DS3905 have a high-impedance setting that allows each resistor to function as a digital switch. The DS3904/DS3905 can operate over a 2.7V to 5.5V supply voltage range, and communication with the device is achieved through a 2-wire serial interface. Address pins allow multiple DS3904/DS3905s to operate on the same two-wire bus. The DS3904 has one address pin, allowing two DS3904s to share the bus, while the DS3905 has three address pins, allowing up to eight DS3905s to share a common bus. The low-cost and small size of the DS3904/DS3905 make them ideal replacements for conventional mechanical trimming resistors. Features Ω, or Two 20kΩ Ω and One 10kΩ Ω, 128♦ Three 20kΩ Position Linear Digital Resistors ♦ Resistor Settings are Stored in NV Memory ♦ Each Resistor has a High-Impedance Setting for Switch Operation to Control Digital Logic ♦ Low Temperature Coefficient ♦ 2-Wire Serial Interface ♦ 2.7V to 5.5V Operating Range ♦ -40°C to +85°C Industrial Temperature ♦ Packaging: 8-Pin µSOP for DS3904, 10-pin µSOP for DS3905 Ordering Information PART Applications TEMP RANGE PIN(R0/R1/R2) PACKAGE RESISTANCE (k) DS3904U-010 -40°C to +85°C 8 μSOP 20/10/20 + High-Z Power-Supply Calibration DS3904U-020 -40°C to +85°C 8 μSOP 20/20/20 + High-Z Cell Phones and PDAs DS3905U-020 -40°C to +85°C 10 μSOP 20/20/20 + High-Z Fibre Optic Transceiver Modules Pin Configurations Portable Electronics TOP VEIW Small and Low-Cost Replacement for Conventional Mechanical Trimming Resistors/ Dip Switches Test Equipment SDA 1 8 A0 SCL 2 7 H0 6 H1 5 H2 VCC 3 GND DS3904 4 μSOP A1 1 10 A2 SDA 2 9 SDL 3 8 H0 7 H1 6 H2 VCC 4 GND 5 DS3905 A0 μSOP Typical Operating Circuit INTERFACE EXAMPLES VCC VCC DS3904/DS3905 VCC 0.1μF 4.7kΩ H0 RESISTOR 0 ADDR F8h 4.7kΩ R10 RHIZ VARIABLE RESISTANCE FOR ADJUSTABLE CURRENT SOURCE VCC 2-WIRE MASTER SCL SDA A0 (DS3905 ONLY) R11 RHIZ DIGITAL LOGIC H1 RESISTOR 1 ADDR F9h 2-WIRE ADDRESSABLE SWITCH (USING 00h AND RHIZ SETTINGS) VIN A1 A2 RHIZ RESISTOR 2 ADDR FAh GAIN CONTROL H2 GND R12 _____________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 DS3904/DS3905 General Description DS3904/DS3905 Triple 128-Position Nonvolatile Variable Digital Resistor/Switch ABSOLUTE MAXIMUM RATINGS Voltage on VCC Pin Relative to Ground.................-0.5V to +6.0V Voltage on SDA, SCL, A0, A1, A2 Relative to Ground*...................................-0.5V to VCC + 0.5V Voltage on H0, H1, and H2 Relative to Ground .......................................-0.5V to +6.0V Current Through H0, H1, and H2..........................................3mA Operating Temperature Range ...........................-40°C to +85°C Programming Temperature Range .........................0°C to +70°C Storage Temperature Range .............................-55°C to +125°C Soldering Temperature...................See J-STD-020 Specification *This voltage must not exceed 6.0V. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED DC OPERATING CONDITIONS (TA = -40°C to +85°C) PARAMETER SYMBOL MAX UNITS 2.7 5.5 V VIH 0.7 x VCC VCC + 0.3 V Input Logic 0 VIL -0.3 0.3 x VCC V Resistor Current IR 3 mA +5.5 V TYP MAX +1 UNITS µA VCC = 3V (Note 3) 95 200 VCC = 5V (Note 3) 145 200 Supply Voltage VCC Input Logic 1 Resistor Terminals H0, H1, H2 CONDITIONS (Note 1) VCC = +2.7V to +5.5V MIN TYP -0.3 DC ELECTRICAL CHARACTERISTICS (VCC = +2.7V to +5.5V, TA = -40°C to +85°C, unless otherwise noted.) PARAMETER Input Leakage SYMBOL IL Standby Supply Current ISTBY Low-Level Output Voltage (SDA) CONDITIONS (Note 2) MIN -1 VOL1 3mA sink current 0 0.4 VOL2 6mA sink current 0 0.6 µA V ANALOG RESISTOR CHARACTERISTICS (VCC = +2.7V to +5.5V, TA = -40°C to +85°C, unless otherwise noted.) PARAMETER SYMBOL Absolute Linearity (Note 4) INL Relative Linearity (Note 5) DNL Temperature Coefficient (Note 6) 2 20k resistor CONDITIONS MIN -1 10k resistor -1 +1 20k resistor -0.5 +0.5 10k resistor -0.5 +0.5 Position 7Fh (20k resistor) -200 +123 +400 Position 7Fh (10k resistor) -150 +173 +450 ______________________________________________________________________ TYP MAX +1 UNITS LSB LSB ppm/°C Triple 128-Position Nonvolatile Digital Variable Resistor/Switch DS3904/DS3905 ANALOG RESISTOR CHARACTERISTICS (continued) (VCC = +2.7V to +5.5V, TA = -40°C to +85°C, unless otherwise noted.) PARAMETER SYMBOL Position 7Fh Resistance RMAX Position 00h Resistance RMIN High Impedance RHIZ CONDITIONS TA = +25°C (20k resistor) MIN 14.5 TYP 20 MAX 25.5 TA = +25°C (10k resistor) 8 10 12 TA = +25°C 200 500 5.5 UNITS k M AC ELECTRICAL CHARACTERISTICS (VCC = +2.7V to +5.5V, TA = -40°C to +85°C.) PARAMETER SYMBOL SCL Clock Frequency (Note 7) fSCL Bus Free Time between STOP and START Conditions (Note 7) tBUF Hold Time (Repeated) START Condition (Notes 7, 8) tHD:STA Low Period of SCL Clock (Note 7) tLOW High Period of SCL Clock (Note 7) tHIGH Data Hold Time (Notes 7, 9) tHD:DAT Data Setup Time (Note 7) tSU:DAT Start Setup Time tSU:STA CONDITIONS Fast mode Standard mode MIN 0 TYP 0 Fast mode 1.3 Standard mode 4.7 Fast mode 0.6 Standard mode 4.0 Fast mode 1.3 Standard mode 4.7 Fast mode 0.6 Standard mode 4.0 MAX 400 100 µs µs µs 0 0.9 Standard mode 0 0.9 100 Standard mode 250 Fast mode 0.6 Standard mode 4.7 µs 20 + 0.1CB 300 Standard mode 20 + 0.1CB 1000 Fast mode 20 + 0.1CB 300 Standard mode 20 + 0.1CB 300 tR Fall Time of Both SDA and SCL Signals (Note 10) tF Setup Time for STOP Condition tSU:STO Capacitive Load for Each Bus Line CB (Note 10) EEPROM Write Time tW (Note 11) Startup Time tST Fast mode 0.6 Standard mode 4.0 µs ns Fast mode Rise Time of Both SDA and SCL Signals (Note 10) kHz µs Fast mode Fast mode UNITS ns ns µs 400 10 pF 20 ms 2 ms _____________________________________________________________________ 3 DS3904/DS3905 Triple 128-Position Nonvolatile Digital Variable Resistor/Switch NONVOLATILE MEMORY CHARACTERISTICS (VCC = +2.7V to +5.5V, TA = +70°C.) PARAMETER SYMBOL CONDITIONS EEPROM Writes MIN TYP MAX UNITS 50,000 All voltages are referenced to ground. Applies to A0, SDA, SCL for the DS3904 and A0, A1, A2, SDA, SCL for the DS3905. Also applies to H0, H1, H2 for both DS3904 and DS3905 when in the high-impedance state. Note 3: ISTBY specified with SDA = SCL = VCC and A0 = GND. Note 4: Absolute linearity is used to determine expected resistance. Absolute linearity is defined as the deviation from the straight line drawn from the value of the resistance at position 00h to the value of the resistance at position 7Fh. Note 5: Relative linearity is used to determine the change of resistance between two adjacent resistor positions. Note 6: Temperature coefficient specifies the change in resistance as a function of temperature. The temperature coefficient varies with resistor position. Limits are guaranteed by design. Note 7: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT > 250ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tRMAX + tSU:DAT = 1000ns + 250ns =1250ns before the SCL line is released. Note 8: After this period, the first clock pulse is generated. Note 9: The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal. Note 10: CB—total capacitance of one bus line in picofarads, timing referenced to 0.9 x VCC and 0.1 x VCC. Note 11: EEPROM write begins after a stop condition occurs. Note 1: Note 2: 4 ______________________________________________________________________ Triple 128-Position Nonvolatile Digital Variable Resistor/Switch SUPPLY CURRENT vs. TEMPERATURE SUPPLY CURRENT vs. SCL FREQUENCY 80 60 SDA = SCL =VCC ADDRESS PINS CONNECTED TO GND 80 10kΩ RESISTOR 0 20 40 60 0 80 TEMPERATURE COEFFICIENT vs. RESISTOR SETTING 400 300 TC OF +25°C TO +85°C TC OF +25°C TO -40°C 100 0 -100 -200 10kΩ RESISTOR 800 700 600 500 TC OF +25°C TO +85°C 400 300 TC OF +25°C TO -40°C 200 100 40 60 80 100 120 20 RESISTOR SETTING (DEC) 20kΩ RESISTOR 60 80 100 120 -20 0 20 40 TEMPERATURE (°C) 60 20kΩ RESISTOR 0.4 0.2 0 -0.2 -20 0 80 40 60 80 RESISTANCE vs. POWER-DOWN VOLTAGE 80 70 20 TEMPERATURE (°C) EEPROM RECALL 60 50 40 PROGRAMMED RESISTANCE 100 >5.5MΩ 90 80 70 EEPROM RECALL 60 50 40 PROGRAMMED RESISTANCE 30 20 20 10 10 0 0 -40 0.6 -40 >5.5MΩ 90 30 -2.0 -2.5 125 10kΩ RESISTOR RESISTANCE vs. POWER-UP VOLTAGE RESISTANCE (kΩ) 10kΩ RESISTOR 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 40 100 DS3904/5 toc07 3.5 3.0 2.5 2.0 0.8 RESISTOR SETTING (DEC) POSITION 00h RESISTANCE PERCENT CHANGE FROM +25°C vs. TEMPERATURE 100 -0.4 0 RESISTANCE (kΩ) 20 75 1.0 0 0 50 POSITION 7Fh RESISTANCE PERCENT CHANGE FROM +25°C vs. TEMPERATURE 900 TEMPERATURE COEFFICIENT (ppm/°C) DS3904/5 toc04 TEMPERATURE COEFFICIENT vs. RESISTOR SETTING 500 25 RESISTOR SETTING (DEC) SCL FREQUENCY (kHz) 20kΩ RESISTOR 0 100 150 200 250 300 350 400 50 TEMPERATURE (°C) 600 200 DS3904/5 toc03 5 RESISTANCE % CHANGE (FROM +25°C) 0 10 20 DS3904/5 toc05 -20 20kΩ RESISTOR 15 60 0 -40 RESISTANCE % CHANGE (FROM +25°C) DS3904/5 toc02 100 40 0 TEMPERATURE COEFFICIENT (ppm/°C) 120 DS3904/5 toc09 20 140 20 DS3904/5 toc06 100 40 160 RESISTANCE (kΩ) VCC = +3V 25 DS3904/5 toc08 SUPPLY CURRENT (μA) 120 VCC = SDA = +5V ADDRESS PINS CONNECTED TO GND 180 SUPPLY CURRENT (μA) VCC = +5V 140 200 DS3904/5 toc01 160 RESISTANCE vs. RESISTOR SETTING 0 1 2 3 4 POWER-UP VOLTAGE (V) 5 6 0 1 2 3 4 5 6 POWER-DOWN VOLTAGE (V) _____________________________________________________________________ 5 DS3904/DS3905 Typical Operating Characteristics (VCC = +5.0V, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VCC = +5.0V, TA = +25°C, unless otherwise noted.) 10 10kΩ RESISTOR 5 0 3.0 3.5 4.0 4.5 5.0 5.5 0.1 0 -0.1 -0.2 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.4 -0.5 0 20 40 60 80 100 0 120 80 100 ABSOLUTE LINEARITY vs. RESISTOR 1 POSITION RELATIVE LINEARITY vs. RESISTOR 1 POSITION ABSOLUTE LINEARITY vs. RESISTOR 2 POSITION -0.2 0.2 0.1 0 -0.1 -0.2 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.3 -0.4 -0.4 -0.4 -0.5 -0.5 40 60 80 100 -0.5 0 120 20 40 60 80 100 0 120 20 40 60 80 100 RESISTOR 1 POSITION (DEC) RESISTOR 1 POSITION (DEC) RESISTOR 2 POSITION (DEC) RELATIVE LINEARITY vs. RESISTOR 2 POSITION ABSOLUTE LINEARITY vs. RESISTOR 1 POSITION RELATIVE LINEARITY vs. RESISTOR 1 POSITION 0.2 0.1 0 -0.1 -0.2 0.3 0.2 0.1 0 -0.1 -0.2 0.5 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.3 -0.4 -0.4 -0.4 -0.5 -0.5 40 60 80 100 RESISTOR 2 POSITION (DEC) 120 RESISTOR 1 10kΩ 0.4 -0.3 -0.5 120 DS3904/5 toc18 RESISTOR 1 10kΩ 0.4 RELATIVE LINEARITY (LSB) 0.3 0.5 DS3904/5 toc17 RESISTOR 2 20kΩ ABSOLUTE LINEARITY (LSB) DS3904/5 toc16 0.5 20 RESISTOR 2 20kΩ 0.4 -0.3 20 DS3904/5 toc15 0.3 120 0.5 ABSOLUTE LINEARITY (LSB) -0.1 RESISTOR 1 20kΩ 0.4 RELATIVE LINEARITY (LSB) 0 DS3904/5 toc14 0.5 DS3904/5 toc13 0.1 0 60 RESISTOR 0 POSITION (DEC) 0.2 0.4 40 RESISTOR 0 POSITION (DEC) 0.3 0 20 SUPPLY VOLTAGE (V) RESISTOR 1 20kΩ 0.4 0.3 -0.3 6.0 0.5 ABSOLUTE LINEARITY (LSB) 0.2 -0.5 2.5 6 0.3 RESISTOR 0 20kΩ 0.4 RELATIVE LINEARITY (LSB) 20kΩ RESISTOR RESISTOR 0 20kΩ 0.4 0.5 DS3904/5 toc11 20 0.5 ABSOLUTE LINEARITY (LSB) DS3904/5 toc10 POSITION 3Fh RESISTANCE (kΩ) 25 15 RELATIVE LINEARITY vs. RESISTOR 0 POSITION ABSOLUTE LINEARITY vs. RESISTOR 0 POSITION DS3904/5 toc12 POSITION 3Fh RESISTANCE vs. SUPPLY VOLTAGE RELATIVE LINEARITY (LSB) DS3904/DS3905 Triple 128-Position Nonvolatile Digital Variable Resistor/Switch 0 20 40 60 80 100 120 RESISTOR 1 POSITION (DEC) ______________________________________________________________________ 0 20 40 60 80 100 RESISTOR 1 POSITION (DEC) 120 Triple 128-Position Nonvolatile Digital Variable Resistor/Switch NAME PIN DS3904 DS3905 DESCRIPTION Table 1. Variable Resistor Registers ADDRESS VARIABLE RESISTOR POSITION 7Fh RESISTANCE NUMBER OF POSITIONS* SDA 1 2 2-Wire Serial Data. Open-drain input/output for 2-wire data. F8h Resistor 0 20k (nominal) 128 (00h to 7Fh) + Hi-Z SCL 2 3 2-Wire Serial Clock. Input for 2-wire clock. F9h Resistor 1 20k or 10k (nominal) 128 (00h to 7Fh) + Hi-Z FAh Resistor 2 20k (nominal) 128 (00h to 7Fh) + Hi-Z VCC 3 4 Supply Voltage Terminal GND 4 5 Ground Terminal H2 5 6 Resistor 2 High Terminals H1 6 7 Resistor 1 High Terminals H0 7 8 Resistor 0 High Terminals A0 8 9 Address-Select Pin A1 — 1 Address-Select Pin (DS3905 Only) A2 — 10 Address-Select Pin (DS3905 Only) Detailed Description The DS3904/DS3905 contain three, 128-position, NV, low temperature coefficient, variable digital resistors. All three resistors also feature a Hi-Z function. The variable resistor registers (F8h, F9h, and FAh) are factory programmed with a default value of 7Fh. They are controlled through a 2-wire serial interface, and can serve as a low-cost replacement for designs using conventional trimming resistors. Furthermore, the DS3904 address pin (A0) allows two DS3904s to be placed on the same 2-wire bus. The three address pins on the DS3905 allow up to eight DS3905s to be placed on the same 2-wire bus. With their low cost and small size, the DS3904/DS3905 are well tailored to replace larger mechanical trimming variable resistors. This allows the automation of calibration in many instances because the 2-wire interface can easily be adjusted by test/production equipment. Variable Resistor Memory Organization The variable resistors of the DS3904/DS3905 are addressed by communicating with the registers in Table 1. Using the Resistor as a Switch By taking advantage of the high-impedance mode, a switch can be created to produce a digital output. Setting a resistor register to 00h creates the low state. Writing 80h into the same resistor register enables the high-impedance state. When used with an external pullup resistor, such as a 4.7kΩ pullup, a high state is generated. *Writing a value greater than 7Fh to any of the resistor registers sets the high-impedance mode control bit (RHIZ, the MSB of the resistor register) resulting in the resistor going into highimpedance mode. Position 0 is the minimum position. Position 7Fh is the maximum position. Device Operation Clock and Data Transitions The SDA pin is normally pulled high with an external resistor or device. Data on the SDA pin can only change during SCL low time periods. Data changes during SCL high periods indicate a start or stop condition depending on the conditions discussed below. See the timing diagrams for further details (Figures 2 and 3). Start Condition A high-to-low transition of SDA with SCL high is a start condition, which must precede any other command. See the timing diagrams for further details (Figures 2 and 3). Stop Condition A low-to-high transition of SDA with SCL high is a stop condition. After a read or write sequence, the stop command places the DS3904/DS3905 into a low-power mode. See the timing diagrams for further details (Figures 2 and 3). Acknowledge All address and data bytes are transmitted through a serial protocol. The DS3904/DS3905 pull the SDA line low during the ninth clock pulse to acknowledge that they have received each byte. Standby Mode The DS3904/DS3905 feature a low-power mode that is automatically enabled after power-on, after a stop command, and after the completion of all internal operations. _____________________________________________________________________ 7 DS3904/DS3905 Pin Description DS3904/DS3905 Triple 128-Position Nonvolatile Digital Variable Resistor/Switch VCC EEPROM VCC DS3905 H0 RHIZ CONTROL F8h RESISTOR 0 MSB 7 LSB RES 0 20kΩ GND H1 RHIZ CONTROL SCL DATA SDA (DS3905 ONLY) A0 A1 A2 2-WIRE INTERFACE F9h RESISTOR 1 MSB 7 LSB RES 1 20kΩ OR 10kΩ FAh RESISTOR 2 MSB 7 LSB Acknowledge Polling H2 RHIZ CONTROL where the data is to be written. After the byte has been received, the DS3904/DS3905 transmit a zero for one clock cycle to acknowledge that the memory address has been received. The master must then transmit an 8bit data word to be written into this memory address. The DS3904/DS3905 again transmit a zero for one clock cycle to acknowledge the receipt of the data byte. At this point, the master must terminate the write operation with a stop condition. The DS3904/DS3905 then enter an internally timed write process tw to the EEPROM memory. All inputs are disabled during this write cycle. RES 2 20kΩ Once a EEPROM write is initiated, the part will not acknowledge until the cycle is complete. Another option is to wait the maximum write cycle delay before initiating another write cycle. Read Operations Figure 1. DS3904/DS3905 Block Diagram Bus Reset After any interruption in protocol, power loss, or system reset, the following steps reset the DS3904/DS3905: 1) Clock up to nine cycles. 2) 3) Look for SDA high in each cycle while SCL is high. Create a start condition while SDA is high. Device Addressing The DS3904/DS3905 must receive an 8-bit device address byte following a start condition to enable a specific device for a read or write operation. The address byte is clocked into the DS3904/DS3905 MSB to LSB. For the DS3904, the address byte consists of 101000 binary followed by A0 then the R/W bit. If the R/W bit is high, a read operation is initiated. For the DS3905, the address byte consists of 1010 binary followed by A2, A1, A0 then the R/W bit. If the R/W bit is low, a write operation is initiated. For a device to become active, the value of the address bits must be the same as the hard-wired address pins on the DS3904/DS3905. Upon a match of written and hardwired addresses, the DS3904/DS3905 output a zero for one clock cycle as an acknowledge. If the address does not match, the DS3904/DS3905 return to a lowpower mode. Write Operations After receiving a matching device address byte with the R/W bit set low, the device goes into the write mode of operation. The master must transmit an 8-bit EEPROM memory address to the device to define the address 8 After receiving a matching address byte with the R/W bit set high, the device goes into the read mode of operation. A read requires a dummy byte write sequence to load in the register address. Once the device address and data address bytes are clocked in by the master, and acknowledged by the DS3904/ DS3905, the master must generate another start condition (repeated start). The master now initiates a read by sending the device address with the R/W bit set high. The DS3904/DS3905 acknowledge the device address and serially clock out the data byte. The master responds with a NACK and generates a stop condition afterwards. See Figures 4 and 5 for command and data byte structures as well as read and write examples. 2-Wire Serial Port Operation The 2-wire serial port interface supports a bidirectional data transmission protocol with device addressing. A device that sends data on the bus is defined as a transmitter, and a device receiving data as a receiver. The device that controls the message is called a master. The devices that are controlled by the master are slaves. The bus must be controlled by a master device that generates the SCL, controls the bus access, and generates the start and stop conditions. The DS3904/DS3905 operate as slaves on the 2-wire bus. Connections to the bus are made through SCL and open-drain SDA lines. The following I/O terminals control the 2-wire serial port: SDA, SCL, and A0. The DS3905 uses two additional address pins A1 and A2 to control the 2-wire serial port. Timing diagrams for the 2-wire serial port can be found in Figures 2 and 3. Timing information for the 2-wire serial port is provided in the AC Electrical Characteristics table for 2-wire serial communications. ______________________________________________________________________ Triple 128-Position Nonvolatile Digital Variable Resistor/Switch DS3904/DS3905 SDA MSB SLAVE ADDRESS R/W DIRECTION BIT ACKNOWLEDGEMENT SIGNAL FROM RECEIVER ACKNOWLEDGEMENT SIGNAL FROM RECEIVER SCL 1 2 6 7 8 9 1 2 3–7 8 ACK START CONDITION 9 ACK REPEATED IF MORE BYTES ARE TRANSFERRED STOP CONDITION OR REPEATED START CONDITION Figure 2. 2-Wire Data Transfer Protocol SDA tBUF tHD:STA tLOW tR tSP tF SCL tHD:STA STOP tSU:STA tHIGH tSU:DAT START REPEATED START tSU:STO tHD:DAT Figure 3. 2-Wire AC Characteristics The following bus protocol has been defined: Data transfer can be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high are interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus Not Busy: Both data and clock lines remain high. Start Data Transfer: A change in the state of the data line from high to low while the clock is high defines a start condition. Stop Data Transfer: A change in the state of the data line from low to high while the clock line is high defines the stop condition. Data Valid: The state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line can be changed during the low period of the clock signal. There is _____________________________________________________________________ 9 DS3904/DS3905 Triple 128-Position Nonvolatile Digital Variable Resistor/Switch COMMAND BYTE MSB START 1 0 1 0 A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable low during the high period of the acknowledge-related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line high to enable the master to generate the stop condition. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the command/control byte. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. DATA BYTE LSB A2* A1* A0 R/W MSB DEVICE IDENTIFIER SLAVE OR ADDRESS "FAMILY CODE" LSB RHIZ CONTROL BIT RESISTOR SETTING *DS3904, USE 0's INSTEAD OF A2 AND A1 FOR THE DEVICE ADDRESS Figure 4. Command and Data Byte Structures one clock pulse per bit of data. Figures 2 and 3 detail how data transfer is accomplished on the 2wire bus. Depending upon the state of the R/W bit, two types of data transfer are possible. Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between start and stop conditions is not limited and is determined by the master device. The information is transferred bytewise and each receiver acknowledges with a ninth bit. Within the bus specifications, a regular mode (100kHz clock rate) and a fast mode (400kHz clock rate) are defined. The DS3904/DS3905 work in both modes. Acknowledge: Each receiving device, when addressed, generates an acknowledge after the byte has been received. The master device must generate an extra clock pulse that is associated with this acknowledge bit. Data transfer from a slave transmitter to a master receiver. The master transmits the first byte (the command/control byte) to the slave. The slave then returns an acknowledge bit. Next follows the data byte transmitted by the slave to the master. The master returns NACK followed by a stop. The master device generates all serial clock pulses and the start and stop conditions. A transfer is ended with a stop condition or with a repeated start condition. Since a repeated start condition is also the beginning of the next serial transfer, the bus is not released. EXAMPLE 2-WIRE TRANSACTIONS MSB WRITE RESISTOR 0 TO MIN POSITION START SET RESISTOR 1 TO Hi-Z START WRITE RESISTOR 2 TO MAX POSITION START READ RESISTOR 1 VALUE START 1 A0h 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 MSB 1 0 0 0 0 0 0 0 0 0 0 0 0 FROM SLAVE 0 ACK LSB 0 0 A1h 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 0 1 0 1 1 0 0 F9h FROM SLAVE MSB 0 ACK 0 1 0 1 0 0 0 0 0 1 1 1 RESISTOR DATA 1 ACK LSB MASTER NACK Figure 5. Example 2-Wire Transactions _____________________________________________________________________ 0 0 0 0 0 1 1 1 0 FROM SLAVE ACK STOP ACK STOP ACK STOP LSB 0 LSB 7Fh REPEATED START STOP 0 80h LSB F9h A0 = GND FOR DS3904 A0, A1, A2 = GND FOR DS3905 10 0 MSB ACK LSB 00h 0 MSB ACK LSB MSB ACK LSB LSB FAh MSB ACK LSB 1 1 F8h MSB ACK LSB 0 MSB MSB ACK LSB A0h MSB 1 0 A0h MSB 1 0 A0h MSB 1 0 LSB 1 Triple 128-Position Nonvolatile Digital Variable Resistor/Switch Power-Supply Decoupling 1) Slave Receiver Mode: Serial data and clock are received through SDA and SCL, respectively. After each byte is received, an acknowledge bit is transmitted. Start and stop conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after the slave (device) address and direction bit has been received. To achieve the best results when using the DS3904/ DS3905, decouple the power supply with a 0.01µF or 0.1µF capacitor. Use a high-quality ceramic surfacemount capacitor. Surface-mount components minimize lead inductance, which improves performance, and ceramic capacitors tend to have adequate high-frequency response for decoupling applications. 2) Slave Transmitter Mode: The first byte is received and handled as in the slave receiver mode. However, in this mode the direction bit indicates that the transfer direction is reversed. Serial data is transmitted on SDA by the DS3904/DS3905 while the serial clock is input on SCL. Start and stop conditions are recognized as the beginning and end of a serial transfer. It is possible to have a voltage on the resistor-high terminals that is higher than the voltage connected to VCC. For instance, connecting VCC to 3.0V while one or more of the resistor high terminals are connected to 5.0V allows a 3V system to control a 5V system. The 5.5V maximum still applies to the limit on the resistor high terminals regardless of the voltage present on VCC. Slave Address: The command/control byte is the first byte received following the start condition from the master device. The command/control byte consists of a 4-bit device identifier. For the DS3904, the identifier is followed by the device-select bits 0, 0, and A0. For the DS3905, the identifier is followed by the device-select bits A2, A1, A0. The device identifier is used by the master device to select which device is to be accessed. When reading or writing the DS3904/DS3905, the device-select bits must match the device-select pin(s). The last bit of the command/control byte (R/W) defines the operation to be performed. When set to a ‘1’, a read operation is selected, and when set to a ‘0’, a write operation is selected. Following the start condition, the DS3904/DS3905 monitor the SDA bus checking the device-type identifier being transmitted. Upon receiving the control code, the appropriate device address bit, and the read/write bit, the slave device outputs an acknowledge signal on the SDA line. High Resistor Terminal Voltage 3) Package Information For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11 © 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. is a registered trademark of Dallas Semiconductor Corporation. DS3904/DS3905 Applications Information The DS3904/DS3905 can operate in the following three modes: