Rev 0; 4/03 Hex Nonvolatile Potentiometer with I/O and Memory The DS3930 contains six 256-position nonvolatile (NV) potentiometers, 64 bytes of NV user EEPROM memory, and four programmable NV I/O pins. The six potentiometers all share a common low side. The potentiometers are separated into two groups of three 50kΩ potentiometers in parallel. Each group of three potentiometers shares a common high side and forms an equivalent resistance of 16.6kΩ (three 50kΩ potentiometers in parallel). Applications RF Transceivers Features ♦ Six 256-Position NV Potentiometers ♦ Four General-Purpose NV I/O Pins ♦ 64 Bytes of User EEPROM Memory ♦ 0 to 5.5V on Any Potentiometer Terminal, Independent of VCC ♦ All Six Potentiometers Share a Common Low Side ♦ Potentiometers Separated into Two Groups of Three Potentiometers, Each Sharing a Common High Side ♦ 2-Wire Serial Interface ♦ Wide Supply Range (2.7V to 5.5V) Voltage References ♦ Up to Eight DS3930s Can Share the Same 2-Wire Bus Power Supply Calibration Mobile Phones and PDAs Fiber Optic Transceiver Modules Ordering Information Portable Electronics Radio Tuners PART Small, Low-Cost Replacement for Mechanical Potentiometers PIN-PACKAGE 20 TSSOP DS3930E Pin Configuration Typical Operating Circuit TOP VIEW VCC A1 2 19 W0 A2 3 18 W1 4.7kΩ DS3930 16 LO0-5 2-WIRE INTERFACE W0 A2 W1 SDA W2 I/O0 I/O1 7 14 W3 I/O2 8 13 W4 VCC 9 12 W5 GND 10 11 I/O3 DIGITAL NONVOLATILE I/O VCC DECOUPLING CAP 0.1µF TSSOP A1 SCL 15 HI3-5 I/O0 6 A0 HI0-2 4.7kΩ 17 W2 SDA 4 SCL 5 VCC 20 HI0-2 A0 1 LO0-5 DS3930 HI3-5 I/O1 W3 I/O2 W4 VCC GND WIPER TERMINALS WIPER TERMINALS W5 I/O3 DIGITAL NONVOLATILE I/O _____________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 DS3930 General Description DS3930 Hex Nonvolatile Potentiometer with I/O and Memory ABSOLUTE MAXIMUM RATINGS Operating Temperature Range .......................... -40°C to +85°C Programming Temperature Range .........................0°C to +70°C Storage Temperature Range .............................-55°C to +125°C Soldering Temperature.................. See IPC/JEDEC J-STD-020A Voltage on VCC Relative to Ground...................... -0.5V to +6.0V Voltage on I/O0, I/O1, I/O2, I/O3, SDA, SCL, A0, A1, and A2 Relative to Ground* .............................. -0.5V to (VCC + 0.5V) Voltage on LO0-5, W0-5, HI0-2, and HI3-5 Relative to Ground ............................................-0.5V to +6.0V Current Through W0-5 ........................................................ ±1mA *This voltage must not exceed 6.0V. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED DC OPERATING CONDITIONS (TA = -40° to +85°C) PARAMETER SYMBOL CONDITIONS TYP MAX UNITS +2.7 +5.5 V Supply Voltage VCC Input Logic 1 (SDA, SCL, A0, A1, A2, I/O0, I/O1, I/O2, I/O3) VIH 0.7 x VCC VCC + 0.3 V Input Logic 0 (SDA, SCL, A0, A1, A2, I/O0, I/O1, I/O2, I/O3) VIL -0.3 0.3 x VCC V Wiper Current IW -1 +1 mA -0.3 +5.5 V MAX UNITS Potentiometer Terminals (LO0-5, W0-5, HI0-2, and HI3-5) (Note 1) MIN VCC = +2.7V to +5.5V DC ELECTRICAL CHARACTERISTICS (VCC = +2.7V to +5.5V; TA = -40°C to +85°C, unless otherwise specified.) PARAMETER Input Leakage SYMBOL CONDITIONS TYP -1 +1 µA Low-Level Output Voltage (SDA, I/O0, I/O1, I/O2, I/O3) VOL1 3mA sink current 0 0.4 V VOL2 6mA sink current 0 0.6 V I/O Capacitance CI/O 10 pF I/O Pullup Resistor Value RI/O 5 7.0 kΩ 3V (Note 2) 160 300 5V (Note 2) 195 350 Standby Current 2 IIL MIN ISTBY 3.5 ______________________________________________________________________ µA Hex Nonvolatile Potentiometer with I/O and Memory DS3930 ANALOG RESISTOR CHARACTERISTICS (VCC = +2.7V to +5.5V; TA = -40°C to +85°C, unless otherwise specified.) PARAMETER SYMBOL End-to-End Resistance Wiper Resistance CONDITIONS TA = +25°C (three 50kΩ pots in parallel) MIN TYP 13.2 RW MAX UNITS 16.5 19.8 kΩ 400 1000 Ω Factory Default Wiper Setting FF Factory Default I/O Setting 0F POT-to-POT Matching Differential Linearity Integral Linearity End-to-End Temperature Coefficient 3 potentiometers in parallel Hex Hex -1 +1 -0.5 +0.5 LSB -1 +1 LSB +250 ppm/°C -250 Ratiometric Temperature Coefficient 0 2 LSB ppm/°C AC ELECTRICAL CHARACTERISTICS (VCC = +2.7V to +5.5V; TA = -40°C to +85°C, unless otherwise specified.) PARAMETER SYMBOL SCL Clock Frequency (Note 3) fSCL Bus Free Time Between STOP and START Condition (Note 3) tBUF Hold Time (Repeated) START Condition (Notes 3 and 4) tHD:STA Low Period of SCL Clock (Note 3) tLOW High Period of SCL Clock (Note 3) tHIGH CONDITIONS MIN TYP MAX Fast mode 0 400 Standard mode 0 100 Fast mode 1.3 Standard mode 4.7 Fast mode 0.6 Standard mode 4.0 Fast mode 1.3 Standard mode 4.7 Fast mode 0.6 Standard mode 4.0 UNITS kHz µs µs µs µs _____________________________________________________________________ 3 DS3930 Hex Nonvolatile Potentiometer with I/O and Memory AC ELECTRICAL CHARACTERISTICS (continued) (VCC = +2.7V to +5.5V; TA = -40°C to +85°C, unless otherwise specified.) PARAMETER SYMBOL Data Hold Time (Notes 3, 5, 7) tHD:DAT Data Setup Time (Note 3) tSU:DAT Start Setup Time (Note 3) tSU:STA CONDITIONS MIN TYP MAX Fast mode 0 0.9 Standard mode 0 0.9 Fast mode 100 Standard mode 250 Fast mode 0.6 Standard mode 4.7 µs 20 + 0.1CB 300 Standard mode 20 + 0.1CB 1000 Fast mode 20 + 0.1CB 300 Standard mode 20 + 0.1CB 300 tR Fall Time of Both SDA and SCL Signals (Note 7) tF Setup Time for STOP Condition tSU:STO Capacitive Load for Each Bus CB (Note 7) EEPROM Write Time tW (Note 8) Fast mode 0.6 Standard mode 4.0 µs ns Fast mode Rise Time of Both SDA and SCL Signals (Note 7) UNITS ns ns µs 400 pF 5 20 ms TYP MAX UNITS EEPROM CHARACTERISTICS (VCC = +2.7V to +5.5V; TA = -40°C to +85°C, unless otherwise specified.) PARAMETER Writes Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: 4 SYMBOL CONDITIONS +70°C MIN 50,000 All voltages are referenced to ground. ISTBY specified for VCC equal 3.0V and 5.0V, SDA = SCL = VCC, and I/O0 = I/O1 = I/O2 = I/O3 = A0 = A1 = A2 = GND. A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT > 250ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tRMAX + tSU:DAT = 1000ns +250ns = 1250ns before the SCL line is released. After this period, the first clock pulse is generated. The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH MIN of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. CB—total capacitance of one bus line in picofarads, timing referenced to 0.9VCC and 0.1VCC. EEPROM write begins after a STOP condition occurs. ______________________________________________________________________ Hex Nonvolatile Potentiometer with I/O and Memory (VCC = 5.0V; TA = +25°C, unless otherwise specified.) 180 VCC = 3V 160 4 3 2 140 SDA = VCC 680 SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) 200 HI = 5V LO = GND 5 740 DS3930 toc02 VCC = 5V 6 VOLTAGE (V) SDA = SCL = 5V DS3930 toc01 220 ACTIVE SUPPLY CURRENT vs. SCL FREQUENCY WIPER VOLTAGE vs. WIPER SETTING DS3930 toc03 SUPPLY CURRENT vs. TEMPERATURE 620 VCC = 5V 560 500 440 VCC = 3V 380 320 1 260 120 0 0 20 40 60 80 150 200 250 300 0 200 400 300 END-TO-END RESISTANCE % CHANGE FROM +25°C vs. TEMPERATURE VOLTAGE DIVIDER % CHANGE FROM +25°C vs. TEMPERATURE 1.0 FOLLOWS VCC CHANGES TO PROGRAMMED VALUE ONCE EEPROM IS RECALLED 0.60 0.40 0.20 0 -0.20 -0.40 -0.60 -0.80 0.20 -1.00 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0.06 -20 0 20 40 0.05 0 -0.05 -0.10 -0.15 60 80 100 -40 0.4 0.3 40 60 80 0.4 0.3 0.1 0.1 INL (LSB) 0.2 0.02 INL (LSB) 20 100 POTS 1, 3, 5 INL (LSB) 0.2 -0.02 0 0.5 0.04 0 -20 TEMPERATURE (°C) POTS 0, 2, 4, INL (LSB) 0.5 DS3930 toc08 0.08 0.10 TEMPERATURE (°C) ALL POTS DNL (LSB) 0.10 HI = VCC LO0-5 = GND POSITION 127 0.15 -0.20 -40 POWER-UP VOLTAGE (V) DS3930 toc06 DS3930 toc05 3 POTS IN PARALLEL MEASURED FROM HI0-2 TO LO0-5 0.80 0 -0.1 DS3930 toc09 1.5 1.00 RESISTANCE % CHANGE (FROM +25°C) EEPROM RECALL 0 100 WIPER VOLTAGE vs. POWER-UP VOLTAGE DS3930 toc07 WIPER VOLTAGE (V) 100 SCL FREQUENCY (kHz) 0 DNL (LSB) 50 SETTING (DEC) 2.5 0.5 200 0 TEMPERATURE (°C) HI = 5V, LO = GND POSITION 127 2.0 100 RESISTANCE % CHANGE (FROM +25°C) 3.0 -20 DS3930 toc04 -40 0 -0.1 -0.04 -0.2 -0.2 -0.06 -0.3 -0.3 -0.08 -0.4 -0.4 -0.10 -0.5 -0.5 0 25 50 75 100 125 150 175 200 225 250 0 25 50 75 100 125 150 175 200 225 250 0 25 50 75 100 125 150 175 200 225 250 POSITION (DEC) POSITION (DEC) POSITION (DEC) _____________________________________________________________________ 5 DS3930 Typical Operating Characteristics Hex Nonvolatile Potentiometer with I/O and Memory DS3930 Pin Description 6 PIN NAME 1 A0 Address Input. The address input pins determine the 2-wire address of the device. FUNCTION 2 A1 Address Input 3 A2 Address Input 4 SDA 2-Wire Serial Data I/O. This pin is for serial data transfer to and from the device. 5 SCL 2-Wire Serial Clock Input. The serial clock input is used to clock data into and out of the device. 6 I/O0 General-Purpose NV I/O Pin 7 I/O1 General-Purpose NV I/O Pin 8 I/O2 General-Purpose NV I/O Pin 9 VCC Supply Voltage 10 GND Ground 11 I/O3 General-Purpose NV I/O Pin 12 W5 Wiper Terminal of Potentiometer 5 13 W4 Wiper Terminal of Potentiometer 4 14 W3 Wiper Terminal of Potentiometer 3 15 HI3-5 High-End Terminal of Potentiometers 3 to 5. This is the common high-side terminal of potentiometers 3, 4, and 5. 16 LO0-5 Low-End Terminal of the Potentiometers. This is the common low-side terminal of all six potentiometers. 17 W2 Wiper Terminal of Potentiometer 2 18 W1 Wiper Terminal of Potentiometer 1 19 W0 Wiper Terminal of Potentiometer 0 20 HI0-2 High-End Terminal of Potentiometers 0 to 2. This is the common high-side terminal of potentiometers 0, 1, and 2. ______________________________________________________________________ Hex Nonvolatile Potentiometer with I/O and Memory DS3930 EEPROM VCC 00h 3Fh 40h EFh F0h F1h F2h F3h F4h F5h F6h F7h F8h 64 BYTES OF EEPROM 8 50kΩ POT0 HI0-2 W0 RESERVED 8 POT0 CONTROL POT1 50kΩ W1 POT1 CONTROL POT2 CONTROL 8 POT2 50kΩ W2 POT3 CONTROL LO0-5 POT4 CONTROL POT5 CONTROL HI3-5 8 50kΩ POT3 I/O CONTROL W3 I/O STATE 8 RESERVED 50kΩ POT4 W4 FFh 8 POT5 50kΩ W5 SDA SCL 8 I/O0 2-WIRE INTERFACE A0 I/O CELL X 4 4 A1 I/O1 I/O2 I/O3 A2 GND DS3930 Figure 1. DS3930 Functional Diagram Detailed Description The DS3930 contains six NV potentiometers with 64 bytes of NV user memory (EEPROM), and four programmable NV I/O pins. Figure 1 is a functional diagram of the DS3930. Potentiometers The six potentiometers share a common low side and are separated into two groups of three potentiometers, each group sharing a common high side. The six 256position potentiometers are controllable using six 8-bit EEPROM registers through the 2-wire interface. _____________________________________________________________________ 7 DS3930 Hex Nonvolatile Potentiometer with I/O and Memory I/O Signals The I/O pins can be used as general-purpose digital I/O signals. The I/O pins have CMOS outputs with an Table 1. I/O Pin Truth Table PULLUP CTRL (I/O CONTROL REGISTER) (BITS 7 TO 4) I/O PIN SETTING (I/O CONTROL REGISTER) (BITS 3 TO 0) I/O PIN OUTPUT 0 0 0 0 1 1 1 0 0 1 1 Pullup disabled (HI-Z) internal pullup resistor (see Figure 2). The I/O pins are configured with the I/O Control register (F6h) and monitored with the I/O State register (F7h). The I/O Control register controls the state of the internal pullup resistor (RI/O) with bits 7 to 4 and the I/O pin setting with bits 3 to 0 (see Table 1). The read-only values of the I/O State register contains the values of the I/O pin setting bits of the I/O Control register unless the I/O output is tri-stated. When the I/O is tri-stated the I/O State register will read high or low depending on the external source on the I/O pin. Since the I/O pins are controlled by EEPROM, the number of writes is limited. Memory The memory map is shown in Table 2. Table 2. Memory Map ADDRESS DEFAULT (HEX) FUNCTION 00h to 3Fh BIT FF 64 bytes of general-purpose EEPROM 40h to EFh FF Reserved F0h FF Controls potentiometer 0 F1h FF Controls potentiometer 1 F2h FF Controls potentiometer 2 F3h FF Controls potentiometer 3 F4h FF Controls potentiometer 4 F5h FF Controls potentiometer 5 F6h 0F Set to 0 to enable I/O3 pullup, set to 1 to disable pullup Bit 6 Set to 0 to enable I/O2 pullup, set to 1 to disable pullup Bit 5 Set to 0 to enable I/O1 pullup, set to 1 to disable pullup Bit 4 Set to 0 to enable I/O0 pullup, set to 1 to disable pullup Bit 3 Sets I/O3 to 0 or 1 Bit 2 Sets I/O2 to 0 or 1 Bit 1 Sets I/O1 to 0 or 1 Bit 0 F7h Sets I/O0 to 0 or 1 0X 8 I/O State Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 Contains state of I/O3 pin (read only) Bit 2 Contains state of I/O2 pin (read only) Bit 1 Contains state of I/O1 pin (read only) Bit 0 F8h to FFh I/O Control Bit 7 Contains state of I/O0 pin (read only) FF ______________________________________________________________________ Reserved Hex Nonvolatile Potentiometer with I/O and Memory PULLUP CTRL The following bus protocol has been defined: • Data transfer can be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high are interpreted as control signals. Accordingly, the following bus conditions have been defined: RI/O I/O PIN SETTING I/O INPUT ESD Bus Not Busy: Both data and clock lines remain high. Start Data Transfer: A change in the state of the data line from high to low while the clock is high defines a start condition. Stop Data Transfer: A change in the state of the data line from low to high while the clock line is high defines the stop condition. Data Valid: The state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line can be changed during the low period of the clock signal. There is one clock pulse per bit of data. Figures 3 and 5 detail how data transfer is accomplished on the 2-wire bus. Depending upon the state of the R/W bit, two types of data transfer are possible. Each data transfer is initiated with a start condition and Figure 2. I/O Cell 2-Wire Serial Port Operation The 2-wire serial port interface supports a bidirectional data transmission protocol with device addressing. A device that sends data on the bus is defined as a transmitter, and a device receiving data as a receiver. The device that controls the message is called a “master.” The devices that are controlled by the master are “slaves.” The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the start and stop conditions. The DS3930 operates as a slave on the 2-wire bus. Connections to the bus are made through the open-drain I/O lines, SDA and SCL. The following I/O terminals control the 2-wire serial port: SDA, SCL, and A0. Timing diagrams for the 2-wire serial port can be SDA MSB SLAVE ADDRESS R/W DIRECTION BIT ACKNOWLEDGEMENT SIGNAL FROM RECEIVER ACKNOWLEDGEMENT SIGNAL FROM RECEIVER SCL 1 2 START CONDITION 6 7 8 9 1 2 3–7 8 ACK 9 ACK REPEATED IF MORE BYTES ARE TRANSFERRED STOP CONDITION OR REPEATED START CONDITION Figure 3. 2-Wire Data Transfer Protocol _____________________________________________________________________ 9 DS3930 found in Figures 3 and 5. Timing information for the 2wire serial port is provided in the AC Electrical Characteristics table for 2-wire serial communications. VCC DS3930 Hex Nonvolatile Potentiometer with I/O and Memory MSB 0 A2 A1 DEVICE ADDRESS A0 R/W REA D/W DEVICE IDENTIFIER 1 IT 0 RIT EB 1 LSB Figure 4. Slave Address terminated with a stop condition. The number of data bytes transferred between start and stop conditions is not limited and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Within the bus specifications, a regular mode (100kHz clock rate) and a fast mode (400kHz clock rate) are defined. The DS3930 works in both modes. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the byte has been received. The master device must generate an extra clock pulse that is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable low during the high period of the acknowledge-related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line high to enable the master to generate the stop condition. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the command/control byte. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. Data transfer from a slave transmitter to a master receiver. The master transmits the first byte (the command/control byte) to the slave. The slave then returns an acknowledge bit. Next follows a number of data bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received 10 byte, a not acknowledge can be returned. The master device generates all serial clock pulses and the start and stop conditions. A transfer is ended with a stop condition or with a repeated start condition. Since a repeated start condition is also the beginning of the next serial transfer, the bus is not released. The DS3930 can operate in the following three modes: Slave Receiver Mode: Serial data and clock are received through SDA and SCL, respectively. After each byte is received, an acknowledge bit is transmitted. Start and stop conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after the slave (device) address and direction bit have been received. 2) Slave Transmitter Mode: The first byte is received and handled as in the slave receiver mode. However, in this mode the direction bit indicates that the transfer direction is reversed. Serial data is transmitted on SDA by the DS3930 while the serial clock is input on SCL. Start and stop conditions are recognized as the beginning and end of a serial transfer. 3) Slave Address: This is the first byte received following the start condition from the master device. The slave address consists of a 4-bit control code. For the DS3930, this is set as 1010 binary for read/write operations. The next bits of the slave address are the device address (A2–A0). The last bit of the slave address (R/W) defines the operation to be performed. When set to a ‘1,’ a read operation is selected, and when set to a ‘0,’ a write operation is selected (see Figure 4). Following the start condition, the DS3930 monitors the SDA bus checking the device type identifier being transmitted. Upon receiving the 1010 device identifier, the appropriate device address bit, and the read/write bit, the slave device outputs an acknowledge signal on the SDA line. 1) _____________________________________________________________________ Hex Nonvolatile Potentiometer with I/O and Memory DS3930 SDA tBUF tSP tHD:STA tLOW tR tF SCL tHD:STA STOP tSU:STA tHIGH tSU:DAT START REPEATED START tSU:STO tHD:DAT Figure 5. 2-Wire AC Characteristics TYPICAL 2-WIRE WRITE TRANSACTION MSB START 1 LSB 0 1 0 A2* A1* A0* R/W DEVICE IDENTIFIER DEVICE ADDRESS MSB SLAVE ACK READ/ WRITE b7 MSB LSB b6 b5 b4 b3 b2 b1 b0 SLAVE ACK b7 LSB b6 REGISTER ADDRESS A0h START 1 0 1 0 0 0 0 0 C) SINGLE-BYTE WRITE -SET I/O0 PIN TO A "1" START 1 0 1 0 0 0 0 0 A0h F0h SLAVE SLAVE 11110000 ACK ACK A0h 00h START 1 0 1 0 0 0 0 0 SLAVE 0 0 0 0 0 0 0 0 SLAVE ACK ACK E) MULTIPLE BYTE READ -2 BYTE READ FROM EEPROM A0h 00h START 1 0 1 0 0 0 0 0 SLAVE 0 0 0 0 0 0 0 0 SLAVE ACK ACK SLAVE ACK b3 b2 b1 b0 SLAVE ACK STOP STOP A1h REPEATED START F6h DATA SLAVE SLAVE XXX0XXX1 11110110 ACK ACK D) MULTIPLE BYTE WRITE -2 BYTE WRITE TO EEPROM b4 DATA EXAMPLE 2-WIRE TRANSACTIONS (WHEN A0, A1, AND A2 ARE ZERO) A0h F0h DATA SLAVE SLAVE A) SINGLE-BYTE WRITE POT SETTING 11110000 START 1 0 1 0 0 0 0 0 ACK ACK -WRITE TO POT 0 REGISTER B) SINGLE-BYTE READ -READ FROM POT 0 REGISTER b5 10100001 SLAVE ACK DATA SLAVE POT SETTING MASTER NACK ACK STOP DATA DATA SLAVE ACK SLAVE ACK A1h REPEATED START STOP 10100001 STOP DATA SLAVE ACK DATA MASTER ACK MASTER NACK STOP *THE ADDRESS DETERMINED BY A0, A1, AND A2 MUST MATCH THE ADDRESS SET BY THE ADDRESS PINS. Figure 6. Example 2-Wire Transactions Applications Information Power Supply Decoupling To achieve the best results when using the DS3930, decouple the power supply with a 0.1µF high-quality, ceramic, surface-mount capacitor. Surface-mount com- ponents minimize lead inductance, which improves performance, and ceramic capacitors tend to have adequate high-frequency response for decoupling applications. The capacitor should be placed as close as possible to the VCC and GND pins. ____________________________________________________________________ 11 DS3930 Hex Nonvolatile Potentiometer with I/O and Memory Wiper Resistance One difference between digital potentiometers and mechanical potentiometers is the wiper resistance. The wiper resistance (RW) is a result of the interconnecting materials on the IC between the internal resistive elements and the wiper pin. This can be modeled by using an ideal potentiometer, with a resistance of RW connected between the ideal wiper and wiper terminal of the digital potentiometer. Chip Information TRANSISTOR COUNT: 27,000 SUBSTRATE CONNECTED TO GROUND. Package Information For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.