Preliminary Datasheet R1EV24002ASAS0A Two-wire serial interface 2k EEPROM (256-word 8-bit) R10DS0101EJ0100 Rev.1.00 Apr. 25, 2012 Description R1EV24xxx series are two-wire serial interface EEPROM (Electrically Erasable and Programmable ROM). They realize high speed, low power consumption and a high level of reliability by employing advanced MONOS memory technology and CMOS process and low voltage circuitry technology. They also have a 8-byte page programming function to make their write operation faster. Note: Renesas Electronics’ serial EEPROM are authorized for using consumer applications such as cellular phone, camcorders, audio equipment. Therefore, please contact Renesas Electronics’ sales office before using industrial applications such as automotive systems, embedded controllers, and meters. Features Single supply: 2.5 V to 5.5 V Two-wire serial interface (I2C serial bus) Clock frequency: 400 kHz Power dissipation: Standby: 2 A (max) Active (Read): 1 mA (max) Active (Write): 2.5 mA (max) Automatic page write: 8-byte/page Write cycle time: 5 ms Endurance: 1,000k Cycles @25C Data retention: 100 Years @25C Small size packages: SOP-8pin Shipping tape and reel SOP 8-pin: 4,000 IC/reel Temperature range: 40 to +85C Lead free products. Preliminary: The specifications of this device are subject to change without notice. Please contact your nearest Renesas Electronics’ Sales Dept. regarding specifications. R10DS0101EJ0100 Rev.1.00 Apr. 25, 2012 Page 1 of 15 R1EV24002ASAS0A Preliminary Ordering Information Orderable Part Numbers R1EV24002ASAS0A#K0 Internal organization 2k bit (256 8-bit) Package 150 mil 8-pin plastic SOP PRSP0008DF-B (FP-8DBV) Lead free Shipping tape and reel 4,000 IC/reel Pin Arrangement 8-pin SOP A0 1 8 VCC A1 2 7 WP A2 3 6 SCL VSS 4 5 SDA (Top view) Pin Description Pin name Function A0 to A2 SCL SDA WP VCC VSS Device address Serial clock input Serial data input/output Write protect Power supply Ground Block Diagram High voltage generator A0, A1, A2 SCL Control logic X decoder WP Address generator VSS Memory array Y decoder VCC Y-select & Sense amp. SDA Serial-parallel converter R10DS0101EJ0100 Rev.1.00 Apr. 25, 2012 Page 2 of 15 R1EV24002ASAS0A Preliminary Absolute Maximum Ratings Parameter Supply voltage relative to VSS Input voltage relative to VSS Operating temperature range*1 Storage temperature range Symbol VCC Vin Topr Tstg Value 0.6 to +7.0 0.5*2 to +7.0*3 40 to +85 55 to +125 Unit V V C C Notes: 1. Including electrical characteristics and data retention. 2. Vin (min): 3.0 V for pulse width 50 ns. 3. Should not exceed VCC + 1.0 V. DC Operating Conditions Parameter Symbol VCC VSS VIH VIL Topr Supply voltage Input high voltage Input low voltage Operating temperature Note: Min 2.5 0 VCC 0.7 0.3*1 40 Typ 0 Max 5.5 0 VCC + 0.5 VCC 0.3 +85 Unit V V V V C 1. VIL (min): 1.0 V for pulse width 50 ns. DC Characteristics (Ta = 40 to +85C, VCC = 2.5 V to 5.5 V) Parameter Input leakage current Output leakage current Standby VCC current Read VCC current Write VCC current Output low voltage Symbol ILI ILO ISB ICC1 ICC2 VOL Min Typ 1.0 Max 2.0 2.0 2.0 1.0 2.5 0.4 Unit A A A mA mA V Test conditions VCC = 5.5 V, Vin = 0 to 5.5 V VCC = 5.5 V, Vout = 0 to 5.5 V Vin = VSS or VCC VCC = 5.5 V, Read at 400 kHz VCC = 5.5 V, Write at 400 kHz IOL = 3.0 mA Capacitance (Ta = +25C, f = 1 MHz) Parameter Input capacitance (A0 to A2, SCL, WP) Output capacitance (SDA) Note: Symbol Cin*1 CI/O*1 Min Typ Max 6.0 6.0 Unit pF pF Test conditions Vin = 0 V Vout = 0 V 1. Not 100 tested. Memory cell characteristics (VCC = 2.5 V to 5.5 V) Endurance Data retention Note: Ta=25C 1,000k Cycles min. 100 Years min. Ta=85C 100k Cycles min 10 Years min. Notes 1 1 1. Not 100 tested. R10DS0101EJ0100 Rev.1.00 Apr. 25, 2012 Page 3 of 15 R1EV24002ASAS0A Preliminary AC Characteristics (Ta = 40 to +85C, VCC = 2.5 to 5.5 V) Test Conditions Input pules levels: VIL = 0.2 VCC VIH = 0.8 VCC Input rise and fall time: 20 ns Input and output timing reference levels: 0.5 VCC Output load: TTL Gate + 100 pF Parameter Clock frequency Clock pulse width low Clock pulse width high Noise suppression time Access time Bus free time for next mode Start hold time Start setup time Data in hold time Data in setup time Input rise time Input fall time Stop setup time Data out hold time Write protect hold time Write protect setup time Write cycle time Symbol fSCL tLOW tHIGH tI tAA tBUF tHD.STA tSU.STA tHD.DAT Min 1200 600 100 1200 600 600 0 Typ Max 400 50 900 Unit kHz ns ns ns ns ns ns ns ns tSU.DAT tR tF tSU.STO tDH tHD.WP tSU.WP tWC 100 600 50 1200 0 300 300 5 ns ns ns ns ns ns ns ms Notes 1 1 1 2 Notes: 1. Not 100 tested. 2. tWC is the time from a stop condition to the end of internally controlled write cycle. R10DS0101EJ0100 Rev.1.00 Apr. 25, 2012 Page 4 of 15 R1EV24002ASAS0A Preliminary Timing Waveforms Bus Timing tF tHIGH 1/fSCL tLOW tR SCL tSU.STA tHD.DAT tSU.DAT tHD.STA tSU.STO SDA (in) tBUF tAA tDH SDA (out) tSU.WP tHD.WP WP Write Cycle Timing Stop condition Start condition SCL D0 in SDA Write data (Address (n)) R10DS0101EJ0100 Rev.1.00 Apr. 25, 2012 ACK tWC (Internally controlled) Page 5 of 15 R1EV24002ASAS0A Preliminary Pin Function Serial Clock (SCL) The SCL pin is used to control serial input/output data timing. The SCL input is used to positive edge clock data into EEPROM device and negative edge clock data out of each device. Maximum clock rate is 400 kHz. Serial Input/Output Data (SDA) The SDA pin is bidirectional for serial data transfer. The SDA pin needs to be pulled up by resistor as that pin is opendrain driven structure. Use proper resistor value for your system by considering VOL, IOL and the SDA pin capacitance. Except for a start condition and a stop condition which will be discussed later, the SDA transition needs to be completed during the SCL low period. Data Validity (SDA data change timing waveform) SCL SDA Data change Note: Data change High-to-low and low-to-high change of SDA should be done during the SCL low period. Device Address (A0, A1, A2) Eight devices can be wired for one common data bus line as maximum. Device address pins are used to distinguish each device and device address pins should be connected to VCC or VSS . When device address code provided from SDA pin matches corresponding hard-wired device address pins A0 to A2, that one device can be activated. Pin Connections for A0 to A2 Pin connection Memory size 2k bit Note: Max connect number 8 A2 VCC/VSS A1 VCC/VSS A0 VCC/VSS Note 1. During floating, “VCC/VSS” are fixed to VSS. Write Protect (WP) When the Write Protect pin (WP) is high, the write protection feature is enabled and operates as shown in the following table. Also, acknowledgment "0" is outputted after inputting device address and memory address. After inputting write data, acknowledgment "1"(NO ACK) is outputted. When the WP is low, write operation for all memory arrays are allowed. The read operation is always activated irrespective of the WP pin status. Write Protect Area WP pin status VIH VIL R10DS0101EJ0100 Rev.1.00 Apr. 25, 2012 Write protect area 2k bit Full (2k bit) Normal read/write operation Page 6 of 15 R1EV24002ASAS0A Preliminary Functional Description Start Condition A high-to-low transition of the SDA with the SCL high is needed in order to start read, write operation (See start condition and stop condition). Stop Condition A low-to-high transition of the SDA with the SCL high is a stop condition. The stand-by operation starts after a read sequence by a stop condition. In the case of write operation, a stop condition terminates the write data inputs and place the device in a internally-timed write cycle to the memories. After the internally-timed write cycle which is specified as tWC, the device enters a standby mode (See write cycle timing). Start Condition and Stop Condition SCL SDA (in) Start condition Stop condition Acknowledge All addresses and data words are serially transmitted to and from in 8-bit words. The receiver sends a zero to acknowledge that it has received each word. This happens during ninth clock cycle. The transmitter keeps bus open to receive acknowledgment from the receiver at the ninth clock. In the write operation, EEPROM sends a zero to acknowledge after receiving every 8-bit words. In the read operation, EEPROM sends a zero to acknowledge after receiving the device address word. After sending read data, the EEPROM waits acknowledgment by keeping bus open. If the EEPROM receives zero as an acknowledge, it sends read data of next address. If the EEPROM receives acknowledgment "1" (no acknowledgment) and a following stop condition, it stops the read operation and enters a stand-by mode. If the EEPROM receives neither acknowledgment "0" nor a stop condition, the EEPROM keeps bus open without sending read data. Acknowledge Timing Waveform SCL SDA IN 1 2 8 9 Acknowledge out SDA OUT R10DS0101EJ0100 Rev.1.00 Apr. 25, 2012 Page 7 of 15 R1EV24002ASAS0A Preliminary Device Addressing The EEPROM device requires an 8-bit device address word following a start condition to enable the chip for a read or a write operation. The device address word consists of 4-bit device code, 3-bit device address code and 1-bit read/write(R/W) code. The most significant 4-bit of the device address word are used to distinguish device type and this EEPROM uses “1010” fixed code. The device address word is followed by the 3-bit device address code A2, A1, A0. The device address code selects one device out of eight devices which are connected to the bus. This means that the device is selected if the inputted 3-bit device address code is equal to the corresponding hard-wired A2 to A0 pins status. The eighth bit of the device address word is the read/write(R/W) bit. A write operation is initiated if this bit is “0” and a read operation is initiated if this bit is “1”. The EEPROM turns to a stand-by state if the device code is not “1010” or device address code doesn’t coincide with status of the correspond hard-wired device address pins. Device Address Word 2k Note: 1 Device address word (8-bit) Device code (fixed) Device address code 0 1 0 A2 A1 A0 R/W code*1 R/W 1. R/W=“1” is read and R/W = “0” is write. R10DS0101EJ0100 Rev.1.00 Apr. 25, 2012 Page 8 of 15 R1EV24002ASAS0A Preliminary Write Operations (WP=Low) Byte Write: (Write operation during WP=Low status) A write operation requires an 8-bit device address word with R/W = “0”. Then the EEPROM sends acknowledgment "0" at the ninth clock cycle. After these, the 2k bit EEPROM receives 8-bit memory address words. Upon receipt of this memory address, the EEPROM outputs acknowledgment "0" and receives a following 8-bit write data. After receipt of write data, the EEPROM outputs acknowledgment "0". If the EEPROM receives a stop condition, the EEPROM enters an internally-timed write cycle and terminates receipt of SCL, SDA inputs until completion of the write cycle. The EEPROM returns to a standby mode after completion of the write cycle. Byte Write Operation WP 1010 W ACK ACK R/W Start Write data (n) D7 D6 D5 D4 D3 D2 D1 D0 2k Memory address a7 a6 a5 a4 a3 a2 a1 a0 Device address ACK Stop Page Write: The EEPROM is capable of the page write operation which allows any number of bytes up to 8 bytes to be written in a single write cycle. The page write is the same sequence as the byte write except for inputting the more write data. The page write is initiated by a start condition, device address word, memory address(n) and write data (Dn) with every ninth bit acknowledgment. The EEPROM enters the page write operation if the EEPROM receives more write data (Dn+1) instead of receiving a stop condition. The a0 to a2 address bits are automatically incremented upon receiving write data (Dn+1). The EEPROM can continue to receive write data up to 8 bytes. If the a0 to a2 address bits reaches the last address of the page, the a0 to a2 address bits will roll over to the first address of the same page and previous write data will be overwritten. Upon receiving a stop condition, the EEPROM stops receiving write data and enters internally-timed write cycle. Page Write Operation WP Start R10DS0101EJ0100 Rev.1.00 Apr. 25, 2012 W ACK R/W ACK Write data (n+m) D5 D4 D3 D2 D1 D0 1010 Write data (n) D7 D6 D5 D4 D3 D2 D1 D0 2k Memory address a7 a6 a5 a4 a3 a2 a1 a0 Device address ACK ACK Stop Page 9 of 15 R1EV24002ASAS0A Preliminary Write Operations (WP=High) Byte Write: (Write operation during WP=High status) A write operation requires an 8-bit device address word with R/W = “0”. Then the EEPROM sends acknowledgment "0" at the ninth clock cycle. After these, the 2k bit EEPROM receives 8-bit memory address. Upon receipt of this memory address, the EEPROM outputs acknowledgment "0". After receipt of 8-bit write data, the EEPROM outputs acknowledgment "1"(NO ACK). Then the EEPROM write operations are not allowed. Byte Write Operation WP 1010 W ACK R/W Start Write data (n) No ACK D7 D6 D5 D4 D3 D2 D1 D0 2k Memory address a7 a6 a5 a4 a3 a2 a1 a0 Device address ACK Stop Page Write: The page write is the same sequence as the byte write. The page write is initiated by a start condition, device address word and memory address(n) with every ninth bit acknowledgment"0". But after inputting write data(Dn) , the EEPROM outputs acknowledgment "1"(NO ACK). Then the EEPROM write operations are not allowed. Page Write Operation WP Start R10DS0101EJ0100 Rev.1.00 Apr. 25, 2012 W ACK R/W No ACK No ACK Write data (n+m) D5 D4 D3 D2 D1 D0 1010 Write data (n) D7 D6 D5 D4 D3 D2 D1 D0 2k Memory address a7 a6 a5 a4 a3 a2 a1 a0 Device address ACK Stop Page 10 of 15 R1EV24002ASAS0A Preliminary Acknowledge Polling: Acknowledge polling feature is used to show if the EEPROM is in a internally-timed write cycle or not. This feature is initiated by the stop condition after inputting write data. This requires the 8-bit device address word following the start condition during a internally-timed write cycle. Acknowledge polling will operate when the R/W code = “0”. Acknowledgment “1” (no acknowledgment) shows the EEPROM is in a internally-timed write cycle and acknowledgment “0” shows that the internally-timed write cycle has completed. See Write Cycle Polling using ACK. Write Cycle Polling Using ACK Send write command Send stop condition to initiate write cycle Send start condition Send device address word with R/W = 0 ACK returned No Yes Next operation is addressing the memory No Yes Proceed write operation R10DS0101EJ0100 Rev.1.00 Apr. 25, 2012 Send memory address Send start condition Proceed random address read operation Send stop condition Send stop condition Page 11 of 15 R1EV24002ASAS0A Preliminary Read Operation There are three read operations: current address read, random read, and sequential read. Read operations are initiated the same way as write operations with the exception of R/W = “1”. Current Address Read: The internal address counter maintains the last address accessed during the last read or write operation, with incremented by one. Current address read accesses the address kept by the internal address counter. After receiving a start condition and the device address word (R/W is “1”), the EEPROM outputs the 8-bit current address data from the most significant bit following acknowledgment “0”. If the EEPROM receives acknowledgment “1” (no acknowledgment) and a following stop condition, the EEPROM stops the read operation and is turned to a standby state. In case the EEPROM has accessed the last address of the last page at previous read operation, the current address will roll over and returns to zero address. In case the EEPROM has accessed the last address of the page at previous write operation, the current address will roll over within page addressing and returns to the first address in the same page. The current address is valid while power is on. The current address after power on will be indefinite. The random read operation described below is necessary to define the memory address. Current Address Read Operation Device address Start R10DS0101EJ0100 Rev.1.00 Apr. 25, 2012 1010 R D7 D6 D5 D4 D3 D2 D1 D0 2k Read data (n+1) ACK R/W No ACK Stop Page 12 of 15 R1EV24002ASAS0A Preliminary Random Read: This is a read operation with defined read address. A random read requires a dummy write to set read address. The EEPROM receives a start condition, device address word (R/W=0) and memory address 8-bit sequentially. The EEPROM outputs acknowledgment “0” after receiving memory address then enters a current address read with receiving a start condition. The EEPROM outputs the read data of the address which was defined in the dummy write operation. After receiving acknowledgment “1”(no acknowledgment) and a following stop condition, the EEPROM stops the random read operation and returns to a standby state. Random Read Operation 1010 @@@ a7 a6 a5 a4 a3 a2 a1 a0 2k Memory address W ACK R/W Start Device address 1010 Start ACK Dummy write Read data (n) # # # R R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 Device address No ACK Stop Current address read Notes: 1. 2nd device address code (#) should be same as 1st (@). Sequential Read: Sequential reads are initiated by either a current address read or a random read. If the EEPROM receives acknowledgment “0” after 8-bit read data, the read address is incremented and the next 8-bit read data are coming out. This operation can be continued as long as the EEPROM receives acknowledgment “0”. The address will roll over and returns address zero if it reaches the last address of the last page. The sequential read can be continued after roll over. The sequential read is terminated if the EEPROM receives acknowledgment “1” (no acknowledgment) and a following stop condition. Sequential Read Operation Start R10DS0101EJ0100 Rev.1.00 Apr. 25, 2012 ACK R/W D7 D6 D5 D4 D3 D2 D1 D0 R D7 D6 D5 D4 D3 D2 D1 D0 1010 2k Read data (n+1) Read data (n+2) ACK ACK Read data (n+m) D5 D4 D3 D2 D1 D0 Device address No ACK Stop Page 13 of 15 R1EV24002ASAS0A Preliminary Notes Data Protection at VCC On/Off When VCC is turned on or off, noise on the SCL and SDA inputs generated by external circuits (CPU, etc) may act as a trigger and turn the EEPROM to unintentional program mode. To prevent this unintentional programming, this EEPROM has a power on reset function. Be careful of the notices described below in order for the power on reset function to operate correctly. SCL and SDA should be fixed to VCC or VSS during VCC on/off. Low to high or high to low transition during VCC on/off may cause the trigger for the unintentional programming. VCC should be turned off after the EEPROM is placed in a standby state. VCC should be turned on from the ground level(VSS) in order for the EEPROM not to enter the unintentional programming mode. VCC turn on rate should be slower than 2 s/V. Noise Suppression Time This EEPROM have a noise suppression function at SCL and SDA inputs, that cut noise of width less than 50 ns. Be careful not to allow noise of width more than 50 ns. Power Source Noise Countermeasures In order to suppress power-source-noise which causes malfunction of the device, it is recommended to put 0.1uF bypass-capacitor (such as a monolithic ceramic capacitor which has good high-frequency characteristics) between VCC and VSS, and shorten the wiring length between the capacitor and VCC/VSS terminals as much as possible. R10DS0101EJ0100 Rev.1.00 Apr. 25, 2012 Page 14 of 15 R1EV24002ASAS0A Preliminary Package Dimensions R1EV24002ASAS0A (PRSP0008DF-B / Previous Code: FP-8DBV) JEITA Package Code P-SOP8-3.9x4.89-1.27 RENESAS Code PRSP0008DF-B *1 Previous Code FP-8DBV D MASS[Typ.] 0.08g NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. F 8 5 *2 c E HE bp Index mark Terminal cross section Reference Symbol (Ni/Pd/Au plating) 4 1 Z *3 e bp x M A L1 A1 θ S y S R10DS0101EJ0100 Rev.1.00 Apr. 25, 2012 L Detail F Dimension in Millimeters Min Nom Max D 4.89 5.15 E 3.90 A2 A1 0.102 0.14 0.254 A 1.73 bp 0.35 0.40 0.45 b1 c 0.15 0.20 0.25 c1 θ 0° 8° HE 5.84 6.02 6.20 e 1.27 x 0.25 y 0.10 Z 0.69 L 0.406 0.60 0.889 L1 1.06 Page 15 of 15 Revision History Rev. 0.01 0.02 1.00 Date Oct. 11, 2011 Jan. 13, 2012 Apr. 25, 2012 R1EV24002ASAS0A Data Sheet Description Summary Page 15 All Initial issue Corrected typo. 2 s/s 2 s/V Delete Preliminary All trademarks and registered trademarks are the property of their respective owners. C-1 Notice 1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. 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