19-6313; Rev 0; 5/12 MAX5825PMB1 Peripheral Module General Description The MAX5825PMB1 peripheral module provides the necessary hardware to interface the MAX5825 8-channel DAC to any system that utilizes PmodK-compatible expansion ports configurable for I2C communication. The IC features eight independent 12-bit accurate internally buffered voltage-output DAC channels. The IC also features an internal reference that is selectable between 2.048V, 2.500V, and 4.096V (4.096V reference operation is not supported with a standard 3.3V Pmod-port power supply). Features S Eight High-Accuracy DAC Channels S 12-Bit Accuracy without Adjustment S Precision Voltage Reference Internal to the IC S Provision for Optional External Reference Input S Jumper-Selectable I2C Address Setting S 6-Pin Pmod-Compatible Connector (I2C) S Secondary Header Allows Daisy-Chaining of Additional Modules on the I2C Bus S Example Software Written in C for Portability S RoHS Compliant S Proven PCB Layout S Fully Assembled and Tested Ordering Information appears at end of data sheet. MAX5825PMB1 Peripheral Module Pmod is a trademark of Digilent Inc. __________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. MAX5825PMB1 Peripheral Module Component List DESIGNATION QTY DESCRIPTION DESIGNATION QTY DESCRIPTION 1 8-pin (2 x 4) straight male header C1 1 10FF Q10%, 10V X5R ceramic capacitor (0603) TDK C2012X5R1A106K/1.25 J2 J3 1 14-pin (2 x 7) straight male header 2 3-pin straight male headers 1 2.2FF Q10%, 10V X5R ceramic capacitor (0603) TDK C1608X5R1A225K/0.80 JP1, JP2 C2 R1–R4 4 150I Q5% resistors (0603) R5–R9 5 4.7kI Q5% resistors (0603) 2 0.1FF Q10%, 16V X7R ceramic capacitors (0603) Murata GRM188R71C104KA01D R10 0 Not installed, 100kI resistor (0603) U1 1 F1 1 4.7FF EMI filter (3-terminal capacitor) Murata NFM21PC475B1A3D Octal-channel, 12-bit buffered DAC (20 TSSOP) Maxim MAX5825AAUP+ — 2 Shorting jumpers J1 1 6-pin right-angle male header — 1 PCB: EPCB5825PM1 C3, C4 Component Suppliers SUPPLIER PHONE WEBSITE Murata Electronics North America, Inc. 770-436-1300 www.murata-northamerica.com TDK Corp. 847-803-6100 www.component.tdk.com Note: Indicate that you are using the MAX5825PMB1 when contacting these component suppliers. Detailed Description I2C Interface The MAX5825PMB1 peripheral module can interface to the host in one of two ways. It can plug directly into a Pmod-compatible port (configured for I2C) through connector J1, or in this case, other I2C boards can attach to the same I2C bus through connector J2. I2C Interface (Daisy-Chaining Modules) Alternatively, the peripheral module can connect to other I2C-based Pmod modules using a 4-conductor ribbon cable connecting to the J2 connector. In this situation, pins 1-4 and 5-8 on J2 provide two connections to the I2C bus, allowing the module to be inserted into an I2C bus daisy-chain. Connector J1 provides connection of the module to the Pmod host. The pin assignments and functions adhere to the Pmod standard recommended by Digilent. See Table 1. The J2 connector allows the module to be connected through a daisy-chain from another I2C module and/or provide I2C and power connections to other I2C modules on the same bus. See Table 2. Table 1. Connector J1 (I2C Communication) PIN SIGNAL DESCRIPTION 1 LDAC Active-low asynchronous DAC load input 2 IRQ Active-low open-drain interrupt output. IRQ low indicates a watchdog timeout. 3 SCL I2C serial clock 4 SDA I2C serial data 5 GND Ground 6 VDD Power supply Table 2. Connector J2 (I2C Expansion) PIN SIGNAL 1 SCL I2C serial clock DESCRIPTION 2 SDA I2C serial data 3 GND Ground 4 VDD Power supply 5 SCL 2-wire serial clock. Same as pin 1 above. 6 SDA 2-wire serial data. Same as pin 2 above. 7 GND Ground 8 VDD Power supply __________________________________________________________________ Maxim Integrated Products 2 MAX5825PMB1 Peripheral Module I2C Addressing Options The I2C slave address for the IC can be one of nine different values, depending on the settings on jumpers JP1 and JP2. Table 3 lists the settings of those jumpers and the corresponding values of the slave address A[3:0]. Refer to the MAX5823/MAX5824/MAX5825 IC data sheet for more information. External Control Signals The IC implements pins that allow asynchronously updating of all DAC channels simultaneously (LDAC) and simultaneously clearing all DAC channels to their default state (CLR). The CLR pin is only available through the external J3 connector. The LDAC signal is available from either the Pmod connector (J1) or the external connector (J3). The default source for LDAC is the Pmod connector (J1). To control LDAC from the external connector (J3), modify the solder link on the back of the board (labeled LK1). The user is cautioned to ensure that only one source for this signal is selected at any given time. The J3 connector provides the DAC output voltages and the external control inputs. See Table 4. Reset State (M/Z Pin) The IC features a pin-selectable DAC reset state using the M/Z input. Upon a power-on reset, all CODE and DAC data registers are reset to zero scale (M/Z = GND) or midscale (M/Z = VDD). The board is shipped with R11 installed (0I) and R10 not installed, which sets M/Z to GND. To change to M/Z = VDD, remove R11 and install a suitable pullup resistor for R10. Refer to the MAX5823/ MAX5824/MAX5825 IC data sheet for more information. Table 3. I2C Slave Address LSBs Software and FPGA Code Example software and drivers are available that execute directly without modification on several FPGA development boards that support an integrated or synthesized microprocessor. These boards include the Digilent Nexys 3, Avnet LX9, and Avnet ZEDBoard, although other platforms can be added over time. Maxim provides complete Xilinx ISE projects containing HDL, Platform Studio, and SDK projects. In addition, a synthesized bit stream, ready for FPGA download, is provided for the demonstration application. The software project (for the SDK) contains several source files intended to accelerate customer evaluation and design. These include a base application (maximModules.c) that demonstrates module functionality and uses an API interface (maximDeviceSpecific Utilities.c) to set and access Maxim device functions within a specific module. The source code is written in standard ANSI C format, and all API documentation including theory/operation, register description, and function prototypes are documented in the API interface file (maximDeviceSpecificUtilities.h & .c). The complete software kit is available for download at www.maxim-ic.com. Quick start instructions are also available as a separate document. Table 4. Connector J3 (External Interface) PIN SIGNAL 1 VDD DESCRIPTION 2 LDACEXT 3 GND Ground 4 CLR Active-low asynchronous DAC clear input Supply voltage Active-low asynchronous DAC load input JP1 (ADDR1) JP2 (ADDR0) A3 A2 A1 A0 1-2 (VDD) 1-2 (VDD) 1 1 1 1 1-2 (VDD) Open 1 1 1 0 5 DAC7 DAC channel 7 voltage output 1-2 (VDD) 2-3 (GND) 1 1 0 0 6 DAC6 DAC channel 6 voltage output Open 1-2 (VDD) 1 0 1 1 7 DAC5 DAC channel 5 voltage output Open Open 1 0 1 0 8 DAC4 DAC channel 4 voltage output Open 2-3 (GND) 1 0 0 0 9 DAC3 DAC channel 3 voltage output 2-3 (GND) 1-2 (VDD) 0 0 1 1 10 DAC2 DAC channel 2 voltage output 2-3 (GND) Open 0 0 1 0 11 DAC1 DAC channel 1 voltage output 2-3 (GND) 2-3 (GND) 0 0 0 0 12 DAC0 DAC channel 0 voltage output 13 REF Reference voltage input/output 14 GND Ground __________________________________________________________________ Maxim Integrated Products 3 MAX5825PMB1 Peripheral Module R1 R2 R3 R4 1 2 3 4 5 6 I2C Expansion Connector 150 LDAC 150 IRQ 150 SCL 150 SDA GND R5 4.7k J2 1 2 3 4 5 6 7 8 F1 EMIFILT 1 R6 4.7k 3 GND C2 U1 VDD R7 4.7k R9 4.7k R8 4.7k LK1 LINKB VDD Do Not Install R10 100k GND R11 10 11 VDD Select LDAC Source 0 GND 19 LDAC 18 SDA 15 SCL 14 CLR 17 IRQ 16 20 13 VDD GND 1 2 3 MAX5825 GND C3 0.1uF VDD VDDIO GND DAC0 DAC1 DAC2 12 JP1 2.2uF VDD C4 0.1uF LDACEXT GND VDD VDD GND LDAC VDD C1 10uF 2 J1 LDAC SDA SCL CLR IRQ DAC3 DAC4 DAC5 DAC6 DAC7 2 DAC0 3 DAC1 4 DAC2 5 DAC3 6 DAC4 7 DAC5 8 DAC6 9 DAC7 1 REF VDD GND DAC7 DAC5 DAC3 DAC1 REF J3 1 3 5 7 9 11 13 2 4 6 8 10 12 14 LDACEXT CLR DAC6 DAC4 DAC2 DAC0 GND Output Connector M/Z ADDR1 REF ADDR0 JP2 VDD GND 1 2 3 I2C Address Selection Figure 1. MAX5825PMB11 Peripheral Module Schematic __________________________________________________________________ Maxim Integrated Products 4 MAX5825PMB1 Peripheral Module Figure 2. MAX5825PMB11 Peripheral Module Component Placement Guide—Component Side Figure 3. MAX5825PMB11 Peripheral Module PCB Layout—Component Side Figure 4. MAX5825PMB11 Peripheral Module PCB Layout—Inner Layer 1 (Ground) __________________________________________________________________ Maxim Integrated Products 5 MAX5825PMB1 Peripheral Module Figure 5. MAX5825PMB11 Peripheral Module PCB Layout—Inner Layer 2 (Power) Figure 6. MAX5825PMB11 Peripheral Module PCB Layout—Solder Side Figure 7. MAX5825PMB11 Peripheral Module Component Placement Guide—Solder Side __________________________________________________________________ Maxim Integrated Products 6 MAX5825PMB1 Peripheral Module Ordering Information PART TYPE MAX5825PMB1# Peripheral Module #Denotes RoHS compliant. __________________________________________________________________ Maxim Integrated Products 7 MAX5825PMB1 Peripheral Module Revision History REVISION NUMBER REVISION DATE 0 5/12 DESCRIPTION Initial release PAGES CHANGED — Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2012 Maxim Integrated Products 8 Maxim is a registered trademark of Maxim Integrated Products, Inc.