TI TPS73233DCQG4

TPS732xx
www.ti.com
SBVS037L – AUGUST 2003 – REVISED AUGUST 2007
Cap-Free, NMOS, 250mA Low Dropout Regulator
with Reverse Current Protection
FEATURES
DESCRIPTION
1
• Stable with No Output Capacitor or Any Value
or Type of Capacitor
• Input Voltage Range: 1.7V to 5.5V
• Ultralow Dropout Voltage: 40mV Typ at 250mA
• Excellent Load Transient Response—with or
without Optional Output Capacitor
• New NMOS Topology Provides Low Reverse
Leakage Current
• Low Noise: 30µVRMS Typ (10kHz to 100kHz)
• 0.5% Initial Accuracy
• 1% Overall Accuracy (Line, Load, and
Temperature)
• Less Than 1µA Max IQ in Shutdown Mode
• Thermal Shutdown and Specified Min/Max
Current Limit Protection
• Available in Multiple Output Voltage Versions
– Fixed Outputs of 1.20V to 5.0V
– Adjustable Outputs from 1.20V to 5.5V
– Custom Outputs Available
2
The TPS732xx uses an advanced BiCMOS process
to yield high precision while delivering very low
dropout voltages and low ground pin current. Current
consumption, when not enabled, is under 1µA and
ideal for portable applications. The extremely low
output noise (30µVRMS with 0.1µF CNR) is ideal for
powering VCOs. These devices are protected by
thermal shutdown and foldback current limit.
DRB PACKAGE
3mmx 3mm SON
(TOP VIEW)
OUT 1
Portable/Battery-Powered Equipment
Post-Regulation for Switching Supplies
Noise-Sensitive Circuitry such as VCOs
Point of Load Regulation for DSPs, FPGAs,
ASICs, and Microprocessors
8 IN
7 N/C
IN
1
NR/FB 3
6 N/C
GND
2
EN
3
5 EN
VIN
5
OUT
4
NR/FB
DCQ PACKAGE
SOT223
(TOP VIEW)
TAB IS GND
6
1
Optional
DBV PACKAGE
SOT23
(TOP VIEW)
N/C 2
GND 4
APPLICATIONS
•
•
•
•
The TPS732xx family of low-dropout (LDO) voltage
regulators uses a new topology: an NMOS pass
element in a voltage-follower configuration. This
topology is stable using output capacitors with low
ESR, and even allows operation without a capacitor.
It also provides high reverse blockage (low reverse
current) and ground pin current that is nearly constant
over all values of output current.
2
3
4
5
Optional
IN
VOUT
OUT
IN
TPS732xx
EN
GND
NR
GND
EN
OUT NR/FB
Optional
Typical Application Circuit for Fixed-Voltage Versions
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2007, Texas Instruments Incorporated
TPS732xx
www.ti.com
SBVS037L – AUGUST 2003 – REVISED AUGUST 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
VOUT (2)
PRODUCT
XX is nominal output voltage (for example, 25 = 2.5V, 01 = Adjustable (3)).
YYY is package designator.
Z is package quantity.
TPS732xxyyyz
(1)
(2)
(3)
For the most current specification and package information, refer to the Package Option Addendum located at the end of this datasheet
or see the TI website at www.ti.com.
Most output voltages of 1.25V and 1.3V to 5.0V in 100mV increments are available through the use of innovative factory EEPROM
programming; minimum order quantities may apply. Contact factory for details and availability.
For fixed 1.20V operation, tie FB to OUT.
ABSOLUTE MAXIMUM RATINGS
over operating junction temperature range unless otherwise noted (1)
TPS732xx
UNIT
VIN range
–0.3 to 6.0
V
VEN range
–0.3 to 6.0
V
VOUT range
–0.3 to 5.5
V
VNR, VFB range
–0.3 to 6.0
V
Peak output current
Internally limited
Output short-circuit duration
Indefinite
Continuous total power dissipation
See Dissipation Ratings Table
Junction temperature range, TJ
–55 to +150
°C
Storage temperature range
–65 to +150
°C
ESD rating, HBM
2
kV
ESD rating, CDM
500
V
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
POWER DISSIPATION RATINGS (1)
BOARD
PACKAGE
RΘJC
RΘJA
DERATING FACTOR
ABOVE TA = 25°C
TA ≤ 25°C
POWER RATING
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
Low-K (2)
DBV
64°C/W
255°C/W
3.9mW/°C
390mW
215mW
155mW
DBV
64°C/W
180°C/W
5.6mW/°C
560mW
310mW
225mW
Low-K (2)
DCQ
15°C/W
53°C/W
18.9mW/°C
1.89W
1.04W
0.76W
(3)
DCQ
15°C/W
45°C/W
22.2mW/°C
2.22W
1.22W
0.89W
DRB
1.2°C/W
40C/W
25.0mW/°C
2.50W
1.38W
1.0W
High-K
High-K
(3)
High-K (3) (4)
(1)
(2)
(3)
(4)
2
See Power Dissipation in the Applications section for more information related to thermal design.
The JEDEC Low-K (1s) board design used to derive this data was a 3 inch x 3 inch, two-layer board with 2-ounce copper traces on top
of the board.
The JEDEC High-K (2s2p) board design used to derive this data was a 3 inch x 3 inch, multilayer board with 1-ounce internal power and
ground planes and 2-ounce copper traces on the top and bottom of the board.
Based on preliminary thermal simulations.
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SBVS037L – AUGUST 2003 – REVISED AUGUST 2007
ELECTRICAL CHARACTERISTICS
Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5V (1), IOUT = 10mA, VEN = 1.7V, and
COUT = 0.1µF, unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
VIN
Input voltage range (1)
VFB
Internal reference (TPS73201)
MIN
TJ = +25°C
ΔVOUT%/ΔVIN
Accuracy (1) (3)
UNIT
V
1.210
V
VFB
5.5 – VDO
V
+0.5
Nominal
TJ = +25°C
–0.5
VIN, IOUT, and T
VOUT + 0.5V ≤ VIN ≤ 5.5V;
10 mA ≤ IOUT ≤ 250mA
–1.0
Line regulation (1)
MAX
5.5
1.198
Output voltage range (TPS73201) (2)
VOUT
TYP
1.7
VOUT(nom) + 0.5V ≤ VIN ≤ 5.5V
1.20
±0.5
+1.0
0.01
1mA ≤ IOUT ≤ 250mA
0.002
10mA ≤ IOUT ≤ 250mA
0.0005
%
%/V
ΔVOUT%/ΔIOUT
Load regulation
VDO
Dropout voltage (4)
(VIN = VOUT (nom) – 0.1V)
IOUT = 250mA
ZO(DO)
Output impedance in dropout
1.7 V ≤ VIN ≤ VOUT + VDO
ICL
Output current limit
VOUT = 0.9 × VOUT(nom)
ISC
Short-circuit current
VOUT = 0V
300
IREV
Reverse leakage current (5) (–IIN)
VEN ≤ 0.5V, 0V ≤ VIN ≤ VOUT
0.1
10
IOUT = 10mA (IQ)
400
550
IOUT = 250mA
650
950
VEN ≤ 0.5V, VOUT ≤ VIN ≤ 5.5,
–40°C ≤ TJ ≤ +100°C
0.02
1
A
0.1
0.3
µA
40
150
mV
600
mA
Ω
0.25
250
425
IGND
Ground pin current
ISHDN
Shutdown current (IGND)
IFB
FB pin current (TPS73201)
PSRR
Power-supply rejection ratio
(ripple rejection)
f = 100Hz, IOUT = 250 mA
58
f = 10kHz, IOUT = 250 mA
37
VN
Output noise voltage
BW = 10Hz – 100kHz
COUT = 10µF, No CNR
27 × VOUT
COUT = 10µF, CNR = 0.01µF
8.5 × VOUT
tSTR
Startup time
VOUT = 3V, RL = 30Ω
COUT = 1 µF, CNR = 0.01 µF
600
VEN(HI)
Enable high (enabled)
VEN(LO)
Enable low (shutdown)
IEN(HI)
Enable pin current (enabled)
TSD
Thermal shutdown temperature
TJ
Operating junction temperature
(1)
(2)
(3)
(4)
(5)
%/mA
1.7
0.02
Shutdown
Temp increasing
+160
Reset
Temp decreasing
+140
–40
µA
µA
dB
µVRMS
µs
VIN
0
VEN = 5.5V
mA
V
0.5
V
0.1
µA
°C
+125
°C
Minimum VIN = VOUT + VDO or 1.7V, whichever is greater.
TPS73201 is tested at VOUT = 2.5V.
Tolerance of external resistors not included in this specification.
VDO is not measured for fixed output versions with VOUT(nom) < 1.8V since minimum VIN = 1.7V.
Fixed-voltage versions only; refer to Applications section for more information.
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FUNCTIONAL BLOCK DIAGRAMS
IN
4MHz
Charge Pump
EN
Thermal
Protection
Ref
Servo
27kΩ
Bandgap
Error
Amp
Current
Limit
OUT
8kΩ
GND
R1
R1 + R2 = 80kΩ
R2
NR
Figure 1. Fixed Voltage Version
IN
Table 1. Standard 1%
Resistor Values for
Common Output Voltages
VO
4MHz
Charge Pump
EN
Thermal
Protection
Ref
Servo
27kΩ
Bandgap
Error
Amp
GND
8kΩ
R2
1.2V
Short
Open
1.5V
23.2kΩ
95.3kΩ
1.8V
28.0kΩ
56.2kΩ
2.5V
39.2kΩ
36.5kΩ
2.8V
44.2kΩ
33.2kΩ
3.0V
46.4kΩ
30.9kΩ
3.3V
52.3kΩ
30.1kΩ
NOTE: VOUT = (R1 + R2)/R2 × 1.204;
R1R2 ≅ 19kΩ for best
accuracy.
OUT
Current
Limit
R1
80kΩ
R1
FB
R2
Figure 2. Adjustable Voltage Version
4
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SBVS037L – AUGUST 2003 – REVISED AUGUST 2007
PIN ASSIGNMENTS
IN
5
1
GND
2
EN
3
DRB PACKAGE
3mm x 3mm SON
(TOP VIEW)
DCQ PACKAGE
SOT223
(TOP VIEW)
DBV PACKAGE
SOT23
(TOP VIEW)
4
TAB IS GND
6
OUT
NR/FB
1
IN
2
3
4
OUT
1
8
IN
N/C
2
7
N/C
NR/FB
3
6
N/C
GND
4
5
EN
5
GND
EN
OUT
NR/FB
TERMINAL FUNCTIONS
TERMINAL
SOT23
(DBV)
PIN NO.
SOT223
(DCQ)
PIN NO.
3×3 SON
(DRB)
PIN NO.
IN
1
1
8
GND
2
3, 6
4, Pad
EN
3
5
5
Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the
regulator into shutdown mode. Refer to the Shutdown section under Applications
Information for more details. EN can be connected to IN if not used.
NR
4
4
3
Fixed voltage versions only—connecting an external capacitor to this pin bypasses
noise generated by the internal bandgap, reducing output noise to very low levels.
FB
4
4
3
Adjustable voltage version only—this is the input to the control loop error amplifier,
and is used to set the output voltage of the device.
OUT
5
2
1
Output of the Regulator. There are no output capacitor requirements for stability.
NAME
DESCRIPTION
Input supply
Ground
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TYPICAL CHARACTERISTICS
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1µF, unless otherwise
noted.
LOAD REGULATION
LINE REGULATION
0.5
0.20
Referred to IOUT = 10mA
−40_C
+25_C
+125_C
Change in VOUT (%)
0.3
0.2
0.1
0
−0.1
−0.2
−0.3
Referred to VIN = VOUT + 0.5V at IOUT = 10mA
0.15
Change in VOUT (%)
0.4
0.10
+25_ C
+125_C
0.05
0
−0.05
−40_ C
−0.10
−0.15
−0.4
−0.5
−0.20
0
50
100
150
200
0
250
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VIN − VOUT (V)
IOUT (mA)
Figure 3.
Figure 4.
DROPOUT VOLTAGE
vs OUTPUT CURRENT
DROPOUT VOLTAGE
vs TEMPERATURE
100
100
TPS73225DBV
80
80
TPS73225DBV
IOUT = 250mA
60
VDO (mV)
VDO (mV)
+125_ C
+25_ C
40
60
40
20
20
−40_C
0
−50
0
0
50
100
150
200
250
−25
0
25
50
75
100
125
Temperature (_C)
IOUT (mA)
Figure 5.
Figure 6.
OUTPUT VOLTAGE ACCURACY HISTOGRAM
OUTPUT VOLTAGE DRIFT HISTOGRAM
30
18
IOUT = 10mA
16
25
I OUT = 10mA
All Voltage Versions
Percent of Units (%)
Percent of Units (%)
14
20
15
10
12
10
8
6
4
5
2
0
6
−1.0
−0.9
−0.8
−0.7
−0.6
−0.5
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
10
20
30
40
50
60
70
80
90
100
0
VOUT Error (%)
Worst Case dVOUT/dT (ppm/_ C)
Figure 7.
Figure 8.
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TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1µF, unless otherwise
noted.
GROUND PIN CURRENT vs OUTPUT CURRENT
GROUND PIN CURRENT vs TEMPERATURE
1000
800
900
700
IOUT = 250mA
800
600
600
I GND (µA)
I GND (µA)
700
500
400
300
100
50
100
150
200
VIN = 5.5V
VIN = 4V
VIN = 2V
0
−50
250
−25
0
25
50
75
IOUT (mA)
Temperature (_C)
Figure 9.
Figure 10.
GROUND PIN CURRENT IN SHUTDOWN
vs TEMPERATURE
CURRENT LIMIT vs VOUT
(FOLDBACK)
1
100
125
3.0
3.5
500
VENABLE = 0.5V
VIN = VOUT + 0.5V
450
ICL
400
Current Limit (mA)
IGND (µA)
300
100
0
0
400
200
VIN = 5.5V
VIN = 4V
VIN = 2V
200
500
0.1
350
300
ISC
250
200
150
100
50
0.01
−50
TPS73233
0
−25
0
25
50
75
100
125
0
1.0
1.5
2.0
VOUT (V)
Figure 11.
Figure 12.
CURRENT LIMIT vs VIN
2.5
CURRENT LIMIT vs TEMPERATURE
600
600
550
550
500
500
Current Limit (mA)
Current Limit (mA)
0.5
Temperature (_C)
450
400
350
300
450
400
350
300
250
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
250
−50
−25
0
25
50
VIN (V)
Temperature (_ C)
Figure 13.
Figure 14.
75
100
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TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1µF, unless otherwise
noted.
PSRR (RIPPLE REJECTION) vs FREQUENCY
PSRR (RIPPLE REJECTION) vs VIN - VOUT
40
90
IOUT = 100mA
COUT = Any
80
35
30
IOUT = 1mA
COUT = 10µF
60
50
IO = 100mA
CO = 1µF
IOUT = 1mA
C OUT = Any
40
25
PSRR (dB)
Ripple Rejection (dB)
70
IOUT = 1mA
COUT = 1µF
20
15
30
20
IOUT = Any
COUT = 0µF
10
VIN = VOUT + 1V
0
10
100
1k
10k
Frequency = 10kHz
COUT = 10mF
VOUT = 2.5V
IOUT = 100mA
10
I OUT = 100mA
COUT = 10µF
5
0
100k
1M
0
10M
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
Frequency (Hz)
VIN - VOUT (V)
Figure 15.
Figure 16.
NOISE SPECTRAL DENSITY
CNR = 0µF
NOISE SPECTRAL DENSITY
CNR = 0.01µF
1
1.8
2.0
1
eN (µV/√Hz)
eN (µV/√Hz)
C OUT = 1µF
COUT = 0µF
0.1
COUT = 10µF
COUT = 1µF
0.1
COUT = 0µF
COUT = 10µF
IOUT = 150mA
IOUT = 150mA
0.01
0.01
10
100
1k
10k
100k
10
100
1k
Frequency (Hz)
Frequency (Hz)
Figure 17.
Figure 18.
RMS NOISE VOLTAGE vs COUT
10k
100k
RMS NOISE VOLTAGE vs CNR
60
140
50
120
VOUT = 5.0V
VOUT = 5.0V
100
30
VN (RMS)
VN (RMS)
40
VOUT = 3.3V
20
0.1
8
20
CNR = 0.01µF
10Hz < Frequency < 100kHz
1
0
10
VOUT = 3.3V
60
40
VOUT = 1.5V
10
0
80
VOUT = 1.5V
COUT = 0µF
10Hz < Frequency < 100kHz
1p
10p
100p
COUT (µF)
CNR (F)
Figure 19.
Figure 20.
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10n
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TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1µF, unless otherwise
noted.
TPS73233
LOAD TRANSIENT RESPONSE
VIN = 3.8V
TPS73233
LINE TRANSIENT RESPONSE
COUT = 0µF
50mV/tick
IOUT = 250mA
VOUT
COUT = 0µF
50mV/div
COUT = 1µF
50mV/tick
COUT = 10µF
50mV/tick
VOUT
VOUT
VOUT
C OUT = 100µF
50mV/div
= 0.5V/µs
dt
50mA/tick
10mA
4.5V
1V/div
VIN
I OUT
10µs/div
10µs/div
Figure 21.
Figure 22.
TPS73233
TURN-ON RESPONSE
TPS73233
TURN-OFF RESPONSE
RL = 1kΩ
COUT = 0µF
RL = 20Ω
COUT = 10µF
VOUT
R L = 20Ω
C OUT = 1µF
R L = 20Ω
C OUT = 1µF
1V/div
RL = 1kΩ
COUT = 0µF
RL = 20Ω
COUT = 10µF
VOUT
2V
2V
VEN
1V/div
1V/div
0V
0V
VEN
100µs/div
100µs/div
Figure 23.
Figure 24.
TPS73233
POWER UP / POWER DOWN
IENABLE vs TEMPERATURE
10
6
5
4
VIN
VOUT
IENABLE (nA)
3
Volts
dVIN
5.5V
250mA
1V/div
VOUT
2
1
1
0.1
0
−1
−2
50ms/div
0.01
−50
−25
0
25
50
75
100
125
Temperature (°C)
Figure 25.
Figure 26.
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TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1µF, unless otherwise
noted.
TPS73201
IFB vs TEMPERATURE
60
160
55
140
50
120
45
100
I FB (nA)
VN (rms)
TPS73201
RMS NOISE VOLTAGE vs CFB
40
35
30
25
80
60
VOUT = 2.5V
COUT = 0µF
R1 = 39.2kΩ
10Hz < Frequency < 100kHz
20
10p
100p
40
20
1n
10n
0
−50
−25
0
25
50
75
100
CFB (F)
Temperature (_C)
Figure 27.
Figure 28.
TPS73201
LOAD TRANSIENT, ADJUSTABLE VERSION
TPS73201
LINE TRANSIENT, ADJUSTABLE VERSION
CFB = 10nF
R1 = 39.2kΩ
COUT = 0µF
100mV/div
COUT = 0µF
VOUT
100mV/div
VOUT
100mV/div
C OUT = 10µF
100mV/div
COUT = 10µF
125
VOUT = 2.5V
CFB = 10nF
VOUT
VOUT
4.5V
3.5V
250mA
VIN
10mA
IOUT
5µs/div
10µs/div
Figure 29.
10
Figure 30.
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Copyright © 2003–2007, Texas Instruments Incorporated
Product Folder Link(s): TPS732xx
TPS732xx
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SBVS037L – AUGUST 2003 – REVISED AUGUST 2007
APPLICATION INFORMATION
The TPS732xx belongs to a family of new generation
LDO regulators that use an NMOS pass transistor to
achieve ultra-low-dropout performance, reverse
current blockage, and freedom from output capacitor
constraints. These features, combined with low noise
and an enable input, make the TPS732xx ideal for
portable applications. This regulator family offers a
wide selection of fixed output voltage versions and an
adjustable output version. All versions have thermal
and over-current protection, including foldback
current limit.
Figure 31 shows the basic circuit connections for the
fixed voltage models. Figure 32 gives the connections
for the adjustable output version (TPS73201).
Optional input capacitor.
May improve source
impedance, noise, or PSRR.
VIN
Optional output capacitor.
May improve load transient,
noise, or PSRR.
IN
VOUT
OUT
TPS732xx
EN
GND
NR
Optional bypass
capacitor to reduce
output noise.
Figure 31. Typical Application Circuit for
Fixed-Voltage Versions
in addition to the internal 8kΩ resistor, presents the
same impedance to the error amp as the 27kΩ
bandgap reference output. This impedance helps
compensate for leakages into the error amp
terminals.
INPUT AND OUTPUT CAPACITOR
REQUIREMENTS
Although an input capacitor is not required for
stability, it is good analog design practice to connect
a 0.1µF to 1µF low ESR capacitor across the input
supply near the regulator. This counteracts reactive
input sources and improves transient response, noise
rejection, and ripple rejection. A higher-value
capacitor may be necessary if large, fast rise-time
load transients are anticipated or the device is
located several inches from the power source.
The TPS732xx does not require an output capacitor
for stability and has maximum phase margin with no
capacitor. It is designed to be stable for all available
types and values of capacitors. In applications where
VIN – VOUT < 0.5V and multiple low ESR capacitors
are in parallel, ringing may occur when the product of
COUT and total ESR drops below 50nΩF. Total ESR
includes all parasitic resistances, including capacitor
ESR and board, socket, and solder joint resistance.
In most applications, the sum of capacitor ESR and
trace resistance will meet this requirement.
OUTPUT NOISE
Optional output capacitor.
May improve load transient
noise, or PSRR.
Optional input capacitor.
May improve source
impedance, noise, or PSRR.
VIN
IN
EN
VOUT
OUT
TPS73201
GND
R1
CFB
FB
R2
VOUT =
(R1 + R2)
R2
x 1.204
Optional capacitor
reduces output noise
and improves
transient response.
Figure 32. Typical Application Circuit for
Adjustable-Voltage Version
R1 and R2 can be calculated for any output voltage
using the formula shown in Figure 32. Sample
resistor values for common output voltages are
shown in Figure 2.
A precision band-gap reference is used to generate
the internal reference voltage, VREF. This reference is
the dominant noise source within the TPS732xx and
it generates approximately 32VRMS (10Hz to 100kHz)
at the reference output (NR). The regulator control
loop gains up the reference noise with the same gain
as the reference voltage, so that the noise voltage of
the regulator is approximately given by:
VOUT
(R1 ) R2)
V N + 32mVRMS
+ 32mVRMS
R2
VREF
(1)
Since the value of VREF is 1.2V, this relationship
reduces to:
mV RMS
V N(mVRMS) + 27
V OUT(V)
V
(2)
ǒ
Ǔ
for the case of no CNR.
For best accuracy, make the parallel combination of
R1 and R2 approximately euqal to 19kΩ. This 19kΩ,
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Product Folder Link(s): TPS732xx
11
TPS732xx
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SBVS037L – AUGUST 2003 – REVISED AUGUST 2007
An internal 27kΩ resistor in series with the noise
reduction pin (NR) forms a low-pass filter for the
voltage reference when an external noise reduction
capacitor, CNR, is connected from NR to ground. For
CNR = 10nF, the total noise in the 10Hz to 100kHz
bandwidth is reduced by a factor of ~3.2, giving the
approximate relationship:
ǒmVV Ǔ
V N(mVRMS) + 8.5
RMS
V OUT(V)
(3)
for CNR = 10nF.
This noise reduction effect is shown as RMS Noise
Voltage vs CNR in the Typical Characteristics section.
The TPS73201 adjustable version does not have the
noise-reduction pin available. However, connecting a
feedback capacitor, CFB, from the output to the FB pin
will reduce output noise and improve load transient
performance.
The TPS732xx uses an internal charge pump to
develop an internal supply voltage sufficient to drive
the gate of the NMOS pass element above VOUT. The
charge pump generates ~250µV of switching noise at
~4MHz; however, charge-pump noise contribution is
negligible at the output of the regulator for most
values of IOUT and COUT.
BOARD LAYOUT RECOMMENDATION TO
IMPROVE PSRR AND NOISE PERFORMANCE
To improve ac performance such as PSRR, output
noise, and transient response, it is recommended that
the PCB be designed with separate ground planes for
VIN and VOUT, with each ground plane connected only
at the GND pin of the device. In addition, the ground
connection for the bypass capacitor should connect
directly to the GND pin of the device.
INTERNAL CURRENT LIMIT
The TPS732xx internal current limit helps protect the
regulator during fault conditions. Foldback current
limit helps to protect the regulator from damage
during output short-circuit conditions by reducing
current limit when VOUT drops below 0.5V. See
Figure 12 in the Typical Characteristics section for a
graph of IOUT vs VOUT.
12
SHUTDOWN
The Enable pin is active high and is compatible with
standard TTL-CMOS levels. VEN below 0.5V (max)
turns the regulator off and drops the ground pin
current to approximately 10nA. When shutdown
capability is not required, the Enable pin can be
connected to VIN. When a pull-up resistor is used,
and operation down to 1.8V is required, use pull-up
resistor values below 50kΩ. To ensure all charge is
removed from the gate of the pass element, the
Enable pin must be driven low before the input
voltage is removed. If the Enable pin is not driven
low, the pass element may be left on because of
stored charge on the gate.
DROPOUT VOLTAGE
The TPS732xx uses an NMOS pass transistor to
achieve extremely low dropout. When (VIN – VOUT) is
less than the dropout voltage (VDO), the NMOS pass
device is in its linear region of operation and the
input-to-output resistance is the RDS-ON of the NMOS
pass element.
For large step changes in load current, the TPS732xx
requires a larger voltage drop from VIN to VOUT to
avoid degraded transient response. The boundary of
this transient dropout region is approximately twice
the dc dropout. Values of VIN – VOUT above this line
insure normal transient response.
Operating in the transient dropout region can cause
an increase in recovery time. The time required to
recover from a load transient is a function of the
magnitude of the change in load current rate, the rate
of change in load current, and the available
headroom (VIN to VOUT voltage drop). Under
worst-case conditions [full-scale instantaneous load
change with (VIN – VOUT) close to dc dropout levels],
the TPS732xx can take a couple of hundred
microseconds to return to the specified regulation
accuracy.
TRANSIENT RESPONSE
The low open-loop output impedance provided by the
NMOS pass element in a voltage follower
configuration allows operation without an output
capacitor for many applications. As with any
regulator, the addition of a capacitor (nominal value
1µF) from the output pin to ground will reduce
undershoot magnitude but increase its duration. In
the adjustable version, the addition of a capacitor,
CFB, from the output to the adjust pin will also
improve the transient response.
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Product Folder Link(s): TPS732xx
TPS732xx
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SBVS037L – AUGUST 2003 – REVISED AUGUST 2007
The TPS732xx does not have active pull-down when
the output is over-voltage. This allows applications
that connect higher voltage sources, such as
alternate power supplies, to the output. This also
results in an output overshoot of several percent if the
load current quickly drops to zero when a capacitor is
connected to the output. The duration of overshoot
can be reduced by adding a load resistor. The
overshoot decays at a rate determined by output
capacitor COUT and the internal/external load
resistance. The rate of decay is given by:
(Fixed voltage version)
VOUT
dVńdt +
C OUT 80kW ø R LOAD
(4)
(Adjustable voltage version)
V OUT
dVńdt +
C OUT 80kW ø (R 1 ) R 2) ø R LOAD
(5)
Any tendency to activate the thermal protection circuit
indicates excessive power dissipation or an
inadequate heatsink. For reliable operation, junction
temperature should be limited to +125°C maximum.
To estimate the margin of safety in a complete design
(including
heatsink),
increase
the
ambient
temperature until the thermal protection is triggered;
use worst-case loads and signal conditions. For good
reliability, thermal protection should trigger at least
+35°C above the maximum expected ambient
condition of your application. This produces a
worst-case junction temperature of +125°C at the
highest
expected
ambient
temperature
and
worst-case load.
The internal protection circuitry of the TPS732xx has
been designed to protect against overload conditions.
It was not intended to replace proper heatsinking.
Continuously running the TPS732xx into thermal
shutdown will degrade device reliability.
POWER DISSIPATION
REVERSE CURRENT
The NMOS pass element of the TPS732xx provides
inherent protection against current flow from the
output of the regulator to the input when the gate of
the pass device is pulled low. To ensure that all
charge is removed from the gate of the pass element,
the enable pin must be driven low before the input
voltage is removed. If this is not done, the pass
element may be left on due to stored charge on the
gate.
After the enable pin is driven low, no bias voltage is
needed on any pin for reverse current blocking. Note
that reverse current is specified as the current flowing
out of the IN pin due to voltage applied on the OUT
pin. There will be additional current flowing into the
OUT pin due to the 80kΩ internal resistor divider to
ground (see Figure 1 and Figure 2).
For the TPS73201, reverse current may flow when
VFB is more than 1.0V above VIN.
The ability to remove heat from the die is different for
each
package
type,
presenting
different
considerations in the PCB layout. The PCB area
around the device that is free of other components
moves the heat from the device to the ambient air.
Performance data for JEDEC low- and high-K boards
are shown in the Power Dissipation Ratings table.
Using heavier copper will increase the effectiveness
in removing heat from the device. The addition of
plated through-holes to heat-dissipating layers will
also improve the heat-sink effectiveness.
Power dissipation depends on input voltage and load
conditions. Power dissipation (PD) is equal to the
product of the output current times the voltage drop
across the output pass element (VIN to VOUT):
P D + (VIN * VOUT) I OUT
(6)
Power dissipation can be minimized by using the
lowest possible input voltage necessary to assure the
required output voltage.
THERMAL PROTECTION
Thermal protection disables the output when the
junction temperature rises to approximately +160°C,
allowing the device to cool. When the junction
temperature cools to approximately +140°C, the
output circuitry is again enabled. Depending on power
dissipation, thermal resistance, and ambient
temperature, the thermal protection circuit may cycle
on and off. This limits the dissipation of the regulator,
protecting it from damage due to overheating.
Package Mounting
Solder pad footprint recommendations for the
TPS732xx are presented in Application Bulletin
Solder Pad Recommendations for Surface-Mount
Devices (SBFA015), available from the Texas
Instruments web site at www.ti.com.
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Copyright © 2003–2007, Texas Instruments Incorporated
Product Folder Link(s): TPS732xx
13
PACKAGE OPTION ADDENDUM
www.ti.com
7-Apr-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPS73201DBVR
ACTIVE
SOT-23
DBV
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS73201DBVRG4
ACTIVE
SOT-23
DBV
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS73201DBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS73201DBVTG4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS73201DCQ
ACTIVE
SOT-223
DCQ
6
78
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS73201DCQG4
ACTIVE
SOT-223
DCQ
6
78
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS73201DCQR
ACTIVE
SOT-223
DCQ
6
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS73201DCQRG4
ACTIVE
SOT-223
DCQ
6
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS73201DRBR
ACTIVE
SON
DRB
8
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS73201DRBRG4
ACTIVE
SON
DRB
8
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS73201DRBT
ACTIVE
SON
DRB
8
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS73201DRBTG4
ACTIVE
SON
DRB
8
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS73213DBVR
ACTIVE
SOT-23
DBV
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS73213DBVRG4
ACTIVE
SOT-23
DBV
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS73213DBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS73213DBVTG4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS73215DBVR
ACTIVE
SOT-23
DBV
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS73215DBVRG4
ACTIVE
SOT-23
DBV
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS73215DBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS73215DBVTG4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS73215DCQ
ACTIVE
SOT-223
DCQ
6
78
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS73215DCQG4
ACTIVE
SOT-223
DCQ
6
78
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS73215DCQR
ACTIVE
SOT-223
DCQ
6
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS73215DCQRG4
ACTIVE
SOT-223
DCQ
6
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS73216DBVR
ACTIVE
SOT-23
DBV
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Addendum-Page 1
Lead/Ball Finish
MSL Peak Temp (3)
PACKAGE OPTION ADDENDUM
www.ti.com
7-Apr-2008
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPS73216DBVRG4
ACTIVE
SOT-23
DBV
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS73216DBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS73216DBVTG4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS73218DBVR
ACTIVE
SOT-23
DBV
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS73218DBVRG4
ACTIVE
SOT-23
DBV
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS73218DBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS73218DBVTG4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS73218DCQ
ACTIVE
SOT-223
DCQ
6
78
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS73218DCQG4
ACTIVE
SOT-223
DCQ
6
78
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS73218DCQR
ACTIVE
SOT-223
DCQ
6
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS73218DCQRG4
ACTIVE
SOT-223
DCQ
6
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS73219DBVR
ACTIVE
SOT-23
DBV
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS73219DBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS73225DBVR
ACTIVE
SOT-23
DBV
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS73225DBVRG4
ACTIVE
SOT-23
DBV
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS73225DBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS73225DBVTG4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS73225DCQ
ACTIVE
SOT-223
DCQ
6
78
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS73225DCQG4
ACTIVE
SOT-223
DCQ
6
78
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS73225DCQR
ACTIVE
SOT-223
DCQ
6
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS73225DCQRG4
ACTIVE
SOT-223
DCQ
6
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS73230DBVR
ACTIVE
SOT-23
DBV
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS73230DBVRG4
ACTIVE
SOT-23
DBV
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS73230DBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS73230DBVTG4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS73230DCQ
ACTIVE
SOT-223
DCQ
6
78
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Addendum-Page 2
Lead/Ball Finish
MSL Peak Temp (3)
PACKAGE OPTION ADDENDUM
www.ti.com
7-Apr-2008
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPS73230DCQG4
ACTIVE
SOT-223
DCQ
6
TPS73230DCQR
ACTIVE
SOT-223
DCQ
TPS73230DCQRG4
ACTIVE
SOT-223
TPS73233DBVR
ACTIVE
TPS73233DBVRG4
78
Lead/Ball Finish
MSL Peak Temp (3)
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
6
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
DCQ
6
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
SOT-23
DBV
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ACTIVE
SOT-23
DBV
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS73233DBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS73233DBVTG4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS73233DCQ
ACTIVE
SOT-223
DCQ
6
78
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS73233DCQG4
ACTIVE
SOT-223
DCQ
6
78
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS73233DCQR
ACTIVE
SOT-223
DCQ
6
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS73233DCQRG4
ACTIVE
SOT-223
DCQ
6
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS73250DBVR
ACTIVE
SOT-23
DBV
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS73250DBVRG4
ACTIVE
SOT-23
DBV
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS73250DBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS73250DBVTG4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS73250DCQ
ACTIVE
SOT-223
DCQ
6
78
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS73250DCQG4
ACTIVE
SOT-223
DCQ
6
78
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS73250DCQR
ACTIVE
SOT-223
DCQ
6
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS73250DCQRG4
ACTIVE
SOT-223
DCQ
6
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
7-Apr-2008
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Apr-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPS73201DBVR
Package Package Pins
Type Drawing
SPQ
SOT-23
3000
179.0
DBV
5
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
8.4
3.2
3.2
1.4
4.0
W
Pin1
(mm) Quadrant
8.0
Q3
TPS73201DBVT
SOT-23
DBV
5
250
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TPS73201DCQR
SOT-223
DCQ
6
2500
330.0
12.4
6.8
7.3
1.88
8.0
12.0
Q3
TPS73201DRBR
SON
DRB
8
3000
330.0
12.4
3.3
3.3
1.0
8.0
12.0
Q2
TPS73201DRBR
SON
DRB
8
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS73201DRBT
SON
DRB
8
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS73201DRBT
SON
DRB
8
250
330.0
12.4
3.3
3.3
1.0
8.0
12.0
Q2
TPS73213DBVR
SOT-23
DBV
5
3000
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TPS73213DBVT
SOT-23
DBV
5
250
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TPS73215DBVR
SOT-23
DBV
5
3000
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TPS73215DBVT
SOT-23
DBV
5
250
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TPS73215DCQR
SOT-223
DCQ
6
2500
330.0
12.4
6.8
7.3
1.88
8.0
12.0
Q3
TPS73216DBVR
SOT-23
DBV
5
3000
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TPS73216DBVT
SOT-23
DBV
5
250
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TPS73218DBVR
SOT-23
DBV
5
3000
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TPS73218DBVT
SOT-23
DBV
5
250
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TPS73218DCQR
SOT-223
DCQ
6
2500
330.0
12.4
6.8
7.3
1.88
8.0
12.0
Q3
TPS73219DBVR
SOT-23
DBV
5
3000
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
Device
4-Apr-2008
Package Package Pins
Type Drawing
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS73219DBVT
SOT-23
DBV
5
250
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TPS73225DBVR
SOT-23
DBV
5
3000
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TPS73225DBVT
SOT-23
DBV
5
250
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TPS73225DCQR
SOT-223
DCQ
6
2500
330.0
12.4
6.8
7.3
1.88
8.0
12.0
Q3
TPS73230DBVR
SOT-23
DBV
5
3000
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TPS73230DBVT
SOT-23
DBV
5
250
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TPS73230DCQR
SOT-223
DCQ
6
2500
330.0
12.4
6.8
7.3
1.88
8.0
12.0
Q3
TPS73233DBVR
SOT-23
DBV
5
3000
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TPS73233DBVT
SOT-23
DBV
5
250
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TPS73233DCQR
SOT-223
DCQ
6
2500
330.0
12.4
6.8
7.3
1.88
8.0
12.0
Q3
TPS73250DBVR
SOT-23
DBV
5
3000
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TPS73250DBVT
SOT-23
DBV
5
250
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TPS73250DCQR
SOT-223
DCQ
6
2500
330.0
12.4
6.8
7.3
1.88
8.0
12.0
Q3
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS73201DBVR
SOT-23
DBV
5
3000
195.0
200.0
45.0
TPS73201DBVT
SOT-23
DBV
5
250
195.0
200.0
45.0
TPS73201DCQR
SOT-223
DCQ
6
2500
358.0
335.0
35.0
TPS73201DRBR
SON
DRB
8
3000
370.0
355.0
55.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Apr-2008
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS73201DRBR
SON
DRB
8
3000
346.0
346.0
29.0
TPS73201DRBT
SON
DRB
8
250
190.5
212.7
31.8
TPS73201DRBT
SON
DRB
8
250
370.0
355.0
55.0
TPS73213DBVR
SOT-23
DBV
5
3000
195.0
200.0
45.0
TPS73213DBVT
SOT-23
DBV
5
250
195.0
200.0
45.0
TPS73215DBVR
SOT-23
DBV
5
3000
195.0
200.0
45.0
TPS73215DBVT
SOT-23
DBV
5
250
195.0
200.0
45.0
TPS73215DCQR
SOT-223
DCQ
6
2500
358.0
335.0
35.0
TPS73216DBVR
SOT-23
DBV
5
3000
195.0
200.0
45.0
TPS73216DBVT
SOT-23
DBV
5
250
195.0
200.0
45.0
TPS73218DBVR
SOT-23
DBV
5
3000
195.0
200.0
45.0
TPS73218DBVT
SOT-23
DBV
5
250
195.0
200.0
45.0
TPS73218DCQR
SOT-223
DCQ
6
2500
358.0
335.0
35.0
TPS73219DBVR
SOT-23
DBV
5
3000
195.0
200.0
45.0
TPS73219DBVT
SOT-23
DBV
5
250
195.0
200.0
45.0
TPS73225DBVR
SOT-23
DBV
5
3000
195.0
200.0
45.0
TPS73225DBVT
SOT-23
DBV
5
250
195.0
200.0
45.0
TPS73225DCQR
SOT-223
DCQ
6
2500
358.0
335.0
35.0
TPS73230DBVR
SOT-23
DBV
5
3000
195.0
200.0
45.0
TPS73230DBVT
SOT-23
DBV
5
250
195.0
200.0
45.0
TPS73230DCQR
SOT-223
DCQ
6
2500
358.0
335.0
35.0
TPS73233DBVR
SOT-23
DBV
5
3000
195.0
200.0
45.0
TPS73233DBVT
SOT-23
DBV
5
250
195.0
200.0
45.0
TPS73233DCQR
SOT-223
DCQ
6
2500
358.0
335.0
35.0
TPS73250DBVR
SOT-23
DBV
5
3000
195.0
200.0
45.0
TPS73250DBVT
SOT-23
DBV
5
250
195.0
200.0
45.0
TPS73250DCQR
SOT-223
DCQ
6
2500
358.0
335.0
35.0
Pack Materials-Page 3
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