TPS731xx www.ti.com SBVS034H – SEPTEMBER 2003 – REVISED OCTOBER 2006 Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection FEATURES • • • • • • • • • • • DESCRIPTION Stable with No Output Capacitor or Any Value or Type of Capacitor Input Voltage Range of 1.7V to 5.5V Ultralow Dropout Voltage: 30mV Typ Excellent Load Transient Response—with or without Optional Output Capacitor New NMOS Topology Provides Low Reverse Leakage Current Low Noise: 30µVRMS Typ (10kHz to 100kHz) 0.5% Initial Accuracy 1% Overall Accuracy over Line, Load, and Temperature Less Than 1µA Max IQ in Shutdown Mode Thermal Shutdown and Specified Min/Max Current Limit Protection Available in Multiple Output Voltage Versions – Fixed Outputs of 1.20V to 5.0V – Adjustable Outputs from 1.20V to 5.5V – Custom Outputs Available The TPS731xx family of low-dropout (LDO) linear voltage regulators uses a new topology: an NMOS pass element in a voltage-follower configuration. This topology is stable using output capacitors with low ESR, and even allows operation without a capacitor. It also provides high reverse blockage (low reverse current) and ground pin current that is nearly constant over all values of output current. The TPS731xx uses an advanced BiCMOS process to yield high precision while delivering very low dropout voltages and low ground pin current. Current consumption, when not enabled, is under 1µA and ideal for portable applications. The extremely low output noise (30µVRMS with 0.1µF CNR) is ideal for powering VCOs. These devices are protected by thermal shutdown and foldback current limit. APPLICATIONS • • • • Portable/Battery-Powered Equipment Post-Regulation for Switching Supplies Noise-Sensitive Circuitry such as VCOs Point of Load Regulation for DSPs, FPGAs, ASICs, and Microprocessors Optional VIN Optional IN DBV PACKAGE SOT23 (TOP VIEW) VOUT OUT TPS731xx EN GND NR Optional IN 1 GND 2 EN 3 5 OUT 4 NR/FB Typical Application Circuit for Fixed-Voltage Versions Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2006, Texas Instruments Incorporated TPS731xx www.ti.com SBVS034H – SEPTEMBER 2003 – REVISED OCTOBER 2006 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) VOUT (2) PRODUCT XX is nominal output voltage (for example, 25 = 2.5V, 01 = Adjustable (3)). YYY is package designator. Z is package quantity. TPS731xxyyyz (1) (2) (3) For the most current specification and package information, refer to the Package Option Addendum located at the end of this datasheet or see the TI website at www.ti.com. Output voltages from 1.3V to 4V in 100mV increments are available through the use of innovative factory EEPROM programming. Minimum order quantities apply; contact factory for details and availability. For fixed 1.2V operation, tie FB to OUT. ABSOLUTE MAXIMUM RATINGS over operating junction temperature range unless otherwise noted (1) TPS731xx UNIT VIN range –0.3 to 6.0 V VEN range –0.3 to 6.0 V VOUT range –0.3 to 5.5 V VNR, VFB range –0.3 to 6.0 V Peak output current Internally limited Output short-circuit duration Indefinite Continuous total power dissipation See Dissipation Ratings Table Junction temperature range, TJ –55 to +150 Storage temperature range °C –65 to +150 °C ESD rating, HBM 2 kV ESD rating, CDM 500 V (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. POWER DISSIPATION RATINGS (1) PACKAGE RΘJC RΘJA DERATING FACTOR ABOVE TA = 25°C Low-K (2) DBV 64°C/W 255°C/W 3.9mW/°C 390mW 215mW 155mW DBV 64°C/W 180°C/W 5.6mW/°C 560mW 310mW 225mW High-K (1) (2) (3) 2 TA ≤ 25°C TA = 70°C TA = 85°C POWER RATING POWER RATING POWER RATING BOARD (3) See Power Dissipation in the Applications section for more information related to thermal design. The JEDEC Low-K (1s) board design used to derive this data was a 3 inch x 3 inch, two-layer board with 2-ounce copper traces on top of the board. The JEDEC High-K (2s2p) board design used to derive this data was a 3 inch x 3 inch, multilayer board with 1-ounce internal power and ground planes and 2-ounce copper traces on the top and bottom of the board. Submit Documentation Feedback TPS731xx www.ti.com SBVS034H – SEPTEMBER 2003 – REVISED OCTOBER 2006 ELECTRICAL CHARACTERISTICS Over operating temperature range (TJ = -40°C to +125°C), VIN = VOUT(nom) + 0.5V (1), IOUT = 10mA, VEN = 1.7V, and COUT = 0.1µF, unless otherwise noted. Typical values are at TJ = 25°C. PARAMETER TEST CONDITIONS VIN Input voltage range (1) VFB Internal reference (TPS73101) ∆VOUT%/∆VIN Accuracy (1) MAX TJ = 25°C UNIT 5.5 V 1.210 V VFB 5.5 – VDO V +0.5 1.198 Nominal TJ = 25°C –0.5 VIN, IOUT, and T VOUT + 0.5V ≤ VIN ≤ 5.5V; 10 mA ≤ IOUT ≤ 150mA –1.0 Line regulation (1) TYP 1.7 Output voltage range (TPS73101) VOUT MIN VOUT(nom) + 0.5V ≤ VIN ≤ 5.5V 1.20 ±0.5 +1.0 0.01 1mA ≤ IOUT ≤ 150mA 0.002 10mA ≤ IOUT ≤ 150mA 0.0005 % %/V ∆VOUT%/∆IOUT Load regulation VDO Dropout voltage (2) (VIN = VOUT (nom) – 0.1V) IOUT = 150mA ZO(DO) Output impedance in dropout 1.7 V ≤ VIN ≤ VOUT + VDO ICL Output current limit VOUT = 0.9 × VOUT(nom) ISC Short-circuit current VOUT = 0V 200 IREV Reverse leakage current (3) (-IIN) VEN ≤ 0.5V, 0V ≤ VIN ≤ VOUT 0.1 10 IOUT = 10mA (IQ) 400 550 IOUT = 150mA 550 750 VEN ≤ 0.5V, VOUT ≤ VIN ≤ 5.5 –40°C ≤ TJ ≤ +100°C 0.02 1 µA 0.1 0.3 µA 30 100 mV 500 mA Ω 0.25 150 360 IGND Ground pin current ISHDN Shutdown current (IGND) IFB FB pin current (TPS73101) PSRR Power-supply rejection ratio (ripple rejection) f = 100Hz, IOUT = 150 mA 58 f = 10kHz, IOUT = 150 mA 37 VN Output noise voltage BW = 10Hz - 100kHz COUT = 10µF, No CNR 27 × VOUT COUT = 10µF, CNR = 0.01µF 8.5 × VOUT tSTR Startup time VEN(HI) Enable high (enabled) VEN(LO) Enable low (shutdown) IEN(HI) Enable pin current (enabled) TSD Thermal shutdown temperature TJ Operating junction temperature (1) (2) (3) %/mA VOUT = 3V, RL = 30Ω COUT = 1µF, CNR = 0.01µF mA µVRMS µs VIN 0 VEN = 5.5V 0.02 Shutdown Temp increasing 160 Reset Temp decreasing 140 –40 µA dB 600 1.7 µA V 0.5 V 0.1 µA °C 125 °C Minimum VIN = VOUT + VDO or 1.7V, whichever is greater. VDO is not measured for the TPS73115 (VO(nom) = 1.5V) since minimum VIN = 1.7V. Fixed-voltage versions only; refer to the Applications section for more information. Submit Documentation Feedback 3 TPS731xx www.ti.com SBVS034H – SEPTEMBER 2003 – REVISED OCTOBER 2006 FUNCTIONAL BLOCK DIAGRAMS IN 4MHz Charge Pump EN Thermal Protection Ref Servo 27kΩ Bandgap Error Amp Current Limit OUT 8kΩ GND R1 R1 + R2 = 80kΩ R2 NR Figure 1. Fixed Voltage Version Table 1. Standard 1% Resistor Values for Common Output Voltages IN VO 4MHz Charge Pump EN Thermal Protection Ref Servo 27kΩ Bandgap Error Amp OUT Current Limit GND 8kΩ 80kΩ R2 4 Submit Documentation Feedback R2 1.2V Short Open 1.5V 23.2kΩ 95.3kΩ 1.8V 28.0kΩ 56.2kΩ 2.5V 39.2kΩ 36.5kΩ 2.8V 44.2kΩ 33.2kΩ 3.0V 46.4kΩ 30.9kΩ 3.3V 52.3kΩ 30.1kΩ 5.0V 78.7kΩ 24.9kΩ NOTE: VOUT = (R1 + R2)/R2 × 1.204; R1R2 ≅ 19kΩ for best accuracy. R1 FB Figure 2. Adjustable Voltage Version R1 TPS731xx www.ti.com SBVS034H – SEPTEMBER 2003 – REVISED OCTOBER 2006 PIN ASSIGNMENTS DBV PACKAGE SOT23 (TOP VIEW) IN 1 GND 2 EN 3 5 OUT 4 NR/FB TERMINAL FUNCTIONS TERMINAL NAME SOT23 (DBV) PIN NO. DESCRIPTION IN 1 Input supply GND 2 Ground EN 3 Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown mode. Refer to the Shutdown section under Applications Information for more details. EN can be connected to IN if not used. NR 4 Fixed voltage versions only—connecting an external capacitor to this pin bypasses noise generated by the internal bandgap, reducing output noise to very low levels. FB 4 Adjustable voltage version only—this is the input to the control loop error amplifier, and is used to set the output voltage of the device. OUT 5 Output of the regulator. There are no output capacitor requirements for stability. Submit Documentation Feedback 5 TPS731xx www.ti.com SBVS034H – SEPTEMBER 2003 – REVISED OCTOBER 2006 TYPICAL CHARACTERISTICS For all voltage versions at TJ= 25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1µF, unless otherwise noted. LOAD REGULATION LINE REGULATION 0.5 0.20 Referred to IOUT = 10mA 0.4 Change in VOUT (%) 0.3 Change in VOUT (%) Referred to VIN = VOUT + 0.5V at IOUT = 10mA 0.15 0.2 0.1 0 −0.1 −0.2 −0.3 0.10 0 −0.05 −40_ C −0.10 −0.15 −0.4 −0.20 −0.5 0 15 30 45 60 75 90 105 120 135 150 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VIN − VOUT (V) IOUT (mA) Figure 3. Figure 4. DROPOUT VOLTAGE vs OUTPUT CURRENT DROPOUT VOLTAGE vs TEMPERATURE 50 50 TPS73125DBV +125_ C 40 30 +25_ C 20 10 40 VDO (mV) VDO (mV) +25_ C +125_C 0.05 0 30 60 90 120 30 20 10 −40_C 0 TPS73125DBV IOUT = 150mA 0 −50 150 −25 IOUT (mA) 0 25 50 75 100 125 Temperature (_ C) Figure 5. Figure 6. OUTPUT VOLTAGE ACCURACY HISTOGRAM OUTPUT VOLTAGE DRIFT HISTOGRAM 30 18 I OUT = 10mA 16 25 I OUT = 10mA All Voltage Versions Percent of Units (%) Percent of Units (%) 14 20 15 10 12 10 8 6 4 5 2 6 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 10 20 30 40 50 60 70 80 90 100 0 −1.0 −0.9 −0.8 −0.7 −0.6 −0.5 −0.4 −0.3 −0.2 −0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 VOUT Error (%) Worst Case dVOUT/dT (ppm/_ C) Figure 7. Figure 8. Submit Documentation Feedback TPS731xx www.ti.com SBVS034H – SEPTEMBER 2003 – REVISED OCTOBER 2006 TYPICAL CHARACTERISTICS (continued) For all voltage versions at TJ= 25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1µF, unless otherwise noted. GROUND PIN CURRENT vs TEMPERATURE 700 600 600 500 500 IGND (µA) IGND (µA) GROUND PIN CURRENT vs OUTPUT CURRENT 700 400 300 200 400 300 VIN = 5.5V VIN = 4V VIN = 2V 200 VIN = 5.5V VIN = 4V VIN = 2V 100 100 0 0 30 60 90 120 0 −50 150 −25 0 25 50 75 100 I OUT (mA) Temperature (_ C) Figure 9. Figure 10. CURRENT LIMIT vs VOUT (FOLDBACK) GROUND PIN CURRENT in SHUTDOWN vs TEMPERATURE 400 125 1 VENABLE = 0.5V VIN = VO + 0.5V 350 ICL 300 250 IGND (µA) Current Limit (mA) IOUT = 150mA ISC 200 150 0.1 100 50 TPS73133 0 0 0.5 1.0 1.5 2.0 2.5 3.0 0.01 −50 3.5 0 25 50 Temperature (_C) Figure 11. Figure 12. CURRENT LIMIT vs VIN 75 100 125 CURRENT LIMIT vs TEMPERATURE 500 500 450 450 400 400 Current Limit (mA) Current Limit (mA) −25 VOUT (V) 350 300 250 200 350 300 250 200 150 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 150 −50 −25 0 25 50 VIN (V) Temperature (_C) Figure 13. Figure 14. Submit Documentation Feedback 75 100 125 7 TPS731xx www.ti.com SBVS034H – SEPTEMBER 2003 – REVISED OCTOBER 2006 TYPICAL CHARACTERISTICS (continued) For all voltage versions at TJ= 25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1µF, unless otherwise noted. PSRR (RIPPLE REJECTION) vs FREQUENCY PSRR (RIPPLE REJECTION) vs FREQUENCY 90 90 IO = 1mA CO = Any 70 IO = 1mA CO = 10mF IO = 1mA CO = 1 m F 80 PSRR (dB) 60 IO = 100mA C O = 1m F 50 IO = 100mA CO = Any 40 50 40 30 20 20 10 1k 100 VOUT = 1.25V 0 100k 10k IO = 100mA CO = 10mF Ceramic RSERIES = 0.3W NrCAP = 0.01mF 10 IO = Any CO = 0 mF VIN = VOUT = 1.25V 0 IO = 100mA CO = 10mF Ceramic No RSERIES NrCAP = 0.01mF 60 30 10 IO = 100mA CO = 10mF Tantalum 70 PSRR (dB) 80 10M 1M 10 1k 100 10k 100k 1M Frequency (Hz) Frequency (Hz) Figure 15. Figure 16. PSRR (RIPPLE REJECTION) vs VIN - VOUT NOISE SPECTRAL DENSITY CNR = 0µF 40 10M 1 35 C OUT = 1µF 25 eN (µV/√Hz) PSRR (dB) 30 20 15 10 Frequency = 100kHz COUT = 10µF VOUT = 2.5V 5 0 0 0.2 0.4 0.6 COUT = 0µF 0.1 COUT = 10µF I OUT = 150mA 0.01 0.8 1.0 1.2 1.4 1.6 1.8 2.0 10 Figure 17. Figure 18. 10k 100k RMS NOISE VOLTAGE vs COUT 1 60 50 VOUT = 5.0V 40 COUT = 1µF 0.1 VN (RMS) eN (µV/√Hz) 1k Frequency (Hz) NOISE SPECTRAL DENSITY CNR = 0.01µF 30 COUT = 10µF VOUT = 1.5V 10 I OUT = 150mA 0.01 0 10 100 1k 10k VOUT = 3.3V 20 COUT = 0µF 100k CNR = 0.01µF 10Hz < Frequency < 100kHz 0.1 1 COUT (µF) Frequency (Hz) Figure 19. 8 100 VIN − VOUT (V) Figure 20. Submit Documentation Feedback 10 TPS731xx www.ti.com SBVS034H – SEPTEMBER 2003 – REVISED OCTOBER 2006 TYPICAL CHARACTERISTICS (continued) For all voltage versions at TJ= 25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1µF, unless otherwise noted. TPS73133 LOAD TRANSIENT RESPONSE RMS NOISE VOLTAGE vs CNR 140 VIN = 3.8V VOUT = 5.0V COUT = 0µF 40mV/tick 120 VOUT COUT = 1µF 100 VN (RMS) 40mV/tick 80 60 40 20 0 VOUT VOUT = 3.3V COUT = 10µF 40mV/tick VOUT = 1.5V 150mA 10p 100p IOUT 25mA/tick COUT = 0µF 10Hz < Frequency < 100kHz 1p VOUT 10mA 1n 10µs/div 10n CNR (F) Figure 21. Figure 22. TPS73133 LINE TRANSIENT RESPONSE TPS73133 TURN-ON RESPONSE RL = 1kΩ COUT = 0µF IOUT = 150mA COUT = 0µF 50mV/div VOUT VOUT RL = 20Ω CO UT = 1µF 1V/div RL = 20Ω COUT = 10µF COUT = 100µF 50mV/div 5.5V 2V VOUT dVIN 1V/div = 0.5V/µs dt 4.5V 1V/div VEN 0V VIN 100µs/div 10µs/div Figure 23. Figure 24. TPS73133 TURN-OFF RESPONSE TPS73133 POWER UP / POWER DOWN 6 RL = 20Ω COUT = 10µF 5 R L = 20Ω C OUT = 1µF 1V/div 4 RL = 1kΩ COUT = 0µF VIN VOUT VOUT 2V Volts 3 2 1 1V/div 0 0V VEN 100µs/div −1 −2 50ms/div Figure 25. Figure 26. Submit Documentation Feedback 9 TPS731xx www.ti.com SBVS034H – SEPTEMBER 2003 – REVISED OCTOBER 2006 TYPICAL CHARACTERISTICS (continued) For all voltage versions at TJ= 25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1µF, unless otherwise noted. TPS73101 RMS NOISE VOLTAGE vs CFB IENABLE vs TEMPERATURE 60 10 55 VN (rms) IENABLE (nA) 50 1 0.1 45 40 35 30 25 0.01 −50 −25 0 25 50 75 100 VOUT = 2.5V COUT = 0µF R1 = 39.2kΩ 10Hz < Frequency < 100kHz 20 10p 125 100p 1n 10n Temperature (_C) CFB (F) Figure 27. Figure 28. TPS73101 IFBvs TEMPERATURE TPS73101 LOAD TRANSIENT, ADJUSTABLE VERSION 160 CFB = 10nF R1 = 39.2kΩ 140 COUT = 0µF 50mV/div 120 VOUT IFB (nA) 100 80 COUT = 10µF 50mV/div 60 VOUT 40 150mA 20 10mA 0 −50 −25 0 25 50 75 100 25µs/div 125 Temperature (_C) Figure 29. Figure 30. TPS73101 LINE TRANSIENT, ADJUSTABLE VERSION COUT = 0µF VOUT = 2.5V CFB = 10nF 100mV/div COUT = 10µF 100mV/div VOUT VOUT 4.5V 3.5V VIN 5µs/div Figure 31. 10 Submit Documentation Feedback IOUT TPS731xx www.ti.com SBVS034H – SEPTEMBER 2003 – REVISED OCTOBER 2006 APPLICATION INFORMATION The TPS731xx belongs to a family of new generation LDO regulators that use an NMOS pass transistor to achieve ultra-low-dropout performance, reverse current blockage, and freedom from output capacitor constraints. These features, combined with low noise and an enable input, make the TPS731xx ideal for portable applications. This regulator family offers a wide selection of fixed output voltage versions and an adjustable output version. All versions have thermal and over-current protection, including foldback current limit. Figure 32 shows the basic circuit connections for the fixed voltage models. Figure 33 gives the connections for the adjustable output version (TPS73101). Optional input capacitor. May improve source impedance, noise, or PSRR. VIN Optional output capacitor. May improve load transient, noise, or PSRR. IN VOUT OUT TPS731xx EN GND NR Optional bypass capacitor to reduce output noise. Figure 32. Typical Application Circuit for Fixed-Voltage Versions Optional output capacitor. May improve load transient noise, or PSRR. Optional input capacitor. May improve source impedance, noise, or PSRR. VIN IN EN VOUT OUT TPS73101 GND R1 CFB FB R2 VOUT = (R1 + R2) R2 x 1.204 Optional capacitor reduces output noise and improves transient response. Figure 33. Typical Application Circuit for Adjustable-Voltage Version R1 and R2 can be calculated for any output voltage using the formula shown in Figure 33. Sample resistor values for common output voltages are shown in Figure 2. For best accuracy, make the parallel combination of R1 and R2 approximately euqal to 19kΩ. This 19kΩ, in addition to the internal 8kΩ resistor, presents the same impedance to the error amp as the 27kΩ bandgap reference output. This impedance helps compensate for leakages into the error amp terminals. INPUT AND OUTPUT CAPACITOR REQUIREMENTS Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1µF to 1µF low ESR capacitor across the input supply near the regulator. This counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated or the device is located several inches from the power source. The TPS731xx does not require an output capacitor for stability and has maximum phase margin with no capacitor. It is designed to be stable for all available types and values of capacitors. In applications where VIN – VOUT < 0.5V and multiple low ESR capacitors are in parallel, ringing may occur when the product of COUT and total ESR drops below 50nΩF. Total ESR includes all parasitic resistances, including capacitor ESR and board, socket, and solder joint resistance. In most applications, the sum of capacitor ESR and trace resistance will meet this requirement. OUTPUT NOISE A precision band-gap reference is used to generate the internal reference voltage, VREF. This reference is the dominant noise source within the TPS731xx and it generates approximately 32µVRMS (10Hz to 100kHz) at the reference output (NR). The regulator control loop gains up the reference noise with the same gain as the reference voltage, so that the noise voltage of the regulator is approximately given by: VOUT (R1 ) R2) V N + 32mVRMS + 32mVRMS R2 VREF (1) Since the value of VREF is 1.2V, this relationship reduces to: mV RMS V N(mVRMS) + 27 V OUT(V) V (2) ǒ Ǔ for the case of no CNR. An internal 27kΩ resistor in series with the noise reduction pin (NR) forms a low-pass filter for the voltage reference when an external noise reduction capacitor, CNR, is connected from NR to ground. For CNR = 10nF, the total noise in the 10Hz to 100kHz bandwidth is reduced by a factor of ~3.2, giving the approximate relationship: Submit Documentation Feedback 11 TPS731xx www.ti.com SBVS034H – SEPTEMBER 2003 – REVISED OCTOBER 2006 ǒmVV Ǔ V N(mVRMS) + 8.5 RMS DROPOUT VOLTAGE V OUT(V) (3) for CNR = 10nF. This noise reduction effect is shown as RMS Noise Voltage vs CNR in the Typical Characteristics section. The TPS73101 adjustable version does not have the noise-reduction pin available. However, connecting a feedback capacitor, CFB, from the output to the FB pin will reduce output noise and improve load transient performance. The TPS731xx uses an internal charge pump to develop an internal supply voltage sufficient to drive the gate of the NMOS pass element above VOUT. The charge pump generates ~250µV of switching noise at ~4MHz; however, charge-pump noise contribution is negligible at the output of the regulator for most values of IOUT and COUT. BOARD LAYOUT RECOMMENDATION TO IMPROVE PSRR AND NOISE PERFORMANCE To improve ac performance such as PSRR, output noise, and transient response, it is recommended that the PCB be designed with separate ground planes for VIN and VOUT, with each ground plane connected only at the GND pin of the device. In addition, the ground connection for the bypass capacitor should connect directly to the GND pin of the device. INTERNAL CURRENT LIMIT The TPS731xx internal current limit helps protect the regulator during fault conditions. Foldback current helps to protect the regulator from damage during output short-circuit conditions by reducing current limit when VOUT drops below 0.5V. See Figure 11 in the Typical Characteristics section for a graph of IOUT vs VOUT. SHUTDOWN The Enable pin is active high and is compatible with standard TTL-CMOS levels. VEN below 0.5V (max) turns the regulator off and drops the ground pin current to approximately 10nA. When shutdown capability is not required, the Enable pin can be connected to VIN. When a pull-up resistor is used, and operation down to 1.8V is required, use pull-up resistor values below 50 kΩ. 12 The TPS731xx uses an NMOS pass transistor to achieve extremely low dropout. When (VIN – VOUT) is less than the dropout voltage (VDO), the NMOS pass device is in its linear region of operation and the input-to-output resistance is the RDS-ON of the NMOS pass element. For large step changes in load current, the TPS731xx requires a larger voltage drop across it to avoid degraded transient response. The boundary of this transient dropout region is approximately twice the dc dropout. Values of VIN – VOUT above this line insure normal transient response. Operating in the transient dropout region can cause an increase in recovery time. The time required to recover from a load transient is a function of the magnitude of the change in load current rate, the rate of change in load current, and the available headroom (VIN to VOUT voltage drop). Under worst-case conditions [full-scale instantaneous load change with (VIN – VOUT) close to dc dropout levels], the TPS731xx can take a couple of hundred microseconds to return to the specified regulation accuracy. TRANSIENT RESPONSE The low open-loop output impedance provided by the NMOS pass element in a voltage follower configuration allows operation without an output capacitor for many applications. As with any regulator, the addition of a capacitor (nominal value 1µF) from the output pin to ground will reduce undershoot magnitude but increase duration. In the adjustable version, the addition of a capacitor, CFB, from the output to the adjust pin will also improve the transient response. The TPS731xx does not have active pull-down when the output is over-voltage. This allows applications that connect higher voltage sources, such as alternate power supplies, to the output. This also results in an output overshoot of several percent if the load current quickly drops to zero when a capacitor is connected to the output. The duration of overshoot can be reduced by adding a load resistor. The overshoot decays at a rate determined by output capacitor COUT and the internal/external load resistance. The rate of decay is given by: (Fixed voltage version) VOUT dVńdt + C OUT 80kW ø R LOAD Submit Documentation Feedback (4) TPS731xx www.ti.com SBVS034H – SEPTEMBER 2003 – REVISED OCTOBER 2006 (Adjustable voltage version) V OUT dVńdt + C OUT 80kW ø (R 1 ) R 2) ø R LOAD (5) REVERSE CURRENT The NMOS pass element of the TPS731xx provides inherent protection against current flow from the output of the regulator to the input when the gate of the pass device is pulled low. To ensure that all charge is removed from the gate of the pass element, the enable pin must be driven low before the input voltage is removed. If this is not done, the pass element may be left on due to stored charge on the gate. After the enable pin is driven low, no bias voltage is needed on any pin for reverse current blocking. Note that reverse current is specified as the current flowing out of the IN pin due to voltage applied on the OUT pin. There will be additional current flowing into the OUT pin due to the 80kΩ internal resistor divider to ground (see Figure 1 and Figure 2). For the TPS73101, reverse current may flow when VFB is more than 1.0V above VIN. THERMAL PROTECTION Thermal protection disables the output when the junction temperature rises to approximately +160°C, allowing the device to cool. When the junction temperature cools to approximately +140°C, the output circuitry is again enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This limits the dissipation of the regulator, protecting it from damage due to overheating. Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. For reliable operation, junction temperature should be limited to +125°C maximum. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least +35°C above the maximum expected ambient condition of your application. This produces a worst-case junction temperature of +125°C at the highest expected ambient temperature and worst-case load. The internal protection circuitry of the TPS731xx has been designed to protect against overload conditions. It was not intended to replace proper heatsinking. Continuously running the TPS731xx into thermal shutdown will degrade device reliability. POWER DISSIPATION The ability to remove heat from the die is different for each package type, presenting different considerations in the PCB layout. The PCB area around the device that is free of other components moves the heat from the device to the ambient air. Performance data for JEDEC low- and high-K boards are shown in the Power Dissipation Ratings table. Using heavier copper will increase the effectiveness in removing heat from the device. The addition of plated through-holes to heat-dissipating layers will also improve the heat-sink effectiveness. Power dissipation depends on input conditions. Power dissipation (PD) product of the output current times across the output pass element (VIN P D + (VIN * VOUT) I OUT voltage and load is equal to the the voltage drop to VOUT): (6) Power dissipation can be minimized by using the lowest possible input voltage necessary to assure the required output voltage. Package Mounting Solder pad footprint recommendations for the TPS731xx are presented in Application Bulletin Solder Pad Recommendations for Surface-Mount Devices (SBFA015), available from the Texas Instruments web site at www.ti.com. Submit Documentation Feedback 13 PACKAGE OPTION ADDENDUM www.ti.com 6-Nov-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS73101DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73101DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73101DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73101DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS731125DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM TPS731125DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM TPS731125DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS731125DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73115DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73115DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73115DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73115DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73118DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73118DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73118DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73118DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73125DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73125DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73125DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73125DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73130DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73130DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73130DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73130DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73131DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 Lead/Ball Finish MSL Peak Temp (3) PACKAGE OPTION ADDENDUM www.ti.com 6-Nov-2006 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS73131DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73131DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73131DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73132DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73132DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73132DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73133DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73133DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73133DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73133DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73150DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73150DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73150DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73150DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 6-Nov-2006 reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. 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