SY58606U

SY58606U
4.25Gbps Precision, 1:2 CML Fanout Buffer
with Internal Termination and Fail Safe Input
General Description
The SY58606U is a 2.5/3.3V, high-speed, fully
differential 1:2 CML fanout buffer optimized to provide
two identical output copies with less than 15ps of skew
and less than 10pspp total jitter. The SY58606U can
process clock signals as fast as 3GHz or data patterns
up to 4.25Gbps.
The differential input includes Micrel’s unique, 3-pin
input termination architecture that interfaces to LVPECL,
LVDS or CML differential signals, (AC- or DC-coupled)
as small as 100mV (200mVpp) without any level-shifting
or termination resistor networks in the signal path. For
AC-coupled input interface applications, an integrated
voltage reference (VREF-AC) is provided to bias the VT pin.
The outputs are 400mV CML, with extremely fast
rise/fall times guaranteed to be less than 85ps.
The SY58606U operates from a 2.5V ±5% supply or
3.3V ±10% supply and is guaranteed over the full
industrial temperature range (–40°C to +85°C). For
applications that require LVPECL or LVDS outputs,
consider Micrel’s SY58607U and SY58608U, 1:2 fanout
buffers with 800mV and 325mV output swings
respectively. The SY58606U is part of Micrel’s high®
speed, Precision Edge product line.
Datasheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
Precision Edge
Features
• Precision 1:2, 400mV CML fanout buffer
• Guaranteed AC performance over temperature and
voltage:
– DC-to > 4.25Gbps throughput
– <320ps propagation delay (IN-to-Q)
– <15ps within-device skew
– <85ps rise/fall times
• Fail Safe Input
– Prevents outputs from oscillating when input is
invalid
• Ultra-low jitter design
– <1psRMS cycle-to-cycle jitter
– <10psPP total jitter
– <1psRMS random jitter
– <10psPP deterministic jitter
• High-speed CML outputs
• 2.5V ±5% or 3.3V ±10% power supply operation
• Industrial temperature range: –40°C to +85°C
• Available in 16-pin (3mm x 3mm) QFN package
Applications
Functional Block Diagram
•
•
•
•
Data Distribution: OC-48, OC-48+FEC, XAUI
SONET clock and data distribution
Fibre Channel clock and data distribution
Gigabit Ethernet clock and data distribution
Markets
•
•
•
•
•
•
•
Storage
ATE
Test and measurement
Enterprise networking equipment
High-end servers
Access
Metro area network equipment
Precision Edge is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
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Micrel, Inc.
SY58606U
Ordering Information(1)
Part Number
Package
Type
Operating
Range
Package Marking
Lead
Finish
SY58606UMG
QFN-16
Industrial
606U with Pb-Free
bar-line indicator
NiPdAu
Pb-Free
QFN-16
Industrial
606U with Pb-Free
bar-line indicator
NiPdAu
Pb-Free
(2)
SY58606UMGTR
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
2. Tape and Reel.
Pin Configuration
16-Pin QFN
Pin Description
Pin Number
Pin Name
1, 4
IN, /IN
2
VT
3
VREF-AC
5, 8,13, 16
VCC
Positive Power Supply: Bypass with 0.1uF//0.01uF low ESR capacitors as close to
the VCC pins as possible.
6, 7, 14, 15
GND,
Ground: Exposed pad must be connected to a ground plane that is the same
potential as the ground pins.
Exposed pad
9, 10
/Q1, Q1
11, 12
/Q0, Q0
August 2009
Pin Function
Differential Input: This input pair is the differential signal input to the device. Input
accepts DC-coupled differential signals as small as 100mV (200mVPP). Each pin of
this pair internally terminates with 50Ω to the VT pin. If the input swing falls below a
certain threshold (typical 30mV), the Fail Safe Input (FSI) feature will guarantee a
stable output by latching the output to its last valid state. See “Input Interface
Applications” subsection.
Input Termination Center-Tap: Each side of the differential input pair terminates to
VT pin. This pin provides a center-tap to a termination network for maximum
interface flexibility. See “Input Interface Applications” subsection.
Reference Voltage: This output biases to VCC–1.2V. It is used for AC-coupling inputs
IN and /IN. Connect VREF-AC directly to the VT pin. Bypass with 0.01µF low ESR
capacitor to VCC. Maximum sink/source current is ±1.5mA. See “Input Interface
Applications” subsection.
CML Differential Output Pairs: Differential buffered copies of the input signal. The
output swing is typically 400mV. Unused output pair may be left floating with no
impact on jitter. See “CML Output Termination” subsection.
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SY58606U
Absolute Maximum Ratings(1)
Operating Ratings(2)
Supply Voltage (VCC) ............................... –0.5V to +4.0V
Input Voltage (VIN) ....................................... –0.5V to VCC
CML Output Voltage (VOUT) .......... VCC-1.0V to VCC+0.5V
Current (VT)
Source or sink on VT pin ............................. ±100mA
Input Current
Source or sink Current on (IN, /IN) ................ ±50mA
Current (VREF)
(4)
Source or sink current on VREF-AC .............. ±1.5mA
Maximum operating Junction Temperature .......... 125°C
Lead Temperature (soldering, 20sec.) .................. 260°C
Storage Temperature (Ts) .................... –65°C to +150°C
Supply Voltage (VIN) ........................ +2.375V to +3.60V
Ambient Temperature (TA) ................... –40°C to +85°C
(3)
Package Thermal Resistance
QFN
Still-air (θJA) ............................................ 60°C/W
Junction-to-board (ψJB) ......................... 33°C/W
DC Electrical Characteristics(5)
TA = –40°C to +85°C, unless otherwise stated.
Symbol
Parameter
Condition
VCC
Power Supply Voltage Range
ICC
Power Supply Current
RDIFF_IN
Differential Input Resistance
(IN-to-/IN)
VIH
Input HIGH Voltage
(IN, /IN)
IN, /IN, Note 7
VIL
Input LOW Voltage
(IN, /IN)
IN, /IN
VIN
Input Voltage Swing
(IN, /IN)
see Figure 3a, Note 6
VDIFF_IN
Differential Input Voltage Swing
(|IN - /IN|)
see Figure 3b
VIN_FSI
Input Voltage Threshold that
Triggers FSI
VREF-AC
Output Reference Voltage
VT_IN
Voltage from Input to VT
Min
Typ
Max
Units
2.375
2.5
2.625
V
3.0
3.3
3.6
60
77
mA
100
110
Ω
VCC–1.6
VCC
V
0
VIH–0.1
V
0.1
1.7
V
No load, max. VCC
90
0.2
VCC–1.3
V
30
100
mV
VCC–1.2
VCC–1.1
V
1.28
V
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for
extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. ψJB and θJA
values are determined for a 4-layer board in still-air number, unless otherwise stated.
4. Due to the limited drive capability, use for input of the same package only.
5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
6. VIN (max) is specified when VT is floating.
7. VIH (min) not lower than 1.2V.
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SY58606U
CML Outputs DC Electrical Characteristics(7)
VCC = +2.5V ±5% or +3.3V ±10%, RL = 100Ω across the outputs; T A = –40°C to +85°C, unless otherwise stated.
Symbol
Parameter
Condition
VOH
Output HIGH Voltage
RL = 50Ω to VCC
Min
Typ
Max
Units
VCC-0.020
VCC-0.010
VCC
V
VOUT
Output Voltage Swing
See Figure 3a
325
400
mV
VDIFF_OUT
Differential Output Voltage Swing
See Figure 3b
650
800
mV
ROUT
Output Source Impedance
45
50
55
Ω
Note:
7. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
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SY58606U
AC Electrical Characteristics
VCC = +2.5V ±5% or +3.3V ±10%, RL = 100Ω across the outputs, Input tr/tf: <300ps; TA = –40°C to +85°C, unless
otherwise stated.
Symbol
Parameter
Condition
Min
fMAX
Maximum Frequency
NRZ Data
4.25
VOUT > 200mV
tPD
Propagation Delay
tSkew
tJitter
Units
Gbps
3.0
VIN: 100mV-200mV
150
270
400
ps
VIN: 200mV-800mV
120
220
320
ps
3
15
ps
100
ps
Note 8
Part-to-Part Skew
Note 9
Data
Max
2.5
Within Device Skew
Clock
GHz
Random Jitter
Note 10
1
psRMS
Deterministic Jitter
Note 11
10
psPP
Cycle-to-Cycle Jitter
Note 12
1
psRMS
Note 13
10
psPP
85
ps
53
%
Total Jitter
tR tF
IN-to-Q
Clock
Typ
Output Rise/Fall Times
(20% to 80%)
At full output swing.
Duty Cycle
Differential I/O
30
47
50
Notes:
8.
Within device skew is measured between two different outputs under identical input transitions.
9.
Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the
respective inputs.
10. Random jitter is measured with a K28.7 pattern, measured at ≤ fMAX.
11. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 223–1 PRBS pattern.
12. Cycle-to-cycle jitter definition: the variation period between adjacent cycles over a random sample of adjacent cycle pairs. tJITTER_CC = Tn –Tn+1,
where T is the time between rising edges of the output signal.
13. Total jitter definition: with an ideal clock input frequency of ≤ fMAX (device), no more than one output edge in 1012 output edges will deviate by
more than the specified peak-to-peak jitter value.
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SY58606U
Functional Description
Input Clock Failure Case
If the input clock fails to a floating, static, or extremely
low signal swing, then the FSI function will eliminate a
metastable condition and guarantee a stable output.
No ringing and no undetermined state will occur at the
output under these conditions.
Note that the FSI function will not prevent duty cycle
distortion in case of a slowly deteriorating (but still
toggling) input signal. Due to the FSI function, the
propagation delay will depend on rise and fall time of
the input signal and on its amplitude. Refer to “Typical
Characteristics” for detailed information.
Fail-Safe Input (FSI)
The input includes a special failsafe circuit to sense
the amplitude of the input signal and to latch the
outputs when there is no input signal present, or
when the amplitude of the input signal drops
sufficiently below 100mVPK (200mVPP), typically
30mVPK. Maximum frequency of SY58606U is limited
by the FSI function.
Timing Diagrams
Figure 1a. Propagation Delay
Figure 1b. Fail Safe Feature
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SY58606U
Typical Characteristics
VCC = 3.3V, GND = 0V, VIN = 100mV, RL = 100Ω across the outputs, T A = 25°C, unless otherwise stated.
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SY58606U
Functional Characteristics
VCC = 2.5V, GND = 0V, VIN = 325mV, Data Pattern: 2 -1, RL = 100Ω across the outputs, T A = 25°C, unless otherwise
stated.
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SY58606U
Functional Characteristics (continued)
VCC = 2.5V, GND = 0V, VIN = 325mV, RL = 100Ω across the outputs, T A = 25°C, unless otherwise stated.
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SY58606U
Input and Output Stage
Figure 2b. Simplified CML Output Buffer
Figure 2a. Simplified Differential Input Buffer
Single-Ended and Differential Swings
Figure 3a. Single-Ended Swing
Figure 3b. Differential Swing
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SY58606U
Input Interface Applications
Figure 4a. CML Interface
(DC-Coupled)
Figure 4b. CML Interface
(AC-Coupled)
Figure 4c. LVPECL Interface
(DC-Coupled)
Option: May connect VT to VCC
Figure 4d. LVPECL Interface
(AC-Coupled)
August 2009
Figure 4e. LVDS Interface
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SY58606U
CML Output Termination
Figure 5b. CML DC-Coupled Termination
Figure 5a. CML DC-Coupled Termination
Figure 5c. CML AC-Coupled Termination
Related Product and Support Documents
Part Number
Function
Data Sheet Link
SY58607U
3.2Gbps Precision, 1:2 LVPECL Fanout Buffer with
Internal Termination and Fail Safe Input
http://www.micrel.com/page.do?page=/productinfo/products/sy58607u.shtml
SY58608U
3.2Gbps Precision, 1:2 LVDS Fanout Buffer with
Internal Termination and Fail Safe Input
http://www.micrel.com/page.do?page=/productinfo/products/sy58608u.shtml
HBW Solutions
New Products and Termination Application Notes
http://www.micrel.com/page.do?page=/productinfo/as/HBWsolutions.shtml
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SY58606U
Package Information
16-Pin QFN
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for
its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a
product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for
surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant
injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk
and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.
© 2006 Micrel, Incorporated.
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