SY58610U 3.2Gbps Precision, LVPECL 2:1 MUX with Internal Termination and Fail Safe Input General Description The SY58610U is a 2.5/3.3V, high-speed, fully differential LVPECL 2:1 MUX capable of processing clock signals up to 2.5GHz and data patterns up to 3.2Gbps. The SY58610U is optimized to provide a buffered output of the selected input with less than 10pspp total jitter. The differential input includes Micrel’s unique, 3-pin input termination architecture that interfaces to LVPECL, LVDS or CML differential signals, (AC- or DC-coupled) as small as 100mV (200mVPP) without any level-shifting or termination resistor networks in the signal path. For AC-coupled input interface applications, an integrated reference voltage (VREF-AC) is provided to bias the VT pin. The outputs are 800mV LVPECL, with extremely fast rise/fall times guaranteed to be less than 130ps. The SY58610U operates from a 2.5V ±5% supply or 3.3V ±10% supply and is guaranteed over the full industrial temperature range (–40°C to +85°C). For applications that require CML or LVDS outputs, consider Micrel’s SY58609U and SY58611U, 2:1 MUX with 400mV and 325mV output swings, respectively. The SY58610U is part of Micrel’s high-speed, Precision Edge® product line. Datasheets and support documentation can be found on Micrel’s web site at: www.micrel.com. Functional Block Diagram Precision Edge® Features • Precision 800mV LVPECL 2:1 MUX • Guaranteed AC performance over temperature and voltage: – DC-to > 3.2Gbps throughput – <370ps propagation delay (IN-to-Q) – <130ps rise/fall times • Fail Safe Input – Prevents outputs from oscillating when input is invalid • Ultra-low jitter design – <1psRMS cycle-to-cycle jitter – <10psPP total jitter – <1psRMS random jitter – <10psPP deterministic jitter • High-speed LVPECL outputs • 2.5V ±5% or 3.3V ±10% power supply operation • Industrial temperature range: –40°C to +85°C • Available in 16-pin (3mm x 3mm) MLF® package Applications • • • • All SONET clock distribution Fibre Channel clock and data distribution Gigabit Ethernet clock and data distribution Backplane distribution. Markets • • • • • Storage ATE Test and measurement Enterprise networking equipment High-end servers Precision Edge is a registered trademark of Micrel, Inc. MLF and MicroLeadFrame are registered trademarks of Amkor Technology. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com November 2006 M9999-111406-A [email protected] or (408) 955-1690 Micrel, Inc. SY58610U Ordering Information(1) Part Number Package Type Operating Range Package Marking Lead Finish SY58610UMG MLF-16 Industrial 610U with Pb-Free bar-line indicator NiPdAu Pb-Free SY58610UMGTR(2) MLF-16 Industrial 610U with Pb-Free bar-line indicator NiPdAu Pb-Free Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only. 2. Tape and Reel. Pin Configuration Truth Table SEL Output 0 IN0 Selected 1 IN1 Selected 16-Pin MLF® (MLF-16) Pin Description Pin Number Pin Name Pin Function 1, 4 VT0, VT1 Input Termination Center-Tap: Each side of the differential input pair terminates to the VT pin. This pin provides a center-tap to a termination network for maximum interface flexibility. See “Input Interface Applications” subsection. 2, 3 VREF-AC0, VREF-AC1 Reference Voltage: These outputs bias to VCC–1.2V. They are used for AC-coupling inputs IN and /IN. Connect VREF-AC directly to the corresponding VT pin. Bypass with 0.01µF low ESR capacitor to VCC. Due to limited drive capability, the VREF-AC pin is only intended to drive its respective VT pin. Maximum sink/source current is ±0.5mA. See “Input Interface Applications” subsection. 5, 6 IN1, /IN1 15, 16 IN0, /IN0 Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs accept DC-Coupled differential signals as small as 100mV (200mVpp). Each pin of the pairs internally terminates with 50Ω to the corresponding VT pin. If the input swing falls below a certain threshold (typical 30mV), the Fail Safe Input (FSI) feature will guarantee a stable output by latching the output to its last valid state. See “Input Interface Applications” subsection. 7 SEL Single-Ended Input: This single-ended TTL/CMOS-compatible input selects the inputs to the multiplexer. Note that this input is internally connected to a 25kΩ pull-up resistor and will default to logic HIGH state if left open. The input-switching threshold is VCC/2. 8, 13 VCC Positive Power Supply: Bypass with 0.1uF//0.01uF low ESR capacitors as close to the VCC pins as possible. 9, 12 /Q, Q LVPECL Differential Output Pair: Differential buffered output copy of the selected input signal. The output swing is typically 800mV. Unused output pair may be left floating with no impact on jitter. See “LVPECL Output Termination” subsection. 10, 11 GND, Exposed Pad 14 NC November 2006 Ground. Exposed pad must be connected to a ground plane that is the same potential as the ground pins. No connect. 2 M9999-111406-A [email protected] or (408) 955-1690 Micrel, Inc. SY58610U Absolute Maximum Ratings(1) Operating Ratings(2) Supply Voltage (VCC) ............................... –0.5V to +4.0V Input Voltage (VIN) .......................................–0.5V to VCC LVPECL Output Current(IOUT) Continuous.......................................................50mA Surge .............................................................100mA Current (VT) Source or sink on VT pin .............................±100mA Input Current Source or sink Current on (IN, /IN) ................±50mA Current (VREF) Source or sink current on VREF-AC(4) ..............±0.5mA Maximum operating Junction Temperature ......... 125°C Lead Temperature (soldering, 20sec.) .................. 260°C Storage Temperature (Ts) ....................–65°C to +150°C Supply Voltage (VIN)........................ +2.375V to +3.60V Ambient Temperature (TA) ................... –40°C to +85°C Package Thermal Resistance(3) MLF® Still-air (θJA) ............................................ 60°C/W Junction-to-board (ψJB) ......................... 33°C/W DC Electrical Characteristics(5) TA = –40°C to +85°C, unless otherwise stated. Symbol Parameter VCC Power Supply Voltage Range Condition ICC Power Supply Current RDIFF_IN Differential Input Resistance (IN-to-/IN) VIH Input HIGH Voltage (IN, /IN) IN, /IN VIL Input LOW Voltage (IN, /IN) IN, /IN VIN Input Voltage Swing (IN, /IN) see Figure 3a, Note 6 VDIFF_IN Differential Input Voltage Swing (|IN - /IN|) see Figure 3b VIN_FSI Input Voltage Threshold that Triggers FSI VREF-AC AC Reference Voltage VT_IN Voltage from Input to VT Min Typ Max Units 2.375 2.5 2.625 V 3.0 3.3 3.6 40 50 mA 100 110 Ω 1.2 VCC V 0.2 VIH–0.1 V 0.1 1.0 V No load, max. VCC 90 0.2 V 30 VCC-1.3 100 mV VCC-1.0 V 1.28 V Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. ψJB and θJA values are determined for a 4-layer board in still-air number, unless otherwise stated. 4. Due to the limited drive capability, use for input of the same package only. 5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 6. VIN (max) is specified when VT is floating. November 2006 3 M9999-111406-A [email protected] or (408) 955-1690 Micrel, Inc. SY58610U LVPECL Outputs DC Electrical Characteristics(7) VCC = +2.5V ±5% or +3.3V ±10%, RL = 50Ω to VCC-2V; TA = –40°C to +85°C, unless otherwise stated. Symbol Parameter Condition Max Units VOH Output HIGH Voltage Q0, /Q0, Q1, /Q1 VCC-1.145 Min Typ VCC -0.895 V VOL Output LOW Voltage Q0, /Q0, Q1, /Q1 VCC-1.945 VCC-1.695 V VOUT Output Voltage Swing See Figure 3a 550 800 950 mV VDIFF_OUT Differential Output Voltage Swing See Figure 3b 1100 1600 Min Typ mV LVTTL/CMOS DC Electrical Characteristics(70) VCC = 2.5V ±5% or 3.3V ±10%; TA = –40°C to + 85°C, unless otherwise stated. Symbol Parameter Condition VIH Input HIGH Voltage VIL Input LOW Voltage IIH Input HIGH Current -125 IIL Input LOW Current -300 Max Units 0.8 V 30 µA 2.0 V µA Notes: 7. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. November 2006 4 M9999-111406-A [email protected] or (408) 955-1690 Micrel, Inc. SY58610U AC Electrical Characteristics(8) VCC = +2.5V ±5% or +3.3V ±10%, RL = 50Ω to VCC-2V; Input tR/tF < 300ps, TA = –40°C to +85°C, unless otherwise stated. Symbol Parameter Condition Min fMAX Maximum Frequency NRZ Data 3.2 VOUT > 400mV tPD Propagation Delay IN-to-Q Clock Typ Max Units Gbps 2.5 3 VIN: 100mV-200mV 180 340 470 ps VIN: >200mV 140 290 370 ps 450 ps 20 ps SEL-to-Q 150 tSkew Input-to-Input Skew Note 9, 10 Part-to-Part Skew Note 11 150 ps tJitter Data Random Jitter Note 12 1 psRMS Deterministic Jitter Note 13 10 psPP Cycle-to-Cycle Jitter Note 14 1 psRMS Total Jitter Note 15 10 psPP 130 ps 53 % Clock tR, tF 5 GHz Output Rise/Fall Times (20% to 80%) At full output swing. 40 Duty Cycle Differential I/O 47 100 Notes: 8. High-frequency AC-parameters are guaranteed by design and characterization. 9 Input-to-input skew is the time difference between the two inputs to one output, under identical input transitions. 10 Input-to-Input Skew is included in IN-to-Q propagation delay. 11. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature, same transition edge, and no skew at the edges at the respective inputs. 12. Random jitter is measured with a K28.7 pattern, measured at ≤ fMAX. 23 13. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 2 –1 PRBS pattern. 14. Cycle-to-cycle jitter definition: the variation period between adjacent cycles over a random sample of adjacent cycle pairs. tJITTER_CC = Tn –Tn+1, where T is the time between rising edges of the output signal. 15. Total jitter definition: with an ideal clock input frequency of ≤ fMAX (device), no more than one output edge in 10^12 output edges will deviate by more than the specified peak-to-peak jitter value. November 2006 5 M9999-111406-A [email protected] or (408) 955-1690 Micrel, Inc. SY58610U Functional Description Input Clock Failure Case If the input clock fails to a floating, static, or extremely low signal swing, such that the voltage swing across the input pair is less than 100mV, the FSI function will eliminate a metastable condition and latch the outputs to the last valid state. No ringing and no undetermined state will occur at the output under these conditions. The output recovers to normal operation once the input signal returns to a valid state with a swing greater than 100mV. Note that the FSI function will not prevent duty cycle distortion in case of a slowly deteriorating (but still toggling) input signal. Due to the FSI function, the propagation delay will depend on rise and fall time of the input signal and on its amplitude. Refer to “Typical Operating Characteristics” for detailed information. Fail-Safe Input (FSI) The input includes a special fail-safe circuit to sense the amplitude of the input signal and to latch the outputs when there is no input signal present, or when the amplitude of the input signal drops sufficiently below 100mVPK (200mVPP), typically 30mVPK. Maximum frequency of the SY58610U is limited by the FSI function. Timing Diagrams Figure 1a. Fail Safe Feature Figure 1b. Propagation Delay IN-to-Q November 2006 6 M9999-111406-A [email protected] or (408) 955-1690 Micrel, Inc. SY58610U Figure 1c. Propagation Delay SEL-to-Q November 2006 7 M9999-111406-A [email protected] or (408) 955-1690 Micrel, Inc. SY58610U Typical Characteristics VCC = 3.3V, GND = 0V, VIN = 100mV, RL = 50Ω to VCC-2V, TA = 25°C, unless otherwise stated. November 2006 8 M9999-111406-A [email protected] or (408) 955-1690 Micrel, Inc. SY58610U Functional Characteristics VCC = 3.3V, GND = 0V, VIN = 400mV, RL = 50Ω to VCC-2V, TA = 25°C, unless otherwise stated. November 2006 9 M9999-111406-A [email protected] or (408) 955-1690 Micrel, Inc. SY58610U Functional Characteristics (continued) VCC = 3.3V, GND = 0V, VIN = 400mV, RL = 50Ω to VCC-2V, TA = 25°C, unless otherwise stated. November 2006 10 M9999-111406-A [email protected] or (408) 955-1690 Micrel, Inc. Input and Output Stage SY58610U Single-Ended and Differential Swings Figure 3a. Single-Ended Voltage Swing Figure 2a. Simplified Differential Input Buffer Figure 3b. Differential Voltage Swing Figure 2b. Simplified LVPECL Output Buffer November 2006 11 M9999-111406-A [email protected] or (408) 955-1690 Micrel, Inc. SY58610U Input Interface Applications Figure 4a. CML Interface (DC-Coupled) Figure 4b. CML Interface (AC-Coupled) Figure 4c. LVPECL Interface (DC-Coupled) Option: May connect VT to VCC Figure 4d. LVPECL Interface (AC-Coupled) November 2006 Figure 4e. LVDS Interface 12 M9999-111406-A [email protected] or (408) 955-1690 Micrel, Inc. SY58610U LVPECL Output Termination LVPECL output has very low output impedance (open emitter), and small signal swing which results in low EMI. LVPECL is ideal for driving 50Ω and 100Ωcontrolled impedance transmission lines. There are several techniques in terminating the LVPECL output, as shown in Figures 5a and 5b. Figure 5b. Three-Resistor “Y-Termination” Figure 5a. Parallel Termination-Thevenin Equivalent Related Product and Support Documents Part Number Function Data Sheet Link SY58609U 4.25Gbps Precision, CML 2:1 MUX with Internal Termination and Fail Safe Input http://www.micrel.com/_PDF/HBW/sy58609u.pdf SY58611U 3.2Gbps Precision, LVDS 2:1 MUX with Internal Termination and Fail Safe Input http://www.micrel.com/_PDF/HBW/sy58611u.pdf HBW Solutions New Products and Termination Application Notes http://www.micrel.com/page.do?page=/productinfo/as/HBWsolutions.shtml November 2006 13 M9999-111406-A [email protected] or (408) 955-1690 Micrel, Inc. SY58610U Package Information 16-Pin (3mm x 3mm) MLF® (MLF-16) MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2006 Micrel, Incorporated. November 2006 14 M9999-111406-A [email protected] or (408) 955-1690