Low-Jitter Configurable Dual LVPECL-CMOS Oscillator

DSC2021
Low-Jitter Configurable Dual LVPECL-CMOS Oscillator
General Description
The DSC2021 series of high performance
dual output oscillators utilize a proven silicon
MEMS technology to provide excellent jitter
and stability while incorporating additional
device functionality. The two outputs are
controlled by separate supply voltages to
allow for independent voltage level control.
The frequencies of the outputs can be
identical or independently derived from a
common PLL frequency source.
The
DSC2021 has provision for up to eight userdefined
pre-programmed,
pin-selectable
output frequency combinations.
The
DSC2021 is also equipped with independent
pin-selectable output drive strengths for the
CMOS output to reduce EMI and noise.
DSC2021 is packaged in a 14-pin 3.2x2.5
mm
QFN
package
and
available
in
temperature grades from Ext. Commercial to
Industrial.
Block Diagram
Features
 Low RMS Phase Jitter: <1 ps (typ)
 High Stability: ±10, ±25, ±50 ppm
 Wide Temperature Range
o Industrial: -40° to 85° C
o Ext. commercial: -20° to 70° C
 High Supply Noise Rejection: -50 dBc
 Two Independent Outputs
o LVPECL and CMOS
 Pin-Selectable Configurations
o 3-bit Output Drive Strength (CMOS)
o 3-bit Output Frequency Combinations
 Wide Frequency Range
o LVPECL Output: 2.3 to 460 MHz
o CMOS Output: 2.3 to 170 MHz
 Miniature Footprint of 3.2x2.5mm
 Excellent Shock & Vibration Immunity
o Qualified to MIL-STD-883
 High Reliability
o 20x better MTF than quartz oscillators
 Supply Range of 2.25 to 3.6 V
 Lead Free & RoHS Compliant
Applications
 Storage Area Networks
o SATA, SAS, Fibre Channel
 Passive Optical Networks
o EPON, 10G-EPON, GPON, 10G-PON
 Ethernet
o 1G, 10GBASE-T/KR/LR/SR, and FCoE
 HD/SD/SDI Video & Surveillance
 PCI Express
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DSC2021
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MK-Q-B-P-D-12042604-2
DSC2021
Low-Jitter Configurable Dual LVPECL-CMOS Oscillator
Pin Description
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Pin Name
Enable
NC
OS0
GND
FS0
FS1
FS2
Output1+
Output1OS1
Output 2
VDD2
VDD
OS2
Pin
Type
I
NA
I
Power
I
I
I
O
O
I
O
Power
Power
I
Description
Enables outputs when high and disables (tri-state) them when low
Leave unconnected or grounded
Least significant bit for output drive strength selection for CMOS
Ground
Least significant bit for frequency selection
Middle bit for frequency selection
Most significant bit for frequency selection
Positive LVPECL Output 1
Negative LVPECL Output 1
Middle bit for output drive strength selection for CMOS
CMOS output
Power Supply 2 for CMOS Output
Power Supply
Most significant bit for output drive strength selection for CMOS
Operational Description
The DSC2021 is a dual output LVPECL-CMOS
oscillator consisting of a MEMS resonator and
a support PLL IC. The two outputs, CMOS and
LVPECL, are generated through independent
8-bit programmable dividers from the output
of the internal PLL. Two constraints are
imposed on the output frequencies: 1) f2=M x
f1/N, where M and N are even integers
between 4 and 254, 2) 1.2GHz < N x f2 <
1.7GHz.
The actual frequencies output by the DSC2021
are controlled by an internal pre-programmed
memory (OTP).
This memory stores all
coefficients required by the PLL for up to eight
different frequency combinations.
Three
control pins (FS0 – FS2) select the output
frequency combination.
Discera supports
customer defined versions of the DSC2021.
Standard frequency options are described in in
the following sections.
The DSC2021 provides control of the output
voltage levels of the CMOS output. VDD2 (pin
12) sets the high voltage level of Output 2 and
must be equal to or less than VDD at all times
to insure proper operation. VDD2 can be as
low as 1.65V.
When Enable (pin 1) is floated or connected to
VDD, the DSC2021 is in operational mode.
Driving Enable to ground will tri-state both
output drivers (hi-impedance mode).
The DSC2021 has programmable output drive
strength for CMOS output. Using three control
pins (OS0-OS2), the drive strength for CMOS
output (output 2) can be adjusted to match
circuit board impedances to reduce power
supply noise, overshoot/undershoot and EMI.
Table 1 displays typical rise / fall times for the
output with a 15pf load capacitance as a
function of these control pins at VDD=3.3V
and room temperature.
Table 1. Rise/Fall times for drive strengths
Output Drive Strength Bits
[OS2, OS1, OS0] - Default [111]
000
001
010
011
100
101
110
111
tr
(ns)
2.1
1.7
1.6
1.4
1.3
1.3
1.2
1.1
tf
(ns)
2.5
2.4
2.4
2
1.8
1.6
1.3
1.3
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DSC2021
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MK-Q-B-P-D-12042604-2
DSC2021
Low-Jitter Configurable Dual LVPECL-CMOS Oscillator
Output Clock Frequencies
Table 2 lists the standard frequency configurations and the associated ordering information to be
used in conjunction with the ordering code above. Customer defined combinations are available.
Table 2. Pre-programmed pin-selectable output frequency combinations
Ordering
Info
Freq
(MHz)
I0001
Freq Select Bits [FS2, FS1, FS0] – Default is [111]
fOUT1
000
150
001
150
010
125
011
100
100
150
101
156.25
110
125
111
100
fOUT2
75
50
50
50
25
25
25
25
fOUT1
I000X
Contact factory for additional configurations.
fOUT2
Frequency select bit are weakly tied high so if left unconnected the default setting will be [111] and
the device will output the associated frequency highlighted in Bold.
Absolute Maximum Ratings
Item
Min
Max
Unit
Supply Voltage
-0.3
+4.0
V
Input Voltage
-0.3
VDD+0.3
V
Junction Temp
-
+150
°C
Storage Temp
-55
+150
°C
Soldering Temp
-
+260
°C
ESD
HBM
MM
CDM
-
V
4000
400
1500
Ordering Code
Condition
Temp Range
E: -20 to 70
I: -40 to 85
DSC2021
40sec max.
F I 2
Package
F: 3.2x2.5mm
-
xxxxx
Stability
1: ±50ppm
2: ±25ppm
5: ±10ppm
Packing
T: Tape & Reel
: Tube
T
Freq (MHz)
See Freq. table
Note: 1000+ years of data retention on internal memory
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DSC2021
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MK-Q-B-P-D-12042604-2
DSC2021
Low-Jitter Configurable Dual LVPECL-CMOS Oscillator
Specifications (Unless specified otherwise: T=25° C, max CMOS drive strength)
Parameter
Condition
Supply Voltage1
Supply Current
VDD
IDD
Supply Current2
IDD
Frequency Stability
Δf
Aging
Startup Time3
Δf
tSU
Input Logic Levels
Input logic high
Input logic low
VIH
VIL
Output Disable Time4
Output Enable Time
Min.
Typ.
Max.
Unit
EN pin low – outputs are disabled
21
3.6
23
V
mA
EN pin high – outputs are enabled
LVPECL: RL=50Ω, FO1=125 MHz
CMOS: CL=15pF, FO2=75 MHz
62
2.25
Includes frequency variations due
to initial tolerance, temp. and
power supply voltage
1 year @25°C
T=25°C
mA
±10
±25
±50
±5
5
ppm
ms
0.25xVDD
V
tDA
5
ns
tEN
20
ns
2
Pull-Up Resistor
0.75xVDD
-
ppm
Pull-up exists on all digital IO
40
kΩ
LVPECL Output
Output Logic Levels
Output logic high
Output logic low
VOH
VOL
Pk to Pk Output Swing
Output Transition time
Rise Time
Fall Time
4
Frequency
tR
tF
RL=50Ω
VDD-1.08
-
VDD-1.55
V
Single-Ended
800
mV
20% to 80%
RL=50Ω, CL= 0pF (to GND)
250
ps
f0
Single Frequency
2.3
460
MHz
SYM
Differential
48
52
%
Period Jitter
JPER
FO1=125 MHz
2.5
Integrated Phase Noise
JCC
200kHz to 20MHz @156.25MHz
100kHz to 20MHz @156.25MHz
12kHz to 20MHz @156.25MHz
0.25
0.38
1.7
Output Duty Cycle
5
psRMS
2
psRMS
CMOS Output
Output Logic Levels
Output logic high
Output logic low
Output Transition time4
Rise Time
Fall Time
Frequency
Output Duty Cycle
tR
tF
f0
SYM
Period Jitter5
JPER
FO2=125 MHz
3
JCC
200kHz to 20MHz @ 125MHz
100kHz to 20MHz @ 125MHz
12kHz to 20MHz @ 125MHz
0.3
0.38
1.7
Integrated Phase Noise
Notes:
1.
2.
3.
4.
5.
VOH
VOL
I=±6mA
0.9xVDD
-
20% to 80%
CL=15pf
Commercial/Industrial temp range
1.1
1.3
2.3
45
0.1xVDD
V
2
2
170
55
ns
MHz
%
psRMS
2
psRMS
Pin 4 VDD should be filtered with 0.01uf capacitor.
Output is enabled if Enable pad is floated or not connected.
tsu is time to stable output frequency after VDD is applied and outputs are enabled.
Output Waveform and Test Circuit figures below define the parameters.
Period Jitter includes crosstalk from adjacent output.
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MK-Q-B-P-D-12042604-2
DSC2021
Low-Jitter Configurable Dual LVPECL-CMOS Oscillator
Nominal Performance Parameters (Unless specified otherwise: T=25° C, VDD=3.3 V)
2.5
2.5
25MHz-CMOS
212MHz-LVPECL
2.0
320MHz-LVPECL
1.5
410MHz-LVPECL
1.0
0.5
50MHz-CMOS
2.0
Phase Jitter (ps RMS)
Phase Jitter (ps RMS)
156MHz-LVPECL
106MHz-CMOS
1.5
125MHz-CMOS
1.0
0.5
0.0
0.0
0
200
400
600
800
0
1000
200
400
600
800
1000
Low-end of integration BW: x kHz to 20 MHz
Low-end of integration BW: x kHz to 20 MHz
CMOS Phase jitter (integrated phase noise)
LVPECL Phase jitter (integrated phase noise)
Output Waveform: LVPECL
tR
Output
tF
80%
830 mv
50%
Output
20%
tEN
1/f o
tDA
VIH
Enable
VIL
Output Waveform: CMOS
tR
tF
VOH
Output
VOL
tEN
1/fo
tDA
VIH
Enable
VIL
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DSC2021
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MK-Q-B-P-D-12042604-2
DSC2021
Low-Jitter Configurable Dual LVPECL-CMOS Oscillator
Solder Reflow Profile
20-40
Sec
Se
3C
/
217°C
200°C
60-150
Sec
.
ax
cM
Se
3C
/
25°C
a x.
Reflow
60-180
Sec
cM
150°C
Se
6C/
Temperature (°C)
cM
ax
.
260°C
Cool
Pre heat
Time
8 min max
MSL 1 @ 260°C refer to JSTD-020C
Ramp-Up Rate (200°C to Peak Temp) 3°C/Sec Max.
Preheat Time 150°C to 200°C
60-180 Sec
Time maintained above 217°C
60-150 Sec
255-260°C
Peak Temperature
Time within 5°C of actual Peak
20-40 Sec
6°C/Sec Max.
Ramp-Down Rate
Time 25°C to Peak Temperature
8 min Max.
Package Dimensions
3.2 x 2.5 mm 14 Lead Plastic Package
Disclaimer:
Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This information
is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry, specifications and
descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted
by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability whatsoever, and Micrel disclaims
any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties relating to fitness for a particular purpose,
merchantability, or infringement of any patent, copyright or other intellectual property right.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the
body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or
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MICREL, Inc.
Phone: +1 (408) 944-0800
●
●
2180 Fortune Drive,
Fax: +1 (408) 474-1000
San Jose, California
95131
● Email: [email protected]
●
●
USA
www.micrel.com
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MK-Q-B-P-D-12042604-2