CY2X014 Low Jitter LVPECL Crystal Oscillator Features Functional Description ■ Low Jitter Crystal Oscillator (XO) The CY2X014 is a high performance and high frequency Crystal Oscillator (XO). The device uses a Cypress proprietary low noise PLL to synthesize the frequency from an embedded crystal. ■ Less than 1 ps Typical RMS Phase Jitter ■ Differential LVPECL Output ■ Output Frequency from 50 MHz to 690 MHz ■ Factory Configured or Field Programmable ■ Integrated Phase-Locked Loop (PLL) ■ Output Enable or Power Down Function ■ Supply Voltage: 3.3V or 2.5V ■ Pb-Free Package: 5.0 x 3.2 mm LCC ■ Commercial and Industrial Temperature Ranges The CY2X014 is available as a factory configured device or as a field programmable device. Logic Block Diagram 4 CRYSTAL OSCILLATOR LOW-NOISE PLL CLK OUTPUT DIVIDER 5 CLK# PROGRAMMABLE CONFIGURATION 1 OE/PD# 6 3 VDD VSS Pinout Figure 1. Pin Diagram - 6 Pin Ceramic LCC OE/PD# 1 Cypress Semiconductor Corporation Document Number: 001-10179 Rev. *D • 6 VDD DNU 2 5 CLK# VSS 3 4 CLK 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 12, 2009 [+] Feedback CY2X014 Table 1. Pin Definitions - 6 Pin Ceramic LCC 1 Pin Name OE/PD# 4, 5 2 6 3 CLK, CLK# DNU VDD VSS I/O Type CMOS Input Description Output Enable Pin: Active HIGH. If OE = 1, CLK is enabled. Power Down Pin: Active LOW. If PD# = 0, the device is powered down and the clock is disabled. The functionality of this pin is programmable. LVPECL Output Differential Output Clock – Do Not Use: DNU pins are electrically connected, but perform no function Power Supply Voltage: 2.5V or 3.3V Power Ground Programming Description Pin 1: Output Enable or Power Down (OE/PD#) The CY2X014 is a programmable device. Before being used in an application, it must be programmed with the output frequencies and other variables described in a later section. Two different device types are available, each with its own programming flow. They are described in the following sections. Pin 1 is programmed as either Output Enable (OE) or Power Down (PD#). The OE function is used to enable or disable the CLK output quickly, but it does not reduce core power consumption. The PD# function puts the device into a low power state, but the wake up takes longer because the PLL must reacquire lock. Field Programmable CY2X014F Industrial vs. Commercial Device Performance Field programmable devices are shipped unprogrammed and must be programmed before being installed on a printed circuit board (PCB). Customers use CyberClocks™ Online Software to specify the device configuration and generate a JEDEC (extension .jed) programming file. Programming of samples and prototype quantities is available using a Cypress programmer. Third party vendors manufacture programmers for small to large volume applications. Cypress’s value added distribution partners also provide programming services. Field programmable devices are designated with an “F” in the part number. They are intended for quick prototyping and inventory reduction. Industrial and Commercial devices have different internal crystals. They have a potentially significant impact on performance levels for applications requiring the lowest possible phase noise. CyberClocks Online Software displays expected performance for both options. Phase Noise vs. Jitter Performance The software is located at www.cyberclocksonline.com. In most cases, the device configuration for optimal phase noise performance is different from the device configuration for optimal cycle to cycle or period jitter. CyberClocks Online Software includes algorithms to optimize performance for either parameter. Factory Configured CY2X014 Table 2. Device Programming Variables For ready-to-use devices, the CY2X014 is available with no field programming required. All requests are submitted to the local Cypress Field Application Engineer (FAE) or sales representative. After the request is processed, the user receives a new part number, samples, and data sheet with the programmed values. This part number is used for additional sample requests and production orders. The CY2X014 is one time programmable (OTP). Variable Output Frequency Pin 1 Function (OE or PD#) Optimization (Phase Noise or Jitter) Temperature Range (Commercial or Industrial) Programming Variables Output Frequency The CY2X014 can synthesize a frequency to a resolution of one part per million (ppm), but the actual accuracy of the output frequency is limited by the accuracy of the integrated reference crystal. The CY2X014 has an output frequency range of 50 MHz to 690 MHz, but the range is not continuous. The CY2X014 cannot generate frequencies in the ranges of 521 MHz to 529 MHz and 596 MHz to 617 MHz. Document Number: 001-10179 Rev. *D Page 2 of 9 [+] Feedback CY2X014 Absolute Maximum Conditions Parameter Description Condition VDD Supply Voltage VIN[1] Input Voltage, DC Relative to VSS TS Temperature, Storage Non operating TJ Temperature, Junction ESDHBM ESD Protection (Human Body Model) JEDEC STD 22-A114-B ΘJA[2] Thermal Resistance, Junction to Ambient 0 m/s airflow Min Max Unit –0.5 4.4 V –0.5 VDD+0.5 V –55 135 °C –40 135 °C 2000 V 64 °C/W Operating Conditions Parameter VDD Min Typ Max Unit 3.3V Supply Voltage Range Description 3.0 3.3 3.6 V 2.5V Supply Voltage Range 2.375 2.5 2.625 V TPU Power Up Time for VDD to Reach Minimum Specified Voltage (Power Ramp is Monotonic) 0.05 – 500 ms TA Ambient Temperature (Commercial) 0 – 70 °C –40 – 85 °C Condition Min Typ Max Unit VDD = 3.6V, CLK = 150 MHz, OE/PD# = VDD, output terminated – – 150 mA VDD = 2.625V, CLK = 150 MHz, OE/PD# = VDD, output terminated – – 145 mA Ambient Temperature (Industrial) DC Electrical Characteristics Parameter IDD[3] Description Operating Supply Current ISB Standby Supply Current PD# = VSS – – 200 μA VOH LVPECL High Output Voltage VDD = 3.3V or 2.5V, RTERM = 50Ω to VDD – 2.0V VDD – 1.15 – VDD – 0.75 V VOL LVPECL Low Output Voltage VDD = 3.3V or 2.5V, RTERM = 50Ω to VDD – 2.0V VDD – 2.0 – VDD – 1.625 V VOD1 LVPECL Output Voltage Swing (VOH - VOL) VDD = 3.3V or 2.5V, RTERM = 50Ω to VDD – 2.0V 600 – 1000 mV VOD2 LVPECL Output Voltage Swing (VOH - VOL) VDD = 2.5V, RTERM = 50Ω to VDD – 1.5V 500 – 1000 mV VOCM LVPECL Output Common Mode Voltage (VOH + VOL)/2 VDD = 2.5V, RTERM = 50Ω to VDD – 1.5V 1.2 – – V IOZ LVPECL Output Leakage Current PD#/OE = VSS –35 – 35 μA VIH Input High Voltage 0.7*VDD – – V VIL Input Low Voltage – – 0.3*VDD V IIH Input High Current Input = VDD – – 115 μA IIL Input Low Current Input = VSS – – 50 μA CIN Input Capacitance – 15 – pF Notes 1. The voltage on any input or I/O pin cannot exceed the power pin during power up. 2. Simulated. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of copper (2/1/1/2 oz.). The internal layers are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model. 3. IDD includes ~24 mA of current that is dissipated externally in the output termination resistors. Document Number: 001-10179 Rev. *D Page 3 of 9 [+] Feedback CY2X014 AC Electrical Characteristics[4] Parameter Description Condition Min Typ Max Unit 50 – 690 MHz VDD = min to max, TA = 0°C to 70°C – – ±35 ppm VDD = min to max, TA = –40° to 85°C – – ±55 ppm – – ±15 ppm F <= 450 MHz, measured at zero crossing 45 50 55 % FOUT Output Frequency[6] FSC Frequency Stability, Commercial Devices[5] FSI Frequency Stability, Industrial Devices[5] AG Aging, 10 Years TDC Output Duty Cycle F > 450 MHz, measured at zero crossing 40 50 60 % TR, TF Output Rise and Fall Time 20% and 80% of full output swing 200 400 600 ps TOHZ Output Disable Time Time from falling edge on OE to stopped outputs (Asynchronous) – – 100 ns TOE Output Enable Time Time from rising edge on OE to outputs at a valid frequency (Asynchronous) – – 100 ns TLOCK Startup Time Time for CLK to reach valid frequency measured from the time VDD = VDD(min.) or from PD# rising edge – – 10 ms TJitter(φ) RMS Phase Jitter (Random) FOUT = 106.25 MHz (12 kHz to 20 MHz) – 1 – ps Typical Output Characteristics Figure 2. 2.5V Supply and Termination to VDD–1.5V, Minimum VDD and Maximum TA 0.9 1.40 0.8 0.7 VOCM (V) Swing (V) 1.35 0.6 1.30 1.25 0.5 1.20 0.4 0 100 200 300 400 Frequency (MHz) 500 600 700 0 100 200 300 400 500 600 700 Frequency (MHz) Notes 4. Not 100% tested, guaranteed by design and characterization. 5. Frequency stability is the maximum variation in frequency from F0. It includes initial accuracy, and variation from temperature and supply voltage. 6. This parameter is specified in CyberClocks Online software Document Number: 001-10179 Rev. *D Page 4 of 9 [+] Feedback CY2X014 Figure 3. 2.5V Supply and Termination to VDD–2V, Minimum VDD and Maximum TA 0.9 0.90 0.8 0.7 VOCM (V) Swing (V) 0.85 0.6 0.80 0.75 0.5 0.4 0.70 0 100 200 300 400 500 600 700 0 100 200 Frequency (MHz) 300 400 500 600 700 Frequency (MHz) Figure 4. 3.3V Supply and Termination to VDD–2V, Minimum VDD and Maximum TA 1.60 0.9 0.8 0.7 VOCM (V) Swing (V) 1.55 0.6 1.50 1.45 0.5 0.4 1.40 0 100 200 300 400 Frequency (MHz) Document Number: 001-10179 Rev. *D 500 600 700 0 100 200 300 400 500 600 700 Frequency (MHz) Page 5 of 9 [+] Feedback CY2X014 Switching Waveforms Figure 5. Output DC Parameters VA CLK VOD VOCM = (V A + VB)/2 CLK# VB Figure 6. Duty Cycle Timing CLK TDC = CLK# TPW TPERIOD TPW TPERIOD Figure 7. Output Rise and Fall Time CLK# CLK 80% 80% 20% 20% TR TF Figure 8. Output Enable and Disable Timing OE VIL TOHZ VIH TOE CLK High Impedance CLK# Termination Circuits Figure 9. LVPECL Termination VDD - 2V (VDD = 3.3V) 50Ω 50Ω 50Ω CLK 50Ω 50Ω CLK# Document Number: 001-10179 Rev. *D BUF BUF CLK VDD - 2V or VDD - 1.5V (VDD = 2.5V) 50Ω 50Ω 50Ω CLK# Page 6 of 9 [+] Feedback CY2X014 Ordering Information Part Number[7] Configuration Package Description Product Flow Pb-Free CY2X014FLXCT Field Programmable 6-Pin Ceramic LCC SMD - Tape and Reel Commercial, 0° to 70°C CY2X014FLXIT Field Programmable 6-Pin Ceramic LCC SMD - Tape and Reel Industrial, –40° to 85°C CY2X014LXCxxxT Factory Configured 6-Pin Ceramic LCC SMD - Tape and Reel Commercial, 0° to 70°C CY2X014LXIxxxT Factory Configured 6-Pin Ceramic LCC SMD - Tape and Reel Industrial, –40° to 85°C Package Diagram Figure 10. 6-Pin 3.2x5.0 mm Ceramic LCC LZ06A 0.50 1.30 Max 2.54 TYP. SIDE VIEW 0.64 TYP. TYP. 0.20 R REF. 5 4 0.32 R INDEX 6 10 7 9 8 TYP. 1.2 TYP. 3 2 0.45 REF. TOP VIEW 1 0.10 REF. 3.2 TYP. 1.27 5.0 0.10 R REF. BOTTOM VIEW Dimensions in mm General Tolerance: ± 0.15MM Kyocera dwg ref KD-VA6432-A 001-10044-** Package Weight ~ 0.12 grams . Note 7. “xxx” is a factory assigned code that identifies the programming option. Document Number: 001-10179 Rev. *D Page 7 of 9 [+] Feedback CY2X014 Document History Page Document Title: CY2X014 Low Jitter LVPECL Crystal Oscillator Document Number: 001-10179 Rev. ECN No. Orig. of Change Submission Date ** 504478 RGL See ECN New data sheet *A 1428603 JWK/SFV See ECM Removed pull up on pin 1 and related specifications, Added items to Programming Variables section, Added CIN specification, Modified tJ2, IIH, IIL, IDD and ISB specifications, Changed to a single Frequency Stability specification, Removed Peak-to-peak Period Jitter specification, Changed pin 2 from NC to DNU, Changed max storage temperature, Title change, 2.5V supply tightened from ±10% to ±5%, 2.5V termination option changed from VDD-1.4V to VDD-1.5V, Added typical output characteristic curves *B 2669117 KVM/AESA 03/05/09 Revised frequency stability and aging specs and conditions, Max frequency changed from 700 MHz to 690 MHz, Duty cycle changed from 45/55 to 40/60 for freq > 450 MHz, Removed reference to CY3672 programmer, Junction and storage temperatures changed from 125 to 135°C, IIH changed from 20μA to 115μA, IIL changed from 20μA to 50μA, Rise and fall times changed from 350 ps to 500 ps, Removed MSL spec, Changed Data Sheet Status to Final. *C 2701663 KVM/PYRS 05/06/09 General clean up Added explanation of gaps in the frequency range Added URL for software Removed frequency stability paragraph under Programming Variables Added programming variables table Added separate IDD spec for 2.5V supply Changed the amount of load current in IDD footnote Changed phase jitter parameter name Removed supply voltage as a programming variable Changed conditions for ESD spec Changed rise & fall times from 500 ps to 400 ps typ, added min and max *D 2718433 WWZ/HMT 06/12/09 No change. Submit to ECN for product launch. Document Number: 001-10179 Rev. *D Description of Change Page 8 of 9 [+] Feedback CY2X014 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Solutions PSoC psoc.cypress.com Clocks & Buffers clocks.cypress.com General Low Power/Low Voltage psoc.cypress.com/solutions psoc.cypress.com/low-power Wireless wireless.cypress.com Precision Analog Memories memory.cypress.com LCD Drive psoc.cypress.com/lcd-drive image.cypress.com CAN 2.0b psoc.cypress.com/can USB psoc.cypress.com/usb Image Sensors psoc.cypress.com/precision-analog © Cypress Semiconductor Corporation, 2007-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-10179 Rev. *D Revised June 12, 2009 Page 9 of 9 CyberClocks is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback