THL3512_Rev.1.03_E THL3512 24-channel LED Driver with LVDS Interface Descriptions Features The THL3512 is an LED driver with 24 channel opendrain outputs. T h e e m b e d d e d o sc i l l a to r a n d P W M c o n t r o l l e r individually generates 256-step brightness set by the dedicated registers for each channel. The serial interface of 2-pair LVDS lines (clock and data) features high-level noise tolerance, high-speed, and long-distance transmission. The LVDS allowing cascaded and multidrop connection offers the maximum flexibility for designers to place and connect LED drivers. The simple and one-way communication protocol is easily-controlled and requires less CPU resources. < Driver part > - Open-Drain Output: 24 channels - Output Sink Current: up to 100mA/ch - Output voltage: up to 40V - Individual Brightness Control: 256 steps - Output disable/enable < Serial interface part > - 2-pair Serial LVDS Input or 3-wire Serial CMOS Input up to 10Mbps - Bridge Function Converting 3-wire Serial CMOS Input to 2-pair Serial LVDS Output - Repeater function of 2-pair Serial LVDS Input / Output with Waveform and Timing Correction - Device Address Selection up to 62 addresses - General call to all devices Applications Amusement LED Backlight LED Display Digital Signage Illumination Protection Circuits UVLO, Overcurrent Protection, Thermal Shutdown Supply Voltage: 3.0~5.5V Package: QFN 48-pin Exposed Pad EU RoHSCompliant Comploant EU RoHS Block Diagram OUT0 ~ OUT23 Open-Drain Outputs Oscillator PWM Controller Registers Address A0~A5 SCL_INp Input Logic LVDS Input LVDS Output SCL_OUTp SCL SCL_INn SCL_OUTn SDA_INp SDA_INn Data SDA SDA_OUTp Re-timing SDA_OUTn SCK SCL CS SDA SI MODE Copyright©2015 THine Electronics, Inc. 3-wire to 2-wire conversion 1 THine Electronics, Inc. Security E THL3512_Rev.1.03_E ABSOLUTE MAXIMUM RATINGS Parameter Condition Min Typ Max Unit VDD Supply Voltage -0.4 6.0 V Digital Input Voltage *Note１ -0.5 6.0 V 40 V 150 °C 150 °C Max Unit 5.5 V 35 V 100 mA/ch 85 °C LED Driver Output Voltage Storage Temperature -55 Junction Temperature, Tj *Note1: As for the A0 pin, the maximum value is VDD+0.5V. While power supply is not applied, voltage to the A0 pin must be lower than 0.5V. RECOMMENDED OPERATING CONDITIONS Parameter Condition VDD Supply Voltage Min Typ 3.0 LED Driver Output Voltage LED Driver Output Current (Continuos) Operating Ambient Temperature, Ta -40 ELECTRICAL CHARACTERISTICS (VDD=5V,Ta=25 ℃ ,unless otherwise noted.) Condtion Parameter VDD Supply Current *Note1 Min Typ Max Unit VDD=3.3V, without LVDS output termination resistors 7 mA VDD=3.3V, with LVDS output termination resistors 100Ω 14 mA VDD=5.0V, without LVDS output termination resistors 10 mA VDD=5.0V, with LVDS output termination resistors 100Ω 18 mA VDD=5.5V, with LVDS output termination resistors 100Ω 25 mA Osillator Frequency(fosc) 900 kHz UVLO Threshold Voltage (VDD Rising) 2.5 V UVLO Hysteresis 0.1 V VDD=3.0V LED Driver Output ON Resistance 4 VDD=3.3V 2 VDD=5.0V 1.7 LED Driver Output Leakage Current Ω 0.7VDD 0.3VDD Digital Input, Hysteresis 0.05VDD ±10 VIC=1.25V ±100 ±30 LVDS Output, Differential Voltage (VOD) 240 mV 350 mV VDD=5.0V 420 mV 1.1 2 μA VDD=3.3V VDD=5.5V LVDS Output, Common Mode Voltage (VOC) μA mV LVDS Input, Leakage Current VDD=3.0V V V Digital Input, Leakage Current LVDS Input, Differential Voltage (VID) μA V Digital Input, Low Level Voltage (VIL) Copyright©2015 THine Electronics, Inc. Ω ±1 Digital Input, High Level Voltage (VIH) Ω 1.25 480 1.4 mV V THine Electronics, Inc. Security E THL3512_Rev.1.03_E 3-wire Serial CMOS Level Input (MODE=High) Symbol Parameter Condition Min Typ Max Unit 10 MHz fSCK SCK Frequency tCH SCK High Time 40 ns tCL SCK Low Time 40 ns tDVCH SI Setup Time 10 ns tCHDX SI Hold Time 10 ns tCHSL CSn Not Active Hold Time 40 ns tSLCH CSn Active Setup Time 40 ns tCHSH CSn Active Hold Time 40 ns tSHCH CSn Not Active Setup Time 40 ns tSHSL CSn Not Active Time 200 ns 2-pair Serial LVDS Output Symbol tr, tf Parameter Condition SCL, SDA Transition Time Min Typ *2 Max Unit 10 ns tSTAH Header Condition Hold Time 6 10 20 ns tDSU SDA Setup Time 6 10 20 ns tDHO SCL Falling Edge Hold Time 5 tPWE End Pulse Width 25 tPD ns 40 SCL Propagation Delay 70 ns 30 ns Max Unit 10 MHz 2-pair Serial LVDS Input (MODE=Low) Symbol Parameter Condition Min Typ fSCL SCL Frequency tDAH SCL High Time 25 ns tDAL SCL Low Time 25 ns Header Condition Hold Time 4 ns tDSU SDA Setup Time 4 ns tDHO SCL Falling Edge Hold Time 3 ns tSTAH *1. In cascading connection, termination resistors are necessary for LVDS outputs. In this case, 2.4mA to 4.8mA current flows at each resistor depending on the power supply voltage. Therefore, the current consumption is larger than the case without the termination resistors. < With termination resistors > < Without termination resistors > SCL_OUTp SCL_OUTn 100Ω Open SDA_OUTp SDA_OUTn 100Ω Open *2. SCL, SDATransition Time Measurement Condition OUTp Load Capacitance:50pF Termination Resistor:100Ω OUTn Copyright©2015 THine Electronics, Inc. 3 THine Electronics, Inc. Security E THL3512_Rev.1.03_E LVDS Spec VID INn VIC=(INp+INn)/2 INp VOD OUTn VOC=(OUTp+OUTn)/2 OUTp INp: SCL_INp, SDA_INp 80% OUTp-OUTn 0V 20% tr INn: SCL_INn, SDA_INn OUTp: SCL_OUTp, SDA_OUTp OUTn: SCL_OUTn, SDA_OUTn tf Timing Diagram tSHSL 3-wire Serial Input/2-pair Serial LVDS Output Timing CSn tCHSL tSLCH tCL tCH tCHSH tSHCH SCK tDVCH tCHDX Bit 7 SI Bit 0 tPD tPWE SCL_OUT tSTAH tDSU tDHO End Pulse Bit 7 SDA_OUT Bit 0 Header Condition 2-pair Serial LVDS Input/Output Timing tDAL tDAH SCL_IN tSTAH tDSU tDHO Bit 7 SDA_IN Header Condition Bit 0 tPD SCL_OUT SDA_OUT Bit 0 Bit 7 * Abbreviation This documents refers to the differential signals in unipolar shorthand; for example, SCL_IN, SDA_IN, SCL_OUT, and SDA_OUT mean (SCL_INp - SCL_INn), (SDA_INp - SDA_INn), (SCL_OUTp - SCL_OUTn), and (SDA_OUTp SDA_OUTn) respectively. * A falling transition of the SDA_IN while the SCL_IN is high is defined as ”Header Condition“. Please refer to the section “2-pair Serial LVDS Input” for details. Copyright©2015 THine Electronics, Inc. 4 THine Electronics, Inc. Security E THL3512_Rev.1.03_E PIN CONFIGURATIONS OUT23 OUT22 OUT21 OUT20 OUT19 OUT18 MODE TEST A5 A4 VDD GND (Top View) 48 47 46 45 44 43 42 41 40 39 38 37 GND SDA_INn SDA_INp SCL_INn SCL_INp VDD GND SCL_OUTp SCL_OUTn SDA_OUTp SDA_OUTn GND 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 Exposed Pad (Bottom Side) OUT17 OUT16 OUT15 OUT14 OUT13 OUT12 OUT11 OUT10 OUT9 OUT8 OUT7 OUT6 OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 A0 A1 A2 A3 VDD GND 13 14 15 16 17 18 19 20 21 22 23 24 * The exposed pad is connected to GND inside the device. The exposed pad should be soldered to GND on the PCB. PIN DESCRIPTION Pin Name Type MODE Digital Input Serial Interface Input Mode Select Low: 2-pair Serial LVDS Input High: 3-wire Serial CMOS Input SCL_INp(SCK) LVDS Input/ Digital Input MODE=Low: 2-pair Serial LVDS Clock Input - Positive MODE=High: 3-wire Serial Clock Input (SCK) SCL_INn(CSn) LVDS Input/ Digital Input MODE=Low: 2-pair Serial LVDS Clock Input - Negative MODE=High: 3-wire Serial Chip Select Input (CSn) SDA_INp(SI) LVDS Input/ Digital Input MODE=Low: 2-pair Serial LVDS Data Input - Positive MODE=High: 3-wire Serial Data Input (SI) SDA_INn LVDS Input/ Digital Input MODE=Low: 2-pair Serial LVDS Data Input - Negative MODE=High: Reserved (Connect to Low) SCL_OUTp LVDS Output 2-pair Serial LVDS Clock Output - Positive SCL_OUTn LVDS Output 2-pair Serial LVDS Clock Output - Negative SDA_OUTp LVDS Output 2-pair Serial LVDS Data Output - Positive SDA_OUTn LVDS Output 2-pair Serial LVDS Data Output - Negative OUT0-OUT23 Open-Drain Output LED Driver Output Channel 0 - 23 TEST Digital Input Test Pin (Connect to Low) A0-A5 Digital Input Device address input Bit0 - 5 VDD ― Power supply GND ― Ground Copyright©2015 THine Electronics, Inc. Description 5 THine Electronics, Inc. Security E THL3512_Rev.1.03_E REGISTER NOTATION Address is noted in hex with the prefix “R“. Bit location is noted by “[]“. Register value is noted in binary with the suffix “b“. Register value is noted in decimal without a suffix. Register value is noted in hex with the suffix “h“. For example, R00 is a register of address 00. For example, R00[5:0] is bit 5 down to bit 0 of address 00. For example, R00[5:0]=000000b For example, R04[7:0]=160 For example, R04=A0h REGISTER MAP Address Default Function R00[7] 0 PWM Phase Control Mode R00[6] 0 LED Output Enable R00[5:0] - R01[7:0] R02[7:0] R03[7:0] R04[7:0] R05[7:0] R06[7:0] R07[7:0] R08[7:0] R09[7:0] R0A[7:0] 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h R0B[7:0] R0C[7:0] R0D[7:0] R0E[7:0] R0F[7:0] R10[7:0] R11[7:0] R12[7:0] R13[7:0] R14[7:0] R15[7:0] R16[7:0] 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h R17[7:0] R18[7:0] 00h 00h Individual Brightness - OUT0 Individual Brightness - OUT1 Individual Brightness - OUT2 Individual Brightness - OUT3 Individual Brightness - OUT4 Individual Brightness - OUT5 Individual Brightness - OUT6 Individual Brightness - OUT7 Individual Brightness - OUT8 Individual Brightness - OUT9 Individual Brightness - OUT10 Individual Brightness - OUT11 Individual Brightness - OUT12 Individual Brightness - OUT13 Individual Brightness - OUT14 Individual Brightness - OUT15 Individual Brightness - OUT16 Individual Brightness - OUT17 Individual Brightness - OUT18 Individual Brightness - OUT19 Individual Brightness - OUT20 Individual Brightness - OUT21 Individual Brightness - OUT22 Individual Brightness - OUT23 Copyright©2015 THine Electronics, Inc. 6 Description 0: Normal Mode 1: Group Control Mode 0: Output Disable 1: Output Enable internal fixation Individual Brightness=Value/256 THine Electronics, Inc. Security E THL3512_Rev.1.03_E FUNCTIONAL DESCRIPTION Writing to registers The device includes 25-byte registers (R00-R18) for setting. Writing to registers is executed through the serial interface and the value is maintained as long as power is applied. The register value can not be read. Writing to registers should be invoked after the power supply (VDD) of all the devices in cascading and multidrop connection gets stable above 3.0V. Then after power-up, if using 2-pair serial LVDS input, initialization of 2-pair serial LVDS input must be done before writing to registers. Writing to registers. However, in case all the registers are continuously rewritten, in other words repeatedly refreshed, the initialization of 2-pair serial LVDS input is not necessary after power-up and instantaneous interruption. Please refer to the section “Initialization of 2-pair Serial LVDS Input” for details. UVLO The device has an internal UVLO (Under-Voltage Locked-Out) circuit to prevent the device from malfunction at low supply voltage. Until power supply (VDD) has reached 2.5V (typical value), the UVLO holds the internal logic circuit in a reset condition, and keeps the LED driver outputs and LVDS outputs in Hi-Z state. The UVLO circuit has hysteresis. If power supply falls below 2.4V (typical value), the device gets into the above UVLO state in which the internal logic circuit is reset and the regsiters are reset to default value. UVLO Threshold(2.5V typ.) Hysterisys (0.1V typ.) Power Supply(VDD) Internal Reset Signal (Active-Low) Overcurrent Protection The device includes overcurrent protection circuits for each LED output pin to prevent the LED driver outputs from driving excessive current. If LED driver outputs turn on with the pins shorted to power supply, overcurrent flowing in output transistors may causes permanent damage to the device. The overcurrent protection is a function to shutdown outputs immediately when the device detects overcurrent condition on output pins. If short circuit condition is resolved, normal operation automatically resumes. However, this function can not always prevent breakdown or damage to the device depending on usage situation and duration of abnormality. Thermal Shutdown The device includes thermal shutdown circuit to prevent damages caused by excessive heat. If the junction temperature exceeds the absolute maximum rating (Tj=150 °C), the thermal shutdown circuit turn off all LED driver outputs. The Thermal shutdown circuits has hysteresis. If Tj falls enough, normal operation automatically resumes. However, this function can not always prevent breakdown or damage to the device depending on usage situation and duration of abnormality. Copyright©2015 THine Electronics, Inc. 7 THine Electronics, Inc. Security E THL3512_Rev.1.03_E Serial Communication Protocol 2-pair serial LVDS input or 3-wire serial CMOS level input is selected as a serial interface for register setting by the MODE pin. The 2-pair serial LVDS input and 3-wire serial CMOS level input share input pins (SCL_INp/SCL_INn, SDA_INp/SDA_INn) which are used as 2-pair serial LVDS input when the MODE pin is set to low, and used as 3-wire serial CMOS level input when the MODE pin is set to high. - The serial interface is clock synchronous and used only for writing to registers (one-way communication). - The data length is 8-bit in MSB first bit order. As for how to recognize the first bit, please refer to the section “2-pair serial LVDS input” and “3-wire serial CMOS level input”. - The first 8 bits that includes the first bit is defined as “1st byte” and the next 8 bits as “2nd byte” and so on. - “1st Byte” is assigned to the device address. If device address is set to 00h, all the devices are selected to be written except the device which has a device address 00111111 by the A5-A0 pins. - “2nd Byte” is assigned to the register address. - The bytes after “3rd Byte” is assigned to register values to write. The register address is incremented every time 8-bit register value is written. For example, the value of “3rd Byte” is written to the register at the address indicated in “2nd byte“, and the value of “4th byte” is written to the register at the address (“2nd byte“+1). - Don’t write except the registers R00-R18 < Serial Data > 1st Byte 2nd Byte Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Register Address Device Address The first bit 3rd Byte Last Byte Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Register Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Register Value Device Address Setting The lower 6 bits out of 8-bit serial interface device address are set by the A0-A5 pin.The higher 2 bits are fixed at 00. For example, in case A5=Low, A4=Low, A3=Low, A2=Low, A1=Low, A0=High, the device address is set to 00000001 (01h). - If the A0-A5 pins are all set to high, the register of the device can not be written. Please set all the A0-A5 pins to high in order to use only 2-pair to 2-pair repeater function or 3-wire to 2-pair bridge function without using LED driver outputs. - Since the device address 00000000 (00h) is the one to be used for writing to all devices, basically don’t use it. - Please set device addresses within the range from 00000001 (01h) to 00111110 (3Eh). Copyright©2015 THine Electronics, Inc. 8 THine Electronics, Inc. Security E THL3512_Rev.1.03_E Serial Interface Connection THL3512 is protocol compatible with LED drivers series of opendrain outputs and constant current outputs so that can be mixed in cascade and multidrop connection scheme .(Please note that multiple LVDS outputs can not be connected to each other.) *LED drivers series of opendrain outputs and constant current outputs are referred to collectively as THL35XX hereafter. Cascade Connection by 2-pair serial LVDS The THL35XX can convert 3-wire serial output from the host such as micro-controller or CPU to 2-pair serial LVDS, which is connected to the 2-pair serial LVDS input of a following device in a point-to-point topology. As for the maximum number of devices to be cascaded, please refer to an application note. 2-pair serial LVDS 3-wire serial CSn Host 2-pair serial LVDS SCL SCK THL35XX SI THL35XX THL35XX SDA MODE pin=High MODE pin=Low MODE pin=Low Multidrop Connection by 2-pair serial LVDS The THL35XX can convert 3-wire serial output from the host such as micro-controller or CPU to 2-pair serial LVDS, which is connected to the 2-pair serial LVDS input of following multiple devices in a multidrop topology. As for the maximum number to devices to be multidropped, please refer to an application note. 2-pair serial LVDS 3-wire serial CSn Host SCK SCL THL35XX SI SDA MODE pin=High THL35XX THL35XX MODE pin=Low MODE pin=Low Multidrop Connection by 3-wire serial 3-wire serial output from the host such as micro-controller or CPU to 2-pair serial LVDS is connected to following multiple devices in a multidrop topology. CSn Host 3-wire serial SCK SI THL35XX THL35XX MODE pin=High MODE pin=High Copyright©2015 THine Electronics, Inc. 9 THine Electronics, Inc. Security E THL3512_Rev.1.03_E 3-wire Serial CMOS Level Input When the MODE pin is set to high, the serial interface for writing to registers becomes 3-wire serial CMOS level input. The chip select (CSn), serial clock (SCK), serial data (SI) of 3-wire serial CMOS level input are input to the SCL_INn pin, the SCL_INp pin, the SDA_IN pin respectively. The SDA_INn must be tied to low. - While the CSn stays low, the data input SI is latched by rising edges of the clock input SCK. - The data latched by the first clock rising edge after the CSn falls is assigned the “first bit“. - The “Last Byte” is written to a register when the CSn rises after Bit0 (in other words, “Last Byte” will not be written to a register until the CSn rises). - If the CSn rises in the middle of a byte, the byte is not written to a register, then the communication resumes from “1st Byte” when the CSn falls next. < 3-wire Serial CMOS Level Input > SCL_INn (CSn) 7 6 5 4 3 2 1 0 7 6 7 6 5 4 3 2 1 0 SCL_INp (SCK) SDA_INp (SI) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 “1st Byte“ bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 “2nd Byte“ “Last Byte“ 2-pair serial LVDS When the MODE pin is set to low, the serial interface for writing to registers becomes 2-pair serial LVDS input (SCL_INp/SCL_INn, SDA_INp/SDA_INn). - The data input SDA_IN is latched by rising edges of the clock input SCL_IN. - A falling transition of the SDA_IN while the SCL_IN is high is defined as ”Header Condition“, and the data latched by the first clock rising edge after the “Header Condition” is assigned the “first bit“. Except ”Header Condition”, the transitions of the data input SDA_IN are allowed while the clock input SCL_IN is low. - The “Last Byte” is written to a register at the reception of an active-low pulse “End Pulse” (actually, “Last Byte” is written to a register at the rising edge of the “End Pulse“). When the “End Pulse” rises, the data output SDA_OUT must be high. - If the ”Header Condition” is received in the middle of a byte, the byte is not written to a register, then the communication resumes from “1st Byte“. < 2-pair serial LVDS input > 7 6 5 4 3 2 1 0 7 6 7 6 5 4 3 2 1 0 End Pulse SCL_IN SDA_IN bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 Header Condition “1st Byte“ “2nd Byte“ bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 “Last Byte“ * The 3-wire to 2-pair bridge function can convert 3-wire serial output from the host such as micro-controller or CPU to 2-pair sereal LVDS. Please refer to the section “3-wire to 2-pair bridge function” for details. Copyright©2015 THine Electronics, Inc. 10 THine Electronics, Inc. Security E THL3512_Rev.1.03_E 3-wire to 2-pair bridge function When the MODE pin is set to high, the serial interface for writing to registers becomes 3-wire serial CMOS level input (CSn, CK, SI), which is converted to 2-wire serial and transferred to the LVDS output pins. - While the CSn is active low, the data input SI is latched and transferred to the LVDS output SDA_OUT on the rising edges of the clock input SCK. There is about 10ns setup time between the clock output SCL_OUT and the data output SDA_OUT. - When the CSn falls, “Header Condition” is generated on 2-pair LVDS output. - After the CSn rises, an active-low pulse "End Pulse” (the pulse width: 40ns typ) is added on the clock output SCL_OUT. - When the CSn rises, the data output SDA_OUT is forced high. In the result, the low to high transition of the clock output SCL_OUT "End Pulse” occurs while the data output SDA_OUT is high < 3-wire to 2-pair bridge > SCL_INn (CSn) 7 6 5 4 3 1 2 0 7 6 7 6 5 4 3 1 2 0 SCL_INp (SCK) SDA_INp (SI) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 7 6 5 4 3 1 2 0 7 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 6 7 6 5 4 3 1 2 0 End Pulse SCL_OUT SDA_OUT bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 Header Condition “1st Byte“ “2nd Byte“ “Last Byte“ 2-pair to 2-pair repeater function When the MODE pin is set to low, the serial interface for writing to registers becomes 2-pair serial LVDS input (SCL_INp/SCL_INn, SDA_INp/SDA_INn). The timing between the clock and the data is compensated and then they are transferred to the LVDS output pins. - The data input SCL_IN is latched and transferred to the LVDS output SDA_OUT on the rising edges of the clock input SCL_IN. There is about 10ns setup time between the clock output SCL_OUT and the data output SDA_OUT. - The “Header Condition” is regenerated and transferred to the output. < 2-pair to 2-pair repeater function > 7 6 5 4 3 1 2 0 7 6 7 6 5 4 3 0 End Pulse 1 2 SCL_IN SDA_IN bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Header Condition 7 6 5 4 3 2 1 0 7 6 7 6 5 4 3 2 1 0 SCL_OUT SDA_OUT bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 “1st Byte“ Copyright©2015 THine Electronics, Inc. “2nd Byte“ 11 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 “Last Byte“ THine Electronics, Inc. Security E THL3512_Rev.1.03_E Initialization of 2-pair Serial LVDS Input After power-up, if using 2-pair serial LVDS input, initialization of 2-pair serial LVDS input must be done before writing to registers. Without the initialization of 2-pair serial LVDS input, the first writing to registers (“1st Byte”-”Last Byte”) may possibly fail. However, the initialization of 2-pair serial LVDS input is not necessary in case failure in the first writing to registers can be allowed; for example, in case all the registers (R00-R18) are continuously rewritten, in other words repeatedly refreshed. In order to initialize 2-pair serial LVDS input, please input active-low pulse (pulse width: 200ns min.) of the CSn into 3wire serial CMOS level input of the first device which converts 3-wire to 2-pair. In consequence, the 2-pair serial LVDS input of all the following devices are initialized. In cascading connection, it takes the propagation delay of all stages in cascaded chain to finish the initialization of 2-pair serial LVDS input. 2-pair serial LVDS 3-wire serial CSn Host SCK 2-pair serial LVDS SCL THL35XX SI THL35XX SDA Active-low pulse input 2-pair serial LVDS inputs to be initialized < Initialization of 2-pair Serial LVDS Input > Initialization Pattern Example 1 Input active-low pulse input to the CSn SCL_INn (CSn) 3-wire serial CMOS level input 2-pair serial LVDS Output Min.200ns SCL_INp (SCK) (High) SDA_INp (SI) (High) SCL_OUT SDA_OUT Initialization Pattern Initialization Pattern Example 2 Input 1st Byte (Device Address)=FFh SCL_INn (CSn) 3-wire serial CMOS level input 7 6 SDA_INp (SI) 4 3 1 2 0 (High) 7 2-pair serial LVDS Output 5 SCL_INp (SCK) 6 5 4 3 2 1 0 SCL_OUT SDA_OUT Initialization Pattern Copyright©2015 THine Electronics, Inc. 12 THine Electronics, Inc. Security E THL3512_Rev.1.03_E Individual Brightness Control The Brightness for each LED output channel (OUT0-OUT23) are individually programmable in 256 steps by the register configuration (R01-R15). The individual Brightness is controlled by PWM duty cycle. The ratio of ON time for the open-drain outputs is expressed in the following equation. ON time ratio = Individual Brightness Control Register Value / 256 The bigger setting value results in the larger ON time ratio, therefore higher brightness. When the register value is 0, the output current sink is held OFF, therefore the LED turns off. < Individual Brightness Control > approximately 290μs Individual Brightness:255 ON ON Dugy=255/256 OFF Individual Brightness:254 ON ON Dugy =254/256 OFF ON Individual Brightness:2 OFF ON Dugy=2/256 ON Individual Brightness:1 OFF ON Dugy =1/256 Individual Brightness:0 OFF ON Dugy =0/256 PWM Phase Control Mode The PWM pulse start position of each channel is controlled in different phases to reduce switching noise. The phase control mode is selectable in 2 ways by the register configuration (R00[7]). In normal mode (R00[7]=0), the PWM pulse start positions of all channels are different from each other. In group control mode (R00[7]=1), the PWM pulse start positions of 2 or 3 channel groups are different from each other. < PWM Phase Control Mode > Normal Mode(R00[7]=0) OUT0 ON OUT1 ON ON OUT2 ON ON ON Delay Delay Delay Copyright©2015 THine Electronics, Inc. Delay 13 THine Electronics, Inc. Security E THL3512_Rev.1.03_E < PWM Phase Control Mode > Group Control Mode(R00[7]=1) Group 0 Group 1 OUT0 ON ON OUT1 ON ON OUT2 ON ON OUT3 ON ON OUT4 ON ON OUT5 ON ON Delay Delay When multiple LED output channels need to be connected in parallel to drive, the PWM phase control mode must be set to group control mode (R00[7]=1), and the channels in the same group must be connected in parallel to drive. < Grouping of Group Control Mode > Group Group0 Group1 Group2 Group3 Group4 Group5 Group6 Group7 Output Channel OUT0, OUT1, OUT2 OUT3, OUT4, OUT5 OUT6, OUT7, OUT8 OUT9, OUT10, OUT11 OUT12, OUT13, OUT14 OUT15, OUT16, OUT17 OUT18, OUT19, OUT20 OUT21, OUT22, OUT23 Pin Name OUT(n) Same group OUT(n+1) OUT(n+2) LED Driver Output Enable All of the LED driver outputs can be disabled by register configuration (R00[6]). When disabled (R00[6]=0), all of the LED driver outputs go into OFF (Hi-Z) state, LEDs turn off. Copyright©2015 THine Electronics, Inc. 14 THine Electronics, Inc. Security E THL3512_Rev.1.03_E Package Dimensions QFN 48-pin 0 .0 5 S 0 .9 0 M A X 0 .6 5 ～ 0 .7 0 0 .2 0 R E F . 0 .0 5 M A X 0 .1 0 7 .0 0 b s c 7 .0 0 b s c S 1 P IN IN D E X T O P V IE W S E A T IN G P L A N E S ID E V IE W 5 .5 0 + /-0 .1 0 0 .3 5 5 .5 0 + /-0 .1 0 0 .0 9 R M IN 0 .3 5 1 P IN IN D E X 0 .2 0 R 0 .4 5 ① 0 .4 0 + /-0 .0 5 48 0 .5 0 b s c 0 .4 0 + /-0 .0 5 0 .2 5 + 0 .0 5 /-0 .0 7 B O T T O M V IE W Copyright©2015 THine Electronics, Inc. U n it:m m 15 THine Electronics, Inc. Security E THL3512_Rev.1.03_E Notices and Requests 1. The product specifications described in this material are subject to change without prior notice. 2. The circuit diagrams described in this material are examples of the application which may not always apply to the customer’s design. We are not responsible for possible errors and omissions in this material. Please note if errors or omissions should be found in this material, we may not be able to correct them immediately. 3. This material contains our copy right, know-how or other proprietary. Copying or disclosing to third parties the contents of this material without our prior permission is prohibited. 4. Note that if infringement of any third party's industrial ownership should occur by using this product, we will be exempted from the responsibility unless it directly relates to the production process or functions of the product. 5. This product is presumed to be used for general electric equipment, not for the applications which require very high reliability (including medical equipment directly concerning people's life, aerospace equipment, or nuclear control equipment). Also, when using this product for the equipment concerned with the control and safety of the transportation means, the traffic signal equipment, or various Types of safety equipment, please do it after applying appropriate measures to the product. 6. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged to have sufficiently redundant or error preventive design applied to the use of the product so as not to have our product cause any social or public damage. 7. Please note that this product is not designed to be radiation-proof. 8. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under the Foreign Exchange and Foreign Trade Control Law. 9. The product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings or malfunction, if pins of the product are shorted by such as foreign substance. The damageｓ may cause a smoking THine Electronics, Inc. E-mail: [email protected] Copyright©2015 THine Electronics, Inc. 16 THine Electronics, Inc. Security E