(Preliminary) PL613-05 1.8V-3.3V PicoPLL, 3-PLL, 200MHz, 3 Output Clock IC FEATURES • • • • • • • • • DESCRIPTION Designed for PCB space savings with 3 low-power The PL613-05 is an advanced triple PLL design Programmable PLLs and 3 distinct clock outputs. based on PhaseLink’s PicoPLL, world’s smallest programmable clock, technology. This flexible Low-power consumption (<10µA when PDB is programmable architecture is ideal for high activated) performance, low-power, low-cost applications. When Output frequency: using the power down (PDB) feature the PL613-05 o < 110MHz @ 1.8V operation consumes less than 10 µA of power. Besides its small o < 166MHz @ 2.5V operation form factor and 3 distinct outputs that can reduce o < 200MHz @ 3.3V operation overall system costs, the PL613-05 offers superior Input frequency: phase noise, jitter and power consumption o Fundamental Crystal: 10MHz to 40MHz performance. o Reference Input: 10MHz to 200MHz Programmable I/O pins can be configured as Output Enable (OE), Power Down (PDB) inputs, or Clock output. Disabled outputs programmable as HiZ or Active Low Single 1.8V to 3.3V, ±10% power supply Operating temperature range from -40°C to 85°C Available in GREEN/RoHS compliant SOP-8L package. PIN CONFIGURATION 1 CLK2, OEM^, PDB^ 2 VDD 3 CLK0 4 PL613-05 XIN, FIN 8 XOUT 7 VDD 6 CLK1 5 GND SOP-8L ^ Denotes internal pull up BLOCK DIAGRAM FREF XIN/FIN XOUT PDB Programming Interface OEM Xtal OSC FREF Programmable PLL1 VCO1 Programmable PLL2 VCO2 Odd/Even Divider (5-bits) %1, %2, %4, %8 Odd/Even Divider (5-bits) CLK1 CLK0 FREF Programmable Function Programmable PLL3 VCO3 Odd/Even Divider (5-bits) %1, %2, %4, %8 CLK2, OEM, PDB 2880 Zanker Road, San Jose, CA 95134, (Tel) 408-571-1668, (Fax) 408-571-1688 www.phaselink.com Rev 09/16/11 Page 1 (Preliminary) PL613-05 1.8V-3.3V PicoPLL, 3-PLL, 200MHz, 3 Output Clock IC PACKAGE PIN ASSIGNMENT Package Pin # Type XIN, FIN 1 I CLK2, OEM, PDB 2 B* VDD 3, 7 P Crystal or Reference Clock input - Programmable Clock (CLK2) output, or - Output Enable Master (OEM) for all clock outputs, or - Power Down mode (PDB) input VDD connection CLK0 4 B* Programmable Clock (CLK0) output GND 5 P GND connection CLK1 6 O Programmable Clock (CLK1) output XOUT 8 O Crystal output pin. Do Not Connect when using FIN Name Description * Note: All bidirectional buffers (I/Os) incorporate an internal 60KΩ pull up resistor except when PDB mode is used. In configurations that use PDB, the PDB pin will have a 10MΩ pull up resistor. KEY PROGRAMMING PARAMETERS CLK[ 0:2 ] Output Frequency CLK[0] F VCO2 / P CLK[1,2] F VCOx / (P*(1,2,4,8)) or F REF / (P*(1,2,4,8)) Where F VCO = F REF * M / R M = 11 bit R = 8 bit P = 5 bit (Odd/Even Divider) Output Drive Strength Each output has three optional drive strengths to choose from. They are: • • • Low: 4mA Std: 8mA (default) High:16mA Programmable Input/Output Most pins are multi-function I/Os and can be configured as: • OEM – (Master OE controlling all outputs) • PDB – (Power Down) • CLK[0:2] – (Output) • HiZ or Active Low disabled state 2880 Zanker Road, San Jose, CA 95134, (Tel) 408-571-1668, (Fax) 408-571-1688 www.phaselink.com Rev 09/16/11 Page 2 (Preliminary) PL613-05 1.8V-3.3V PicoPLL, 3-PLL, 200MHz, 3 Output Clock IC FUNCTIONAL DESCRIPTION The PL613-05 is a highly featured, very flexible, advanced triple PLL design for high performance, low-power applications. The device accepts a low-cost fundamental crystal input of 10MHz to 40MHz or a reference clock input of 10MHz to 200MHz and is capable of producing 3 distinct output frequencies up to 200MHz. All 3-PLLs are fully programmable, with a total of four, 5-bit Post VCO, Odd/Even (patent pending) ‘P-counter’ dividers with additional 1, 2, 4 or 8 ‘Post P-counter’ dividers to allow generating the most demanding frequencies easily. The outputs can be programmed to deliver the generated frequencies from the PLLs, or the reference input. Each bidirectional feature pin (I/O) on the PL613-05 incorporates a 60K Ω pull up resistor (10MΩ for PDB function) and can be configured to perform various functions. Usage of various design features of these products is mentioned in the following paragraphs. PLL Programming The three PLLs in PL613-05 are fully programmable. Each PLL is equipped with an 8-bit input frequency divider (R-Counter) and an 11-bit VCO frequency feedback loop (M-Counter) divider. The three PLL outputs are transferred to four 5-bit post VCO, Odd/Even (patent pending) dividers (P-Counter), as shown in the above diagrams. In addition, there are three optional (÷1, ÷2, ÷4 or ÷8) post P-Counter dividers, that can further divide the VCO frequencies. In general, the PLL output frequency is determined by the following formula F OUT = (F REF *M) / (R*P) For output calculations, please note that ‘P’ includes the ‘P’ counter bits plus the additional optional (÷1, ÷2, ÷4 or ÷8) dividers, if used. CLKx (Clock Outputs) There are 3 distinct output frequencies available on the PL613-05. Clock output frequencies can be configured as follows: CLK[0] F VCO2 / P CLK[1,2] F VCOx / (P*(1,2,4,8)) or F REF / (P*(1,2,4,8)) Each output can be programmed with a 4mA, 8mA, or 16mA drive strength. The maximum output frequency is 200MHz @ 3.3V, 166MHz @ 2.5V or 110MHz @ 1.8V. OEM (Master Output Enable) One pin can be configured to be a single Master OE (OEM) input pin that controls all the outputs of the PL613-05. In addition the state of the disabled outputs can be programmed to float (Hi Z) or Active ‘0’. The OEM pin incorporates a 60kΩ pull up resistor for normal operating condition. The logic for OEM is shown below: OEM OE Type Osc PLL Output Pin (Programmable) 0 (Default) On On Hi Z 0 1 On On Active ‘0’ 1 Normal Operation (Default) Note: Typical enable time is 10ns. Power-Down Control (PDB) When activated, PDB ‘Disables all the PLLs, the oscillator circuitry, counters, and all other active circuitry. PDB activation disables all outputs and the IC consumes <10µA of power. The PDB input incorporates a 10MΩ pull up resistor for normal operating condition. The PDB feature can be programmed to allow the output to float (Hi Z), or to operate in the ‘Active low’ mode. The logic for PDB is shown below: PDB PDB Type Osc PLL Output Pin Program 0 (Default) Off Off Hi Z 0 1 Off Off Active ‘0’ 1 Normal Operation (Default) Note: Typical enable time is <2ms. 2880 Zanker Road, San Jose, CA 95134, (Tel) 408-571-1668, (Fax) 408-571-1688 www.phaselink.com Rev 09/16/11 Page 3 (Preliminary) PL613-05 1.8V-3.3V PicoPLL, 3-PLL, 200MHz, 3 Output Clock IC LAYOUT RECOMMENDATIONS The following guidelines are to assist you with a performance optimized PCB design: Signal Integrity and Termination Considerations - Keep traces short! - Trace = Inductor. With a capacitive load this equals ringing! - Long trace = Transmission Line. Without proper termination this will cause reflections (looks like ringing). - Design long traces (<1 inch) as “striplines” or “microstrips” with defined impedance. - Match trace at one side to avoid reflections bouncing back and forth. - Place decoupling capacitors as close as possible to the V DD pin(s) to limit noise from the power supply - Multiple V DD pins should be decoupled separately for best performance. - Addition of a ferrite bead in series with V DD can help prevent noise from other board sources - Value of decoupling capacitor is frequency dependant. Typical values to use are 0.1µF for designs using frequencies < 50MHz and 0.01µF for designs using frequencies > 50MHz. Crystal Tuning Circuit Series and parallel capacitors used to fine tune the crystal load to the circuit load. Typical CMOS termination Place Series Resistor as close as possible to CMOS output CMOS Output Buffer (Typical buffer impedance 20Ω) Decoupling and Power Supply Considerations Crystal To CMOS Input 50Ω line Cst Series Resistor Use value to match output buffer impedance to 50Ω trace. Typical value 30Ω XIN XOUT 1 Cpt 8 Cpt CST – Series Capacitor, used to lower circuit load to match crystal load. Raises frequency offset. This can be eliminated by using a crystal with a Cload of equal or greater value than the oscillator. CPT – Parallel Capacitors, Used to raise the circuit load to match the crystal load. Lowers frequency offset. 2880 Zanker Road, San Jose, CA 95134, (Tel) 408-571-1668, (Fax) 408-571-1688 www.phaselink.com Rev 09/16/11 Page 4 (Preliminary) PL613-05 1.8V-3.3V PicoPLL, 3-PLL, 200MHz, 3 Output Clock IC ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PARAMETERS SYMBOL MIN. MAX. UNITS V DD -0.5 4.6 V Input Voltage Range VI -0.5 V DD +0.5 V Output Voltage Range VO -0.5 V DD +0.5 V 260 °C Supply Voltage Range Soldering Temperature (Green package) 10 Data Retention @ 85°C Storage Temperature TS Ambient Operating Temperature* Year -65 150 °C -40 85 °C Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only. AC SPECIFICATIONS PARAMETERS Crystal Input Frequency (XIN) CONDITIONS Fundamental Crystal MIN. TYP. 10 @ V DD =3.3V Input (FIN) Frequency @ V DD =2.5V MAX. UNITS 40 MHz 200 10 166 @ V DD =1.8V MHz 110 Input (FIN) Signal Amplitude Internally AC coupled (High Frequency) 0.9 VDD Vpp Input (FIN) Signal Amplitude Internally AC coupled (Low Frequency) 3.3V < 50MHz, 2.5V < 40MHz, 1.8V < 15MHz 0.1 VDD Vpp Output Frequency Settling Time Output Enable Time @ VDD =3.3V 200 @ VDD =2.5V 166 @ VDD =1.8V 110 MHz At power-up (after VDD increases over 1.62V) 2 ms OE Function; Ta=25º C, 15pF Load 10 ns PDB Function; Ta=25º C, 15pF Load 2 ms 2 ppm VDD Sensitivity Frequency vs. VDD +/-10% -2 Output Rise Time 15pF Load, 10/90% VDD, High Drive, 3.3V 1.2 1.7 ns Output Fall Time 15pF Load, 90/10% VDD, High Drive, 3.3V 1.2 1.7 ns Duty Cycle PLL Enabled, @ VDD /2, High Drive 50 55 % Period Jitter, Pk-to-Pk* (10,000 samples) Configuration Dependant, with capacitive decoupling between V DD and GND. 45 300 * Note: Jitter performance depends on the programming parameters. 2880 Zanker Road, San Jose, CA 95134, (Tel) 408-571-1668, (Fax) 408-571-1688 www.phaselink.com Rev 09/16/11 Page 5 ps (Preliminary) PL613-05 1.8V-3.3V PicoPLL, 3-PLL, 200MHz, 3 Output Clock IC DC SPECIFICATIONS PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Supply Current, Dynamic, Loaded CMOS Outputs I DD All outputs @ 20MHz 10pF Load 15 21 mA Supply Current, Dynamic, Loaded CMOS Outputs I DD All outputs @ 20MHz 10pF Load 11 16 mA Supply Current, Dynamic, Loaded CMOS Outputs I DD All outputs @ 20MHz 10pF Load 8.5 11 mA Supply Current I DD When PDB=0 All outputs @ 20MHz 10pF Load, V DD = 3.3V <10 µA Operating Voltage V DD 3.3V Operation 2.97 3.3 3.63 2.5V Operation 2.25 2.5 2.75 1.8V Operation 1.62 1.8 1.98 Output Low Voltage V OL I OL = +4mA Std Drive Output High Voltage V OH I OH = -4mA Std Drive Output Current, Low Drive I OSD Output Current, Std Drive Output Current, High Drive 0.4 V V V DD – 0.4 V V OL = 0.4V, V OH = 2.4V 4 mA I OSD V OL = 0.4V, V OH = 2.4V 8 mA I OHD V OL = 0.4V, V OH = 2.4V 16 mA CRYSTAL SPECIFICATIONS PARAMETERS Fundamental Crystal Resonator Frequency Crystal Loading Rating SYMBOL MIN F XIN 10 C L (xtal) Operating Drive Level Metal Can Crystal Small SMD Crystal TYP ESR Max Shunt Capacitance ESR Max UNITS 40 MHz 15 0.1 Shunt Capacitance MAX pF 2 mW C0 5.5 pF ESR 40 Ω C0 2.5 pF ESR 60 Ω 2880 Zanker Road, San Jose, CA 95134, (Tel) 408-571-1668, (Fax) 408-571-1688 www.phaselink.com Rev 09/16/11 Page 6 (Preliminary) PL613-05 1.8V-3.3V PicoPLL, 3-PLL, 200MHz, 3 Output Clock IC PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT) SOP-8L Symbol A A1 A2 b C D E H L e Dimension in MM Min. Max. 1.35 1.75 0.10 0.25 1.25 1.50 0.33 0.53 0.19 0.27 4.80 5.00 3.80 4.00 5.80 6.20 0.40 0.89 1.27 BSC E H D A2 A A1 C e b 2880 Zanker Road, San Jose, CA 95134, (Tel) 408-571-1668, (Fax) 408-571-1688 www.phaselink.com Rev 09/16/11 Page 7 L (Preliminary) PL613-05 1.8V-3.3V PicoPLL, 3-PLL, 200MHz, 3 Output Clock IC ORDERING INFORMATION (GREEN PACKAGE COMPLIANT) For part ordering, please contact our Sales Department: 2880 Zanker Road, San Jose, CA 95134, USA Tel: (408) 571-1668 Fax: (408) 571-1688 PART NUMBER The order number for this device is a combination of the following: Part number, Package type and Operating temperature range PL613-05- XXX PART NUMBER XX X 3 DIGIT ID Code * (will be assigned at programming time) NONE= TUBE R=TAPE and REEL PACKAGE TYPE S=SOP-8L TEMPERATURE C=COMMERCIAL (0°C to 70°C) I= INDUSTRIAL (-40°C to +85°C) * PhaseLink will assign a unique 3-digit ID code for each approved programmed part number. Part Number/Order Number PL613-05-XXXSC PL613-05-XXXSI PL613-05-XXXSC-R PL613-05-XXXSI-R Marking † P613-05 XXX LLLLL (1) P613-05 XXX LLLLL (1) Package Option 8-Pin SOP (Tube) 8-Pin SOP (Tape and Reel) † Marking Notes : 1) LLLLL represents the production lot number PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. Solder reflow profile available at www.phaselink.com/QA/solderingGreen.pdf 2880 Zanker Road, San Jose, CA 95134, (Tel) 408-571-1668, (Fax) 408-571-1688 www.phaselink.com Rev 09/16/11 Page 8