PLL PL612-05

(Preliminary)
1.8V-3.3V PicoPLL, 2-PLL, 200MHz, 5 Output Clock IC
FEATURES
DESCRIPTION
 Designed for PCB space savings with 2 low-power
Programmable PLLs and up to 5 clock outputs.
 Low-power consumption (<10µA when PDB is
activated)
 Output frequency:
o <133MHz @ 1.8V operation
o <166MHz @ 2.5V operation
o <200MHz @ 3.3V operation
 Input frequency:
o Fundamental Crystal: 10MHz - 50MHz
o Reference Input: 1MHz - 200MHz
 Programmable I/O pins can be configured as Output
Enable (OE), Configuration Switching (CSEL), Power
Down (PDB) input, or Clock outputs.
 Single 1.8V ~ 3.3V, ± 10% power supply
 Operating temperature range from -40C to 85C
 Available in GREEN/RoHS compliant SOP-8L or
MSOP-10L packages..
The PL612-05 is an advanced dual PLL design based
on PhaseLink’s PicoPLL TM , world’s smallest
programmable clock, technology. This flexible
programmable architecture is ideal for high
performance, low-power, low-cost applications. When
using the power down (PDB) feature the PL612-05
consumes less than 10 µA of power, while its
Configuration Select (CSEL) function allows switching
of 2 programmable configurations. Besides its small
form factor and 3 or 5 outputs that can reduce overall
system costs, the PL612-05 offers superior phase
noise, jitter and power consumption performance.
PIN CONFIGURATION
10
XIN, FIN
CLK4, CSEL^
2
9
XOUT
CLK2, OEM^, PDB^
3
8
VDD
VDD
4
7
CLK1
CLK3
5
6
CLK0
XIN, FIN
1
CLK2, OEM^, PDB^
2
VDD
3
CLK0
4
MSOP-10L
PL612-05
1
PL612-05
GND
8
XOUT
7
VDD
6
CLK1
5
GND
SOP-8L
^ Denotes internal pull up
BLOCK DIAGRAM
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 9/4/07 Page 1
(Preliminary)
1.8V-3.3V PicoPLL, 2-PLL, 200MHz, 5 Output Clock IC
PACKAGE PIN ASSIGNMENT
Name
Package Pin #
Type
MSOP-10L SOP-8L
Description
XIN, FIN
10
1
I
Crystal or Reference Clock input
CLK4, CSEL
2
-
B*
- Programmable Clock (CLK4) output or
- Configuration Switching input
CLK2, OEM,
PDB
3
2
B*
- Programmable Clock (CLK2) output, or
- Output Enable Master (OEM) for all clock outputs, or
- Power Down mode (PDB) input
VDD
4, 8
3, 7
P
VDD connection
CLK3
5
-
O
Programmable Clock (CLK3) output
CLK0
6
4
B*
Programmable Clock (CLK0) output
GND
1
5
P
GND connection
CLK1
7
6
O
Programmable Clock (CLK1) output
XOUT
9
8
O
Crystal output pin. Do Not Connect when using FIN
* Note: All bidirectional buffers (I/Os) incorporate an internal 60KΩ pull up resistor except when PDB mode is used. In
configurations that use PDB, the PDB pin will have a 10MΩ pull up resistor.
KEY PROGRAMMING PARAMETERS
CLK[ 0:4 ]
Output Frequency
CLK[0]
F VCO2 / P
CLK[1]
F VCO1 / (P*(1,2,4,8)) or F REF / (P*(1,2,4,8))
CLK[2]
F REF / (P*(1,2,4,8))
CLK[3]
F VCO2 / (P*(1,2,4,8)) or F REF / (P*(1,2,4,8))
Output Drive Strength
Each output has
three optional drive
strengths to choose
from. They are:
 Low: 4mA
 Std: 8mA (default)
 High:16mA
Programmable Input/Output
Most pins are multi-function I/Os and can be
configured as:
 OEM – (Master OE controlling all outputs)
 CSEL – (Device Configuration Switching)
 PDB – (Power Down)
 CLK[0:4] – (Output)
 HiZ or Active Low disabled state
CLK[4]
F REF / P
Where F VCO = F REF * M / R
M = 11 bit
R = 8 bit
P = 5 bit (Odd/Even Divider)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 9/4/07 Page 2
(Preliminary)
1.8V-3.3V PicoPLL, 2-PLL, 200MHz, 5 Output Clock IC
FUNCTIONAL DESCRIPTION
The PL612-05 is a highly featured, very flexible, advanced Dual PLL design for high performance, low-power
applications. Starting from a low-cost fundamental input crystal of 10MHz to 50MHz or a reference clock input of
1MHz to 200MHz, the PL612 is capable of producing 3 (SOP-8L) or 5 (MSOP-10L) distinct output frequencies of up
to 200MHz. Both PLLs are fully programmable, with a total of three Odd/Even (patent pending) ‘5-bit’ Post VCO
(P-counter) dividers with additional 1, 2, 4 or 8 ‘Post P-counter’ dividers to allow generating the most demanding
frequencies easily. The outputs can be programmed to deliver the generated frequencies from the PLLs, or the
reference input. Each bidirectional feature pin (I/O) on the PL613-05 incorporates a 60KΩ pull up resistor (10MΩ
for PDB function) and can be configured to perform various functions. Usage of various design features of these
products is mentioned in the following paragraphs.
PLL Programming
The two PLLs in PL612-05 are fully programmable.
Each PLL is equipped with an 8-bit input frequency
divider (R-Counter) and an 11-bit VCO frequency
feedback loop (M-Counter) divider. The PLL outputs
are transferred to Odd/Even (patent pending) 5-bit
post VCO dividers (P-Counter), as shown in the
above diagrams. In addition, there are three optional
(÷1, ÷2, ÷4 or ÷8) ‘post P-Counter’ dividers that can
further divide the VCO frequency. In general, the
PLL output frequency is determined by the following
formula
F OUT = (F REF *M) / (R*P).
For output calculations, please note that ‘P’ includes
the ‘P’ counter bits plus the additional optional (÷1,
÷2, ÷4 or ÷8) dividers, if used.
CLKx (Clock Outputs)
There are a maximum of 3 (SOP-8L) or 5 (MSOP10L) outputs available on the PL612-05. Clock output
frequencies can be configured as follows:
CLK[0]
F VCO2 / P
CLK[1]
F VCO1 / (P*(1,2,4,8)) or F REF / (P*(1,2,4,8))
CLK[2]
F REF / (P*(1,2,4,8))
CLK[3]
F VCO2 / (P*(1,2,4,8)) or F REF / (P*(1,2,4,8))
CLK[4]
F REF / P
OEM (Master Output Enable)
One pin can be configured to be a single Master OE
(OEM) input pin that controls all the outputs of the
PL612-05. In addition the state of the disabled outputs
can be programmed to float (Hi Z) or to operate in the
‘Active low’ mode. The OEM Function operates on the
following logic:
OEM
OE Type
Osc PLL
Output
Pin
(Programmable)
0
1
0 (Default)
On
On
Hi Z
1
On
On
Active ‘0’
Normal Operation (Default)
Note: Typical enable time is 10ns.
Power-Down Control (PDB)
When activated, PDB ‘Disables all the PLLs, the
oscillator circuitry, counters, and all other active
circuitry. PDB activation disables all outputs and the
IC consumes <10µA of power. The PDB input
incorporates a 10MΩ pull up resistor for normal
operating condition.
The PDB feature can be programmed to allow the
output to float (Hi Z), or to operate in the ‘Active low’
mode. The logic for PDB is shown below:
PDB PDB Type
Osc PLL
Output
Pin
Program
Hi Z
0
Off
Off
(Default)
0
1
Off
Off
Active ‘0’
1
Normal Operation (Default)
Note: Typical enable time is 2ms.
Each output can be programmed with a 4mA, 8mA, or
16mA drive strength. The maximum output frequency
is 200MHz @ 3.3V, 166MHz @ 2.5V or 133MHz @
1.8V.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 9/4/07 Page 3
(Preliminary)
1.8V-3.3V PicoPLL, 2-PLL, 200MHz, 5 Output Clock IC
On-The-Fly Configuration Switching (CSEL)
The PL612-05 can be programmed to allow switching
between 2 different configurations, allowing for
changes in the output frequency and other feature
changes. Many applications (i.e. video/audio) can
use the same design footprint, but allow for
configuration switching, adhering to various
standards. CSEL is used to make the switching
selection. This pin incorporates a 60kΩ pull up
resistor for normal operating condition. The logic for
configuration switching of the programmed parts is
shown below:
CSEL
Programmed
Configuration
0
0
1
1(Default)
Note: Typical enable time is 100µs .
LAYOUT RECOMMENDATIONS
The following guidelines are to assist you with a performance optimized PCB design:
Signal Integrity and Termination
Considerations
Decoupling and Power Supply
Considerations
- Keep traces short!
- Place decoupling capacitors as close as possible to
the VDD pin(s) to limit noise from the power supply
- Trace = Inductor. With a capacitive load this
equals ringing!
- Long trace = Transmission Line. Without proper
termination this will cause reflections ( looks like
ringing ).
- Design long traces (> 1 inch) as “striplines” or
“microstrips” with defined impedance.
- Match trace at one side to avoid reflections
bouncing back and forth.
- Multiple VDD pins should be decoupled separately
for best performance.
- Addition of a ferrite bead in series with VDD can
help prevent noise from other board sources
- Value of decoupling capacitor is frequency
dependant. Typical values to use are 0.1F for
designs using frequencies < 50MHz and 0.01F for
designs using frequencies > 50MHz.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 9/4/07 Page 4
(Preliminary)
1.8V-3.3V PicoPLL, 2-PLL, 200MHz, 5 Output Clock IC
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 9/4/07 Page 5
(Preliminary)
1.8V-3.3V PicoPLL, 2-PLL, 200MHz, 5 Output Clock IC
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
V DD
-0.5
4.6
V
Input Voltage Range
VI
-0.5
V DD +0.5
V
Output Voltage Range
VO
-0.5
V DD +0.5
V
260
C
Supply Voltage Range
Soldering Temperature (Green package)
10
Data Retention @ 85C
Storage Temperature
TS
Ambient Operating Temperature*
Year
-65
150
C
-40
85
C
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only.
AC SPECIFICATIONS
PARAMETERS
Crystal Input Frequency (XIN)
CONDITIONS
Fundamental Crystal
MIN.
TYP.
10
@ V DD =3.3V
Input (FIN) Frequency
@ V DD =2.5V
MAX.
UNITS
50
MHz
200
1
166
@ V DD =1.8V
MHz
133
Input (FIN) Signal Amplitude
Internally AC coupled (High Frequency)
0.9
VDD
Vpp
Input (FIN) Signal Amplitude
Internally AC coupled (Low Frequency)
3.3V <50MHz, 2.5V <40MHz, 1.8V <15MHz
0.1
VDD
Vpp
Output Frequency
Settling Time
Output Enable Time
@ VDD =3.3V
200
@ VDD =2.5V
166
@ VDD =1.8V
133
MHz
At power-up (after VDD increases over 1.62V)
2
ms
OE Function; Ta=25º C, 15pF Load
10
ns
PDB Function; Ta=25º C, 15pF Load
2
ms
2
ppm
VDD Sensitivity
Frequency vs. VDD +/-10%
-2
Output Rise Time
15pF Load, 10/90% VDD, High Drive, 3.3V
1.2
1.7
ns
Output Fall Time
15pF Load, 90/10% VDD, High Drive, 3.3V
1.2
1.7
ns
Duty Cycle
PLL Enabled, @ VDD /2
50
55
%
Period Jitter, Pk-to-Pk*
(10,000 samples)
Input 16MHz fundamental mode crystal, all
outputs at 40MHz, 10pF Load, with capacitive
decoupling between V DD and GND.
100
120
ps
45
* Note: Jitter performance depends on the programming parameters.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 9/4/07 Page 6
(Preliminary)
1.8V-3.3V PicoPLL, 2-PLL, 200MHz, 5 Output Clock IC
DC SPECIFICATIONS
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Supply Current, Dynamic,
with Loaded CMOS Outputs
I DD
All outputs @ 20MHz,
10pF Load, V DD = 3.3V
13
19
mA
Supply Current, Dynamic,
with Loaded CMOS Outputs
I DD
All outputs @ 20MHz,
10pF Load, V DD = 2.5V
9
14
mA
Supply Current, Dynamic with
Loaded CMOS Outputs
I DD
All outputs @ 20MHz,
10pF Load, V DD = 1.8V
6.5
9
mA
Supply Current, Dynamic,
with Loaded Outputs
I DD
When PDB=0
<10
µA
Operating Voltage
V DD
3.3V Operation
2.97
3.3
3.63
2.5V Operation
2.25
2.5
2.75
1.8V Operation
1.62
1.8
1.98
0.4
V
Output Low Voltage
V OL
I OL = +4mA Std. Drive
V
Output High Voltage
V OH
I OH = -4mA Std. Drive
V DD – 0.4
V
Output Current, Low Drive
I OSD
V OL = 0.4V, V OH = 2.4V
4
mA
Output Current, Std Drive
I OSD
V OL = 0.4V, V OH = 2.4V
8
mA
Output Current, High Drive
I OHD
V OL = 0.4V, V OH = 2.4V
16
mA
CRYSTAL SPECIFICATIONS
PARAMETERS
Fundamental Crystal Resonator Frequency
Crystal Loading Rating
SYMBOL
MIN.
F XIN
10
C L (xtal)
TYP.
50
MHz
pF
100
Operating Drive Level
Shunt Capacitance
ESR Max
Shunt Capacitance
ESR Max
W
W
30
Crystal Shunt Capacitance
Small SMD Crystal
UNITS
15
Maximum Sustainable Drive Level
Metal Can Crystal
MAX.
C0
4
pF
C0
5.5
pF
ESR
50
Ω
C0
2.5
pF
ESR
80
Ω
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 9/4/07 Page 7
(Preliminary)
1.8V-3.3V PicoPLL, 2-PLL, 200MHz, 5 Output Clock IC
PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT)
MSOP-10L
Symbol
A
A1
A2
b
C
D
E
H
L
e
Dimension in MM
Min.
Max.
0.86
1.06
0.05
0.15
0.81
0.91
0.17
0.25
0.1
0.2
3.00 BSC
3.00 BSC
-5.08
0.43
0.63
0.50 BSC
E
H
D
A2 A
A1
C
L
b
e
SOP-8L
Symbol
A
A1
A2
b
C
D
E
H
L
e
Dimension in MM
Min.
Max.
1.35
1.75
0.10
0.25
1.25
1.50
0.33
0.53
0.19
0.27
4.80
5.00
3.80
4.00
5.80
6.20
0.40
0.89
1.27 BSC
E
H
D
A2 A
A1
C
e
b
L
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 9/4/07 Page 8
(Preliminary)
1.8V-3.3V PicoPLL, 2-PLL, 200MHz, 5 Output Clock IC
ORDERING INFORMATION (GREEN PACKAGE COMPLIANT)
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Part number, Package type and Operating temperature range
PL612-05-XXX X X X
PART NUMBER
3 DIGIT ID Code *
(will be assigned at
programming time)
NONE= TUBE
R=TAPE and REEL
PACKAGE TYPE
M=MSOP-10L
S=SOP-8L
TEMPERATURE
C=COMMERCIAL (0C to 70C)
I= INDUSTRIAL (-40C to +85C)
* PhaseLink will assign a unique 3-digit ID code for each approved programmed part number.
Part Number/Order Number
Package Option
PL612-05-XXXMC
K2XXX
10-Pin MSOP (Tube)
PL612-05-XXXMC-R
K2XXX
P612-05
XXX
P612-05
XXX
10-Pin MSOP (Tape and Reel)
PL612-05-XXXSC
PL612-05-XXXSC-R
†
Marking †
8-Pin SOP (Tube)
8-Pin SOP (Tape and Reel)
Note: ‘XXX’ designates marking identifier that, at times, could be independent of the part number.
Please consult your PhaseLink sales representative for marking information.
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information
furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the
express written approval of the President of PhaseLink Corporation.
Solder reflow profile available at www.phaselink.com/QA/solderingGreen.pdf
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 9/4/07 Page 9