CMX7861Q1 DataSheet

CMX7861
CML Microcircuits
FirmCODEC
COMMUNICATION SEMICONDUCTORS
D/7861_FI-1.x/1 December 2011
DATASHEET
®
Advance Information
7861FI-1.x Programmable Baseband Interface
Features
Dual Channel Codecs
o Can operate in modem or codec mode
o Two ADCs 16 bit
o Two DACs 14 bit
o Programmable input and output gain
o Differential/single ended inputs/outputs
Digital Channel Filters
o Two fully-programmable digital filters
o Filter design and configuration support
Auxiliary ADCs
o Four 10-bit DACs
o Autonomous RAMDAC sequencer
Auxiliary ADC
o One 10-bit ADC with four-input MUX
o ADC averaging, trip on high/low ‘watch’
modes
Auxiliary GPIO
o Four programmable input/outputs
Auxiliary Synthesised Clock Generators
o Two programmable clock outputs
C-BUS Host Serial Interface
o SPI-like with register addressing
o Read/write 128-byte FIFOs and data buffers
o Streamline transfers, low host service
latency
Master SSP Interface
o External slave device control
o Serial Flash connection
o Pass-through (Thru-port) mode expands
host C-BUS/SPI capacity
2011 CML Microsystems Plc
Features Cont.
Low-power 3.0V to 3.6V operation
Multiple power-saving options
Small 64-pin VQFN Package
Evaluation support
o PE0601-7861 Evaluation kit
o PE0002 Interface card
Applications
General-purpose DSP analogue/digital
interface
o Sensors
o Control systems
o Telemetry/SCADA/data modems
High Performance Narrowband Data Radio
o DMR
o APCO P25
o Software Defined Radio (SDR)
o 6.25kHz to 25kHz RF channel spacings
o worldwide compatibility e.g. ETSI, FCC,
ARIB, FCC Part 90 per spectral efficiency
requirements
High Performance I/Q Radio Interface
o Tx and Rx: ‘direct connect’ to zero IF
transceiver
o Simple external RC filters
o Digital filter configurable for multiple RF
channel spacings (Rx), Default is for DMR
o I/Q trims
CMX7861 FirmCODEC® Programmable Baseband Interface
CMX7861
Dual Channel Codec
Channel 1 ADC
Programmable Digital Filter 1
Channel 2 ADC
Channel 3 DAC
Programmable Digital Filter 2
Channel 4 DAC
Analogue
System/Signals
Auxiliary Operations
ADC
Sample Buffers
Clock Generation
ADC/DAC Sync
Power Management
FIFO
DACs
GPIO
‘Smart’
Function
Engine
Configuration
C-BUS
Registers
DSP
Microcontroller
This document contains:
Function Image™
Datasheet
Clocks Synths
User
Manual
Aux SSP
CMX7861 FirmCODEC®
1
Brief Description
1.1
General
®
The CMX7861 FirmCODEC is a general-purpose, dual-channel baseband interface device for use in
DSP-based systems. The device is a combination of codec, embedded signal processing and auxiliary
system support functions that, together, allow simple interfacing to analogue and digital systems.
Single-ended and differential interface options are provided and I/Q-based operation is supported. The
device can also be used in radio systems operating with channel bandwidths up to 50kHz, interfacing RF
devices to baseband DSP/microcontroller, performing the main data conversion and auxiliary operations
for monitoring and control.
Fully-programmable on-chip digital channel filters can be utilised for signal conditioning purposes.
Intelligent auxiliary ADC, DAC and GPIO sub-systems perform valuable functions and minimise host
interaction and host I/O resources. Two synthesised system clock generators develop clock signals for
off-chip use. The C-BUS/SPI master interface expands host C-BUS/SPI ports to control external devices.
The CMX7861 utilises CML’s proprietary FirmASIC component technology that enables on-chip subsystems to be configured by a Function Image™ data file, which is uploaded during device initialisation
and defines the device's function and feature set. The Function Image™ can be loaded automatically from
a host µC over the C-BUS serial interface or from an external memory device. The device's functions and
features can be enhanced by subsequent Function Image™ releases, facilitating in-the-field upgrades.
The CMX7861 operates from a 3.3V supply and includes selectable power saving modes. It is available in
a 64-VQFN package.
1.2
Codec and Modem Modes
Two general modes of operation are supported: codec mode and modem mode.
Codec mode is intended for applications where a general purpose codec is required. When in codec
mode the CMX7861 will provide digital-to-analogue and analogue-to-digital conversion, producing a flat
pass band over the sampled bandwidth. Simple programmable transmit and receive filter options are
provided but there are no signal interpolation facilities available, and the maximum sample rate is limited.
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CMX7861 FirmCODEC® Programmable Baseband Interface
CMX7861
Modem mode is suited to applications where the CMX7861 is used to transmit modulated data and
receive that data. Modem mode provides a transmit signal interpolator which will aid in the modulation
process by converting mapped symbols to a filtered, modulated output. Receive channel filters are also
provided, however filter design is more complex than codec mode as ADC and DAC roll off need to be
considered when designing filters. Modem mode is, in general, more efficient than codec mode and is
capable of providing a higher sample rate.
This datasheet is the first part of a two-part document.
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CMX7861 FirmCODEC® Programmable Baseband Interface
CMX7861
CONTENTS
Section
Page
1
Brief Description ...................................................................................................................... 2
1.1
General ......................................................................................................................... 2
1.2
Codec and Modem Modes ........................................................................................... 2
1.3
History........................................................................................................................... 6
2
Block Diagrams ....................................................................................................................... 7
3
Signal/Pin List .......................................................................................................................... 8
3.1
Power Supply Signal Definitions ................................................................................ 10
4
PCB Layout Guidelines and Power Supply Decoupling .................................................... 11
5
External Components ........................................................................................................... 12
5.1
Xtal Interface .............................................................................................................. 12
5.2
C-BUS Interface ......................................................................................................... 12
5.3
Signal Output .............................................................................................................. 13
5.3.1 Output Signal Routing .......................................................................................... 13
5.3.2 Output Reconstruction Filter – (I/Q mode) ........................................................... 14
5.3.3 Output Reconstruction Filter – Single-ended Outputs ......................................... 15
5.4
Signal Input ................................................................................................................. 15
5.4.1 Input Signal Routing ............................................................................................. 15
5.4.2 Input Anti-alias Filter (I/Q mode) .......................................................................... 17
5.4.3 Input Anti-alias Filter (Inputs 3 and 4) .................................................................. 17
6
General Description .............................................................................................................. 19
6.1
CMX7861 Features .................................................................................................... 19
6.2
Signal Interfaces ......................................................................................................... 20
7
Detailed Descriptions ............................................................................................................ 22
7.1
Xtal Frequency ........................................................................................................... 22
7.2
Host Interface ............................................................................................................. 22
7.2.1 C-BUS Operation ................................................................................................. 22
7.3
Function Image™ Loading ......................................................................................... 25
7.3.1 FI Loading from Host Controller ........................................................................... 25
7.3.2 FI Loading from Serial Memory............................................................................ 27
7.4
Device Control ............................................................................................................ 28
7.4.1 Normal Operation Overview ................................................................................. 28
7.4.2 Basic Tx and Rx Operation .................................................................................. 29
7.4.3 Device Configuration (Using the Programming Register) .................................... 32
7.4.4 Device Configuration (Using dedicated registers) ............................................... 32
7.4.5 Interrupt Operation ............................................................................................... 32
7.4.6 Signal Control....................................................................................................... 33
7.4.7 Tx Mode Processing ............................................................................................ 33
7.4.8 Rx Mode Processing ............................................................................................ 34
7.4.9 Duplex Mode ........................................................................................................ 35
7.4.10 Other Modes ........................................................................................................ 35
7.4.11 Data Transfer ....................................................................................................... 36
7.4.12 Sample Format..................................................................................................... 38
7.4.13 Data Buffering ...................................................................................................... 42
7.4.14 Managing Data Transfer ...................................................................................... 43
7.4.15 GPIO Pin Operation ............................................................................................. 43
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CMX7861 FirmCODEC® Programmable Baseband Interface
7.5
7.6
7.7
7.8
7.9
8
CMX7861
7.4.16 Auxiliary ADC Operation ...................................................................................... 43
7.4.17 Auxiliary DAC/RAMDAC Operation ..................................................................... 44
7.4.18 SPI Thru-Port ....................................................................................................... 44
Digital System Clock Generators ............................................................................... 45
7.5.1 Main Clock Operation .......................................................................................... 45
7.5.2 System Clock Operation ...................................................................................... 45
Signal Level Optimisation ........................................................................................... 46
7.6.1 Transmit Path Levels ........................................................................................... 46
7.6.2 Receive Path Levels ............................................................................................ 47
Application Information ............................................................................................... 47
7.7.1 ADC and DAC Filters ........................................................................................... 47
7.7.2 ADC and DAC Sample Timing Synchronisation .................................................. 47
Codec And Modem Mode Descriptions ...................................................................... 48
7.8.1 Codec Mode ......................................................................................................... 48
7.8.2 Modem Mode ....................................................................................................... 49
C-BUS Register Summary.......................................................................................... 50
Performance Specification ................................................................................................... 51
8.1
Electrical Performance ............................................................................................... 51
8.1.1 Absolute Maximum Ratings ................................................................................. 51
8.1.2 Operating Limits ................................................................................................... 51
8.1.3 Operating Characteristics .................................................................................... 52
8.1.4 Performance Characteristics................................................................................ 56
8.2
C-BUS Timing ............................................................................................................. 57
8.3
Packaging ................................................................................................................... 58
Table
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Page
Signal/Pin List .................................................................................................................... 8
Definition of Power Supply and Reference Voltages ....................................................... 10
BOOTEN Pin States ........................................................................................................ 25
FIFO Transfer Summary .................................................................................................. 37
Rx ADC1/ADC2 sample blocks........................................................................................ 38
Rx ADC1/ADC2, Phase/Magnitude sample blocks ......................................................... 40
Tx DAC1/DAC2 sample blocks ........................................................................................ 42
C-BUS Registers .............................................................................................................. 50
Figure
Page
Figure 1 Overall Block Diagram ...................................................................................................... 7
Figure 2 CMX7861 Power Supply and De-coupling ..................................................................... 11
Figure 3 Recommended External Components - Xtal Interface ................................................... 12
Figure 4 Recommended External Components - C-BUS Interface .............................................. 12
Figure 5 Analogue Output Routing ............................................................................................... 14
Figure 6 Recommended External Components – I/Q Output Reconstruction Filter ..................... 15
Figure 7 Recommended External Components - Single-ended Outputs Reconstruction Filter ... 15
Figure 8 Analogue Input Routing .................................................................................................. 16
Figure 9 Input Anti-alias FIlter: Inputs 1 and 2 .............................................................................. 17
Figure 10 Input Anti-alias FIlter: Inputs 3 and 4 ............................................................................ 17
Figure 11 CMX7861 Interface to Analogue Systems.................................................................... 20
Figure 12 CMX7861 I/Q Tx, I/Q Rx ............................................................................................... 20
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CMX7861 FirmCODEC® Programmable Baseband Interface
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
CMX7861
CMX7861 Two-point Tx, Classic FM Limiter-Discriminator Rx .................................... 21
CMX7861 Polar Tx, Amplitude and Phase Rx .............................................................. 21
Basic C-BUS Transactions ........................................................................................... 23
C-BUS Data Streaming Operation ................................................................................ 24
FI Loading from Host .................................................................................................... 26
FI Loading from Serial Memory .................................................................................... 27
Tx Mode Processing ..................................................................................................... 33
Rx Mode Processing ..................................................................................................... 34
Constellation Diagram – no frequency or phase error .................................................. 35
Constellation Diagram – phase error ............................................................................ 35
Constellation Diagram – frequency error ...................................................................... 35
Received Eye Diagram ................................................................................................. 36
Tx and Rx Data FIFOs .................................................................................................. 37
Main Clock Generation ................................................................................................. 45
Digital System Clock Generation Schemes .................................................................. 46
ADC/DAC Sample Timing Synchronisation .................................................................. 48
C-BUS Timing ............................................................................................................... 57
Mechanical Outline of 64-pin VQFN (Q1) ..................................................................... 58
Information in this datasheet should not be relied upon for final product design. It is always recommended
that you check for the latest product datasheet version from the CML website: [www.cmlmicro.com].
1.3
History
Version
1
Changes
Date
First issue
Dec 2011
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CMX7861 FirmCODEC® Programmable Baseband Interface
MUX
INPUT1N
INPUT1P
INPUT2N
INPUT2P
ADC 1
Programmable Filter/
Decimation
MUX
INPUT3N
INPUT3FB
INPUT4N
INPUT4FB
ADC 2
VBIAS
MUX
OUTPUT2P
OUTPUT2N
AUXDAC1
AUXDAC2
AUXDAC3
AUXDAC4
MUX
MUX
OP4VDD
OUTPUT4P
OUTPUT4N
OP4VSS
SYSCLK1
SYSCLK2
CDATA
RDATA
SCLK
CSN
IRQN
RESETN
Programmable Filter/
Interpolation
OUTPUT3
AUXADC1
AUXADC2
AUXADC3
AUXADC4
Configuration and Task
Processor
DAC 1
SSOUT0
SSOUT1
SSOUT2
SPICLK
MOSI
MISO
FIFO
ADC/DAC Sample
Synchroniser/Timer
OUTPUT1P
OUTPUT1N
Serial Port
Block Diagrams
C-BUS Registers
2
CMX7861
DAC 2
FIFO
Master Clock
XTAL/CLK
XTALN
GPIO Driver
GPIOA
GPIOB
GPIOC
GPIOD
Ramp
Aux DACs
Regulator
MUX
Aux ADC
Threshold
Compare
BOOTEN0
BOOTEN1
Bias Generator
and Reference
Aux System Clock Generators
DVDD
DVCORE
DVSS
AVDD
VBIAS
DACREF
ADCREF
AVSS
SUBSTRATE
Figure 1 Overall Block Diagram
Figure 1 Illustrates the overall functionality of the CMX7861 and the auxiliary functions.
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CMX7861 FirmCODEC® Programmable Baseband Interface
3
CMX7861
Signal/Pin List
Table 1 Signal/Pin List
Pin
Pin Name
Type
Description
1
GPIOB
BI
2
BOOTEN1
IP+PU
3
BOOTEN2
IP+PU
4
DVSS1
PWR
Negative supply rail (ground) for the digital on-chip circuits.
5
DVDD1
PWR
3.3V positive supply rail for the digital on-chip circuits. This pin
should be decoupled to DVSS by capacitors mounted close to the
device pin.
6
SSOUT2
OP
SPI: Slave Select Out 2
7
RESETN
IP
Logic input used to reset the device (active low).
8
GPIOC
BI
General Purpose I/O.
9
GPIOD
BI
General Purpose I/O.
10
DVSS2
PWR
11
OUTPUT3
OP
General Purpose I/O.
The combined state of BOOTEN1 and BOOTEN2, upon RESET,
determine the Function Image™ load interface.
Negative supply rail (ground) for the digital on-chip circuits.
Single ended analogue signal output.
12
AVDD1
PWR
Positive 3.3V supply rail for the analogue on-chip circuit. Levels
and thresholds within the device are proportional to this voltage.
This pin should be decoupled to AVSS by capacitors mounted
close to the device pin.
13
OP4VSS
PWR
Negative supply rail (ground) for the on-chip speaker driver circuit.
14
OUTPUT4P
OP
15
OUTPUT4N
OP
Low impedance differential output speaker driver. Together these
are referred to as Output 4.
Positive supply rail for on-chip speaker driver circuit. Levels and
thresholds within the device are proportional to this voltage. This
pin should be decoupled to OP4VSS by capacitors mounted close
to the device pin.
16
OP4VDD
PWR
17
OUTPUT1P
OP
18
OUTPUT1N
OP
19
OUTPUT2P
OP
20
OUTPUT2N
OP
21
AVSS2
PWR
Negative supply rail (ground) for the analogue on-chip circuits
22
DACREF
PWR
DAC reference voltage, connect to AVss.
23
INPUT3N
IP
24
INPUT3FB
OP
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Differential outputs; ‘P’ is positive, ‘N’ is negative. Together these
are referred to as Output 1. Can also be used as the ‘I’ output in
an I/Q based system.
Differential outputs; ‘P’ is positive, ‘N’ is negative. Together these
are referred to as Output 2. Can also be used as the ‘Q’ output in
an I/Q based system.
Negative input ‘N’ and feedback ‘FB’ connections to a single
ended amplifier. Together these are referred to as Input 3. Gain
and filtering circuitry can be constructed around these pins.
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CMX7861 FirmCODEC® Programmable Baseband Interface
Pin
Pin Name
Type
25
INPUT4N
IP
26
INPUT4FB
OP
27
VBIAS
OP
28
INPUT1P
IP
29
INPUT1N
IP
30
ADCREF
PWR
31
INPUT2P
IP
32
INPUT2N
IP
33
AUXADC1
IP
34
AUXADC2
IP
35
AUXADC3
IP
36
AUXADC4
IP
CMX7861
Description
Negative input ‘N’ and feedback ‘FB’ connections to a single
ended amplifier. Together these are referred to as Input 4. Gain
and filtering circuitry can be constructed around these pins.
Internally generated bias voltage of approximately AV DD/2. If VBIAS
is powersaved this pin will be connected via a high impedance to
AVDD. This pin must be decoupled to AVSS by a capacitor mounted
close to the device pin.
Differential inputs; ‘P’ is positive, ‘N’ is negative. Together these
are referred to as Input 1. Can also be used as the ‘I’ Input in an
I/Q based system.
ADC reference voltage, connect to AVSS.
Differential inputs; ‘P’ is positive, ‘N’ is negative. Together these
are referred to as Input 2. Can also be used as the ‘Q’ Input in an
I/Q based system.
Auxiliary ADC inputs multiplexed to a single ADC with Threshold
and Compare operations.
37
AVDD3
PWR
Positive 3.3V supply rail for the analogue on-chip circuit. Levels
and thresholds within the device are proportional to this voltage.
This pin should be decoupled to AVSS by capacitors mounted
close to the device pin.
38
AVSS3
PWR
Negative supply rail (ground) for the analogue on-chip circuits.
39
AUXDAC1
OP
40
AUXDAC2
OP
41
AUXDAC3
OP
42
AUXDAC4
OP
43
DVSS3
PWR
Negative supply rail (ground) for the digital on-chip circuits
44
DVCORE1
PWR
Digital core supply, nominally 1.8V. This pin should be decoupled
to DVSS by capacitors mounted close to the device pins and
connected with a power supply track to DVCORE2.
45
DVDD2
PWR
3.3V positive supply rail for the digital on-chip circuits. This pin
should be decoupled to DVSS by capacitors mounted close to the
device pin.
46
NC
NC
47
DVSS4
PWR
Negative supply rail (ground) for the digital on-chip circuits.
48
DVSS5
PWR
Negative supply rail (ground) for the digital on-chip circuits.
49
XTALN
OP
Output of the on-chip Xtal oscillator inverter.
50
XTAL/CLK
IP
Input to the oscillator inverter from the Xtal circuit or external clock
source.
51
SYSCLK1
OP
Synthesised digital clock output 1.
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Auxiliary DAC outputs with DAC1 output having an optional
ramping RAMDAC operation.
Do not connect.
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CMX7861 FirmCODEC® Programmable Baseband Interface
CMX7861
Pin
Pin Name
Type
Description
52
SYSCLK2
OP
Synthesised digital clock output 2.
53
SCLK
IP
C-BUS serial clock input from the µC.
54
RDATA
TS OP
55
CDATA
IP
C-BUS serial data input from the µC.
56
CSN
IP
C-BUS chip select input from the µC.
Three-state C-BUS serial data output to the µC. This output is
high impedance when not sending data to the µC.
57
IRQN
OP
‘wire-Orable’ output for connection to the Interrupt Request input
of the µC. This output is pulled down to DVSS when active and is
high impedance when inactive. An external pull-up resistor is
required.
58
DVCORE2
PWR
Digital core supply, nominally 1.8V. This pin should be decoupled
to DVSS by capacitors mounted close to the device pins, and
connected, with a power supply track, to DVCORE1.
59
MOSI
OP
SPI: Master Out Slave In.
60
SSOUT1
OP
SPI: Slave Select Out 1.
61
MISO
IP
SPI: Master In Slave Out.
62
SSOUT0
OP
SPI: Slave Select Out 0.
63
SPICLK
OP
SPI: Serial Clock.
64
GPIOA
BI
General Purpose I/O.
EXPOSED
METAL
PAD
SUBSTRATE
~
On this device, the central metal pad may be electrically unconnected or,
alternatively, may be connected to analogue ground (AVss).
No other electrical connection is permitted.
Notes:
3.1
IP
OP
BI
TS OP
PWR
NC
Input (+ PU/PD = internal pull-up / pull-down resistor of approximately 75kΩ)
Output
Bidirectional
Three-state Output
Power Connection
No Connection - should NOT be connected to any signal
=
=
=
=
=
=
Power Supply Signal Definitions
Table 2 Definition of Power Supply and Reference Voltages
Signal Name
Pin name
Usage
AVDD
AVDD1, AVDD2, AVDD3
Power supply for analogue circuits
DVDD
DVDD1, DVDD2
Power supply for digital circuits, nominally 3.3V
DVcore
DVCORE1, DVCORE2
Power for digital core voltage of approximately 1.8V
VBIAS
VBIAS
CMX7861 generated bias voltage of approximately
AVDD/2
DVSS
AVSS
DVSS1, DVSS2, DVSS3,
DVSS4, DVSS5
AVSS1, AVSS2, AVSS3,
SUBSTRATE (Optional)
DACREF, ADCREF
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Ground for digital circuits
Ground for analogue circuits
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CMX7861 FirmCODEC® Programmable Baseband Interface
4
CMX7861
PCB Layout Guidelines and Power Supply Decoupling
+ C26
Digital Ground Plane
C27
DVSS
GPIOB
BOOTEN1
BOOTEN2
DVSS1
DVDD1
C21
SSOUT2
RESETN
GPIOC
GPIOD
DVSS
DVSS2
OUTPUT3
AVDD1
OP4VSS
C25
OUTPUT4P
OUTPUT4N
+
OP4VDD
AVSS
AVDD
XTALN
XTAL/CLK
SYSCLK1
SYSCLK2
SCLK
RDATA
CDATA
CSN
IRQN
DVCORE2
MOSI
SSOUT1
MISO
3
46
4
45
5
44
CMX7861Q1
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
DVSS5
DVSS4
DVDD
NC
DVDD2
DVSS
DVCORE1
C28
C22
DVSS3
AUXDAC4
DVSS
AUXDAC3
AUXDAC2
AUXDAC1
AVSS3
AVDD3
AUXADC4
+ C23
C24
AUXADC3
AUXADC2
AVSS
AUXADC1
INPUT2N
INPUT2P
ADCREF
INPUT1N
INPUT1P
VBIAS
INPUT4FB
INPUT4N
INPUT3FB
INPUT3N
OUTPUT1P
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
DACREF
C30
47
AVSS2
C29
2
OUTPUT2N
AVDD
48
OUTPUT2P
+ C20
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
OUTPUT1N
DVDD
SSOUT0
Active low reset from
supervisory IC or RC circuit
SPICLK
GPIOA
C-BUS
C31
Analogue Ground Plane
C20
C21
C22
C23
C24
C25
AVSS
10µF
10nF
10nF
10µF
10nF
10nF
C26
C27
C28
C29
C30
C31
22µF
10nF
10nF
10µF
10nF
100nF
Figure 2 CMX7861 Power Supply and De-coupling
Notes:
To achieve good noise performance, AVDD and VBIAS decoupling and protection of the receive path from
extraneous in-band signals is very important. It is recommended that the printed circuit board is laid out
with a ground plane in the CMX7861 analogue area to provide a low impedance connection between the
AVSS pins and the AVDD and VBIAS decoupling capacitors.
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CMX7861 FirmCODEC® Programmable Baseband Interface
5
CMX7861
External Components
5.1
Xtal Interface
C1
XTAL/CLK
50
X1
XTALN
49
C2
DVSS
X1
C1
C2
For frequency range see
8.1.2 Operating Limits
22pF typical
22pF typical
Figure 3 Recommended External Components - Xtal Interface
Notes:
The clock circuit can operate with either a Xtal or external clock generator. If using an external clock
generator it should be connected to the XTAL/CLK pin and the Xtal and other components are not
required. For external clock generator frequency range see 8.1.2 Operating Limits. When using an
external clock generator the Xtal oscillator circuit may be disabled to save power, see 9.2.3 Program
Block 1 – Clock Control for details. Also refer to section 7.1 Xtal Frequency.
The tracks between the Xtal and the device pins should be as short as possible to achieve maximum
stability and best start up performance. It is also important to achieve a low impedance connection
between the Xtal capacitors and the ground plane.
The DVSS to the Xtal oscillator capacitors C1 and C2 should be of low impedance and preferably be part
of the DVSS ground plane to ensure reliable start up. For correct values of capacitors C1 and C2 refer to
the documentation of the Xtal used.
5.2
C-BUS Interface
DVDD
R2
57
56
55
54
53
R2
IRQN
CSN
CDATA
RDATA
SCLK
10k
- 100k
Figure 4 Recommended External Components - C-BUS Interface
Note:
If the IRQN line is connected to other compatible pull-down devices only one pull-up resistor is required
on the IRQN node.
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CMX7861 FirmCODEC® Programmable Baseband Interface
5.3
5.3.1
CMX7861
Signal Output
Output Signal Routing
The CMX7861 has four possible analogue outputs:
Differential output 1 - OUTPUT1P and OUTPUT1N (or I output for an I/Q-based system)
Differential output 2 - OUTPUT2P and OUTPUT2N (or Q output for an I/Q-based system)
Single-ended output 3 – OUTPUT3 that can drive headset/earpieces
Differential output 4 – OUTPUT4P and OUTPUT4N – a low-impedance speaker driver
The CMX7861’s two DACs (DAC 1 and DAC 2) can output analogue waveforms on any or all of these
four outputs. CMX7861 allows us to connect the two DACs to any of the four analogue outputs.
Due to the highly-flexible nature of the CMX7861 and the multitude of input and output configurations, it is
important to clearly understand the differences between Pin/Signal names, and the internal signal streams
controlled by most of the registers. To help clarify this situation, the following convention has been used
throughout the text and on diagrams within this document:
Outputs from the device to external systems will be referred to as OUTPUT1, 2, 3, or 4. Where
appropriate, OUTPUT 1 and 2 may also be referred to as I and Q outputs respectively (if the
description is specifically for an I/Q-based system).
Internal signal streams routed to the four outputs and processed by the two DACs will be referred to
as DAC1 and/or DAC2 samples.
Figure 5 Analogue Output Routing, shows the analogue output signal routing and control.
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CMX7861 FirmCODEC® Programmable Baseband Interface
CMX7861
Output1_Coarse_Gain [6:0]
Output_Config [0]
Output1_Coarse
_Gain [15]
x2
DAC
1
Output_Config
[1]
DAC
1
Filter
OUTPUT1N
OUTPUT1P
OUTPUT 1
(or I output for
an I/Q-based
system)
Output2_Coarse_Gain [6:0]
Output_Config [2]
Signal_Control
[7:6]
Output2_Coarse
_Gain [15]
x2
DAC
2
Output_Config
[2]
DAC
2
Filter
OUTPUT2P
OUTPUT2N
OUTPUT 2
(or Q output for
an I/Q-based
system)
Signal_Control
[5:4]
Output_Config [5]
OUTPUT4P
Output_Config [7]
OUTPUT4N
Output3_Coarse
_Gain [15]
Output_Config
[8]
Output 3/4
Pwr
8Ohm
driver
x2
OUTPUT3
32Ohm
driver
Output_Config [4]
Output3_Coarse_Gain [5:0]
Figure 5 Analogue Output Routing
The registers that control analogue output signal routing are described in the following sections:
9.1.10 Signal Control - $61 write
9.1.21 Output 1 - 4 Configuration - $B3 write
9.1.22 Output 1 and 2 Coarse Gain - $B4, $B5 write
Include Output3 coarse gain register here when it is defined
5.3.2
Output Reconstruction Filter – (I/Q mode)
When output 1 (or I) and output 2 (or Q) are used as I/Q outputs, internal reconstruction filtering is
provided with four selectable bandwidths (-3dB point shown in section 9.1.21). The bandwidth of the
internal reconstruction filter may be selected using the Output 1 - 4 Configuration - $B3 write or Signal
Control - $61 write registers.
To complete the output reconstruction filter one of the following external RC networks should be used for
each of the differential outputs. The external RC network should have a bandwidth that matches the
bandwidth of the selected internal reconstruction filter.
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17
18
19
20
CMX7861
OUTPUT1P
R3
OUTPUT1N
R4
OUTPUT2P
R5
OUTPUT2N
R6
C9
C10
Bandwidth (kHz)
R3-R6 (kOhms)
C9-C10 (pF)
100
50
25
12.5
22
20
22
22
33
75
150
270
Figure 6 Recommended External Components – I/Q Output Reconstruction Filter
When transmitting an I/Q signal, each I/Q output will produce a signal with bandwidth half the channel
bandwidth. A reconstruction filter with a –3dB point close to half the channel bandwidth will therefore have
significant roll off within the channel bandwidth – which is undesirable. An appropriate choice for channels
occupying up to a 12.5kHz bandwidth (channel bandwidth/2 = 6.25kHz) would be a reconstruction filter of
12.5kHz bandwidth.
5.3.3
Output Reconstruction Filter – Single-ended Outputs
To complete the output reconstruction filter one of the following external RC networks should be used for
each of the single-ended outputs. The external RC network should have a bandwidth that matches the
bandwidth of the selected internal reconstruction.
14 OUTPUT 4P
15 OUTPUT 4N
11 OUTPUT 3
AVss
Figure 7 Recommended External Components - Single-ended Outputs Reconstruction Filter
5.4
5.4.1
Signal Input
Input Signal Routing
The CMX7861 has four possible analogue input paths:
Differential input 1 - INPUT1P and INPUT1N (or I input for an I/Q-based system)
Differential input 2 – INPUT2P and INPUT2N (or Q input for an I/Q-based system)
Single-ended input 3 – INPUT3N and INPUT3FB
Single-ended input 4 – INPUT4N and INPUT4FB
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CMX7861 FirmCODEC® Programmable Baseband Interface
CMX7861
The CMX7861’s two ADCs (ADC1 and ADC2) can sample up to two of these inputs. The CMX7861
allows us to connect these four inputs to the two ADCs.
Due to the highly-flexible nature of the CMX7861 and the multitude of input and output configurations, it is
important to clearly understand the differences between Pin/Signal names, and the internal signal streams
controlled by most of the registers. To help clarify this situation, the following convention has been used
throughout the text and on diagrams within this document:
Inputs to the device from external systems will be referred to as INPUT1, 2, 3, or 4. Where
appropriate, INPUT 1 and 2 may also be referred to as I and Q inputs respectively (if the
description is specifically for an I/Q-based system).
Internal signal streams routed from the four inputs and processed by the two ADCs will be referred to
as ADC1 and/or ADC2 samples.
Figure 8 Analogue Input Routing, shows the analogue input signal routing and control.
Input_Config [0]
Input1_Coarse_Gain [2:0]
Input_Config [1]
INPUT 1P
INPUT 1N
(or I)
Signal_Control
[3:2]
Input_Config
[11]
Anti-alias
Filter
for ADC1
ADC
1
Signal_Control
[1:0]
Input_Config
[10]
Anti-alias
Filter
for ADC2
ADC
2
IP1
INPUT 3
Input_Config [9]
+
IP3
Bias
Input_Config [3]
Input_Config [2]
Input1_Coarse_Gain [10:8]
Input_Config [5]
Input_Config [4]
Input2_Coarse_Gain [2:0]
INPUT 2P
INPUT 2N
(or Q)
INPUT 4
IP2
Input_Config [8]
+
IP4
Bias
Input_Config [7]
Input_Config [6]
Input2_Coarse_Gain [10:8]
Figure 8 Analogue Input Routing
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CMX7861
The registers that control analogue input signal routing are described in the following sections:
9.1.10 Signal Control - $61 write
9.1.19 Input 1 - 4 Configuration - $B0 write
9.1.20 Input 1-4 Coarse Gain - $B1, $B2 write
5.4.2
Input Anti-alias Filter (I/Q mode)
When Input 1 (I) and Input 2 (Q) are used as the inputs to ADCs 1 and 2, the device has a programmable
anti-alias filter in the input path, which is controlled using the Input 1 - 4 Configuration - $B0 write or Signal
Control - $61 write registers. This should be sufficient for most applications, however if additional filtering
is required it can be done at the input to the device.
Figure 9 Input Anti-alias FIlter: Inputs 1 and 2
The input impedance of pins 28 to 32 varies with the input gain setting, approx 14kOhm at +22.4dB rising
to 100kOhm at 0dB. The output impedance of the circuit driving the inputs shown above should be no
more than approximately 1kOhm, for the above RC network R7-10 <= approx. 1kOhm. Recommended
values for R7-10 and C11-14 will depend on the filtering required.
5.4.3
Input Anti-alias Filter (Inputs 3 and 4)
C16
R12
C15
INPUT 3FB
24
R11
INPUT 3N
23
+
VBIAS
C18
R14
C17
R13
INPUT 4FB
26
INPUT 4N
25
+
VBIAS
C15
C16
R11
R12
See note
100pF
See note
100k
C17
C18
R13
R14
See note
100pF
See note
100k
Figure 10 Input Anti-alias FIlter: Inputs 3 and 4
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CMX7861 FirmCODEC® Programmable Baseband Interface
CMX7861
Notes:
Assuming R12 and R14 at 100kOhm, R11 and R13 should be selected to provide the required dc gain
(assuming C15 and C17 are not present) as follows:
GAINAUDIO1 = 100k
/ R11
GAINAUDIO2 = 100k
/ R13
The gain should be such that the resultant output at the pins is within the input signal range.
C15 and C17 should be selected to maintain the lower frequency roll-off of the AUDIO inputs as
follows:
C15
0.1µF
GAINAUDIO1
C17
0.1µF
GAINAUDIO2
The High Frequency cut off = ~ 16KHz
1
2 .R14C18
The Low Frequency cut off = ~ 16 Hz
1
2 .R13C17
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CMX7861 FirmCODEC® Programmable Baseband Interface
6
CMX7861
General Description
6.1
CMX7861 Features
®
The CMX7861 FirmCODEC is a general-purpose, dual-channel baseband interface device for use in
DSP-based systems and supports duplex operation of two ADC and two DAC channels. Flexibility is the
key to the device with target applications being sensors, control and monitoring systems and providing an
interface to RF systems.
The device is highly configurable with selectable single-ended and differential inputs and outputs plus the
ability to operate in I/Q mode.
A flexible power control facility allows the device to be placed in its optimum powersave mode when not
actively processing signals.
On-chip auxiliary functions include: an Xtal clock generator with phase locked loop and buffered output to
provide a system clock output (if required) for other devices, a multiplexed input ADC, DAC outputs and
GPIO.
Fully-programmable on-chip digital channel filters can be used for signal conditioning purposes prior to
passing data to the host DSP. The C-BUS/SPI master interface expands host C-BUS/SPI ports to control
external devices.
Block diagrams of the device are shown in section 2.
Note: In the list below, the greyed-out text indicates future planned updates
Tx Functions:
Single-ended and differential analogue outputs
Interpolation stage with filtering – providing pulse shape filtering for mapped symbols
RAMDAC capability for PA ramping control
Tx trigger feature allowing precise control of burst start time
Tx burst sequence for automatic RAMDAC ramp and Tx hardware switching
Rx Functions:
Single-ended and differential analogue inputs
Rx channel filtering
Received signal strength indication (RSSI)
I/Q and Phase/Magnitude output formats for FM systems
AGC using SPI Thru-Port
Auxiliary Functions:
Two programmable system clock outputs
Auxiliary ADC with four selectable input paths
SPI Thru-Port for interfacing to synthesisers, a Cartesian loop IC (CMX998) and/or other seriallycontrollable devices
Four auxiliary DACs, one with built-in programmable RAMDAC
Interface:
Optimised C-BUS (4-wire, high-speed synchronous serial command/data bus) interface to host for
control and data transfer, including streaming C-BUS for efficient data transfer
Open drain IRQ to host
Four GPIO pins
Tx trigger input (provided by GPIOA)
Serial memory or C-BUS (host) boot mode
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CMX7861 FirmCODEC® Programmable Baseband Interface
6.2
CMX7861
Signal Interfaces
The CMX7861 FirmCODEC IC can be used to provide any interface the user requires depending on the
data supplied to the device. Typical interfaces are baseband, I/Q and phase/magnitude.
CMX7861
Output 1
Output 2
C-BUS
Sensors
Control
Monitoring
Measuring
Input 2
Output
Processing
Analogue
Systems
Input
Processing
Input 1
DACs
GPIO
Auxiliary
Systems
ADC
Clocks
Figure 11 CMX7861 Interface to Analogue Systems
CMX7861
LO
‘Q’ Input
RF Receiver
Transmit
Processing
‘I’ Output
90
‘Q’ Output
RF Transmitter
C-BUS
Receive
Processing
‘I’ Input
T/R
GPIO
Auxiliary
Systems
ADC
DACs
Clocks
Figure 12 CMX7861 I/Q Tx, I/Q Rx
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CMX7861 FirmCODEC® Programmable Baseband Interface
CMX7861
CMX7861
Receive
Processing
Input 1
T/R
FM
Demodulator
Input 2
RF Receiver
Transmit
Processing
Output 1
PLL
Output 2
C-BUS
RSSI
RF Transmitter
GPIO
Auxiliary
Systems
ADC
DACs
Clocks
Figure 13 CMX7861 Two-point Tx, Classic FM Limiter-Discriminator Rx
CMX7861
Receive
Processing
Input 1
T/R
Limited
Signal
Input 2
RSSI
Amplitude
Modulation
Transmit
Processing
Output 1
Phase
Modulator
Output 2
RF Transmitter
C-BUS
RF Receiver
DACs
GPIO
Auxiliary
Systems
ADC
Clocks
Figure 14 CMX7861 Polar Tx, Amplitude and Phase Rx
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CMX7861 FirmCODEC® Programmable Baseband Interface
7
CMX7861
Detailed Descriptions
7.1
Xtal Frequency
The CMX7861 is designed to work with a Xtal, or an external frequency oscillator within the ranges
specified in section 8.1.3 Operating Characteristics. Program Block 1 (see User Manual) must be loaded
with the correct values to ensure that the device will work to specification with the user-selected clock
frequency. A table of configuration values can be found in Table 17 Xtal/Clock Frequency Settings for
Program Block 1, supporting sample rates up to 144k samples per second when the Xtal frequency is
9.6MHz or the external oscillator frequency is 9.6 or 19.2 MHz. Rates other than those tabulated (within
this range) are possible, see section 9.2.3 Program Block 1 – Clock Control. Further information can be
provided on request. The accuracy of the sample rates provided is affected by the accuracy of the Xtal or
oscillator used.
7.2
Host Interface
A serial data interface (C-BUS) is used for command, status and data transfers between the CMX7861
and the host µC; this interface is compatible with Microwire™, SPI™ and other similar interfaces. Interrupt
signals notify the host µC when a change in status has occurred; the µC should read the IRQ Status
register across the C-BUS and respond accordingly. Interrupts only occur if the appropriate mask bit has
been set, see 7.4.5 Interrupt Operation.
7.2.1
C-BUS Operation
This block provides for the transfer of data and control or status information between the CMX7861
internal registers and the host µC over the C-BUS serial bus. Single register transactions consist of a
single register address byte sent from the µC, which may be followed by a data word sent from the µC to
be written into one of the CMX7861’s write-only registers, or a data word read out from one of the
CMX7861’s read-only registers. Streaming C-BUS transactions consist of a single register address byte
followed by many data bytes being written to or read from the CMX7861. All C-BUS data words are a
multiple of 8 bits wide, the width depending on the source or destination register. Note that certain C-BUS
transactions require only an address byte to be sent from the µC, no data transfer being required. The
operation of the C-BUS is illustrated in Figure .
Data sent from the µC on the CDATA (command data) line is clocked into the CMX7861 on the rising
edge of the SCLK input. Data sent from the CMX7861 to the µC on the RDATA (reply data) line is valid
when SCLK is high. The CSN line must be held low during a data transfer and kept high between
transfers. The C-BUS interface is compatible with most common µC serial interfaces and may also be
easily implemented with general purpose µC I/O pins controlled by a simple software routine. Section 8.2
C-BUS Timing gives detailed C-BUS timing requirements.
Note that, due to internal timing constraints, there may be a delay of up to 60µs between the end of a
C-BUS write operation and the device reading the data from its internal register.
C-BUS single byte command (no data)
CSN
Note:
The SCLK line may be high or
low at the start and end of each
transaction.
SCLK
CDATA
7
6
5
MSB
RDATA
4 3 2
Address
1
0
LSB
Hi-Z
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CMX7861 FirmCODEC® Programmable Baseband Interface
CMX7861
C-BUS n-bit register write
CSN
SCLK
CDATA
7
6
5
MSB
RDATA
4 3 2
Address
1
4 3 2
Address
1
0
LSB
n-1 n-2 n-3
2
Write data
1
n-1 n-2 n-3
2
Read data
1
MSB
0
LSB
Hi-Z
C-BUS n-bit register read
CSN
SCLK
CDATA
7
6
5
MSB
RDATA
0
LSB
Hi-Z
MSB
0
LSB
Data value unimportant
Repeated cycles
Either logic level valid (and may change)
Either logic level valid (but must not change from low to high)
Figure 15 Basic C-BUS Transactions
To increase the data bandwidth between the µC and the CMX7861, certain of the C-BUS read and write
registers are capable of data-streaming operation. This allows a single address byte to be followed by the
transfer of multiple read or write data words, all within the same C-BUS transaction. This can significantly
increase the transfer rate of large data blocks, as shown in Figure .
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CMX7861 FirmCODEC® Programmable Baseband Interface
CMX7861
Example of C-BUS data-streaming (8-bit write register)
CSN
SCLK
CDATA
RDATA
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Address
First byte
Second byte
…
7 6 5 4 3 2 1 0
Last byte
…
7 6 5 4 3 2 1 0
Last byte
Hi-Z
Example of C-BUS data-streaming (8-bit read register)
CSN
SCLK
CDATA
RDATA
7 6 5 4 3 2 1 0
Address
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
First byte
Second byte
Hi-Z
Data value unimportant
Repeated cycles
Either logic level valid (and may change)
Either logic level valid (but must not change from low to high)
Figure 16 C-BUS Data Streaming Operation
Notes:
1. For Command byte transfers only the first 8 bits are transferred ($01 = Reset)
2. For single byte data transfers only the first 8 bits of the data are transferred
3. The CDATA and RDATA lines are never active at the same time. The address byte determines
the data direction for each C-BUS transfer.
4. The SCLK can be high or low at the start and end of each C-BUS transaction
5. The gaps shown between each byte on the CDATA and RDATA lines in the above diagram are
optional, the host may insert gaps or concatenate the data as required.
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CMX7861 FirmCODEC® Programmable Baseband Interface
7.3
CMX7861
Function Image™ Loading
The Function Image™ (FI), which defines the operational capabilities of the device, may be obtained from
the CML Technical Portal, following registration and authorisation. This is in the form of a 'C' header file
which can be included into the host controller software or programmed into an external serial memory.
TM
The Function Image size will not exceed 128kbytes, although a typical FI will be considerably less than
this. Note that the BOOTEN1/2 pins are only read at power-on, when the RESETN pin goes high, or
following a C-BUS General Reset, and must remain stable throughout the FI loading process. Once the FI
load has completed, the BOOTEN1/2 pins are ignored by the CMX7861 until the next power-up or Reset.
The BOOTEN1 and BOOTEN2 pins are both fitted with internal low-current pull-up devices.
For serial memory load operation, BOOTEN2 should be pulled low by connecting it to DV ss either directly
or via a 47k resistor (see Table 3).
Whilst booting, the boot loader will return the checksum of each block loaded in the C-BUS Rx Data FIFO.
The checksums can be verified against the values provided with the FI to ensure that the FI has loaded
correctly.
Once the FI has been loaded, the CMX7861 performs these actions:
(1) The product identification code ($7861) is reported in the C-BUS Rx Data FIFO
(2) The FI version code is reported in the C-BUS Rx Data FIFO.
Table 3 BOOTEN Pin States
C-BUS host load
reserved
Serial memory load
reserved
7.3.1
BOOTEN2
1
1
0
0
BOOTEN1
1
0
1
0
FI Loading from Host Controller
The FI can be included into the host controller software build and downloaded into the CMX7861 at
power-up over the C-BUS interface, using the Tx FIFO. For Function Image™ load, the FIFO accepts raw
16-bit Function Image™ data (using the Tx FIFO Word) - $49 write register, there is no need for
distinction between control and data fields. The BOOTEN1/2 pins must be set to the C-BUS load
configuration, the CMX7861 powered or reset, and then data can then be sent directly over the C-BUS to
the CMX7861.
If the host detects a brownout, the BOOTEN1 and BOOTEN2 pins should be set to re-load the FI. A
General Reset should then be issued or the RESETN pin used to reset the CMX7861 and the appropriate
FI load procedure followed.
Streaming C-BUS may be used to load the Tx FIFO Word - $49 write register with the Function Image™,
and the Tx FIFO Level - $4B read register used to ensure that the FIFO is not allowed to overflow during
the load process.
The download time is limited by the clock frequency of the C-BUS; with a 5MHz SCLK it should take less
than 250ms to complete even when loading the largest possible Function Image™.
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CMX7861 FirmCODEC® Programmable Baseband Interface
CMX7861
BOOTEN2 = 1
BOOTEN1 = 1
Power-up or
write General Reset to CMX7861
Read the Rx FIFO Level - $4F and wait until 3
device check words appear in Rx FIFO Word $4D. Read and discard them
Block number N =1
BOOTEN1 and BOOTEN2 may be
changed once it is clear that the CMX7861
has comitted to C-BUS boot – i.e. when a
word has been read from the C-BUS
command FIFO
Write Block 1 Length (DBN_len) to
Tx FIFO Word - $49
Write Start Block N Address (DBN_ptr) to
Tx FIFO Word - $49
Check Tx FIFO Level - $4B
Write up to “128-FIFO fill level” words to
Tx FIFO Word - $49
End of Block?
No
Yes
Read and verify 32-bit checksum words from
RxFIFO Word - $4D
N = N+1
Is the next block the Activation Block?
No – load next
block
Yes
Write Start Block N Length (ACTIVATE_len) to
Tx FIFO Word - $49
Write Start Block N Address (ACTIVATE_ptr) to
Tx FIFO Word - $49
Poll Status -$7E until Reg Done b14 = 1
(PRG Flag is unmasked in Reg Done Select register
- $69 by default and indicates when the FI is loaded)
VDD
Read the Product ID Code and the FI
version code from the
Rx FIFO Word -$4D
BOOTEN1
BOOTEN2
CMX7861 is now ready for use
Figure 15 FI Loading from Host
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CMX7861 FirmCODEC® Programmable Baseband Interface
7.3.2
CMX7861
FI Loading from Serial Memory
The FI must be converted into a format for the serial memory programmer (normally Intel Hex) and loaded
into the serial memory either by the host or an external programmer. The serial memory should contain
the same data stream as written to the Command FIFO shown in Figure 15. The most significant byte of
each 16-bit word should be stored first in serial memory.
The serial memory should be interfaced to the CMX7861 SPI Thru-Port using SSOUT0 as the chip select.
The CMX7861 needs to have the BOOTEN pins set to Serial Memory Load, and then on power-on
following the RESETN pin becoming high, or following a C-BUS General Reset, the CMX7861 will
automatically load the data from the serial memory without intervention from the host controller.
BOOTEN2 = 0
BOOTEN1 = 1
Power-up or write General Reset to
CMX7861
Poll Status -$7E until Reg Done b14 = 1
(PRG Flag is unmasked in Reg Done Select register $69 by default and indicates when the FI is loaded)
Read and discard 3 device check words from
the RxFIFO Word - $4D.
BOOTEN1 and BOOTEN2
may be changed from this
point on, if required
VDD
Read and verify the 32-bit checksum word of
each block loaded – found in the RxFIFO
Word - $4D
Read the Product ID code and the FI version
code from the RxFIFO Word - $4D
CMX7861 is now ready for use
BOOTEN1
BOOTEN2
Jumper for
programming
serial memory
(if required)
Figure 16 FI Loading from Serial Memory
The CMX7861 has been designed to function with the AT25F512 serial flash device, however other
manufacturers' parts may also be suitable. The time taken to load the FI should be less than 500ms even
when loading the largest possible Function Image™.
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CMX7861 FirmCODEC® Programmable Baseband Interface
7.4
CMX7861
Device Control
Once the Function Image™ is loaded, the CMX7861 can be set into one of four main modes using the
Mode Register- $6B write register:
Idle mode – for configuration or low power operation
Transmit mode – DAC operating
Receive mode – ADC operating
Duplex mode - DAC and ADC operating.
These four modes are described in the following sections. All control is carried out over the C-BUS
interface: either directly to operational registers in transmit, receive and duplex modes or, for parameters
that are not likely to change during operation, using the Programming Register - $6A write in Idle mode.
To conserve power when the device is not actively processing a signal, place the device into Idle mode.
Additional power-saving can be achieved by disabling unused hardware blocks, however, most of the
hardware power-saving is automatic. Note that VBIAS must be enabled to allow any of the Input or Output
blocks to function. It is only possible to write to the Programming register whilst in Idle mode. See:
9.1.16 Programming Register - $6A write
9.1.17 Mode Register- $6B write
9.2 Programming Register Operation
9.1.24 VBIAS Control - $B7 write.
7.4.1
Normal Operation Overview
In normal operation (after the CMX7861 is configured) the appropriate mode must be selected and
samples provided in transmit or retrieved in receive. This process is carried out by selecting the mode (Tx,
Rx or Duplex) and selecting which samples are required.
For example, in transmit mode, transmit samples are routed to DAC1 and DAC2 and subsequently to
output 1,2,3,or 4.
Output samples should be provided in the Tx FIFO, and samples are received using the Rx FIFO.
The CMX7861 can be configured to interrupt the host on FIFO fill level.
The CMX7861 offers internal buffering of data in addition to the Command and Rx FIFOs in both receive
and transmit directions. In the process of burst transmission or reception, the most significant registers
are:
9.1.17 Mode Register- $6B write
9.1.34 IRQ Status - $7E read
9.1.18 IRQ Mask - $6C write
9.1.3 Tx FIFO Data/Control - $48, $49 and $4A write
9.1.26 Receive FIFO Data/Control - $4C, $4D, $4E read
9.1.25 Tx FIFO Level - $4B read
9.1.27 Receive FIFO Level - $4F read.
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7.4.2
CMX7861
Basic Tx and Rx Operation
The CMX7861 has many features that provide a great deal of flexibility, but basic signal transmission and
reception can be carried out fairly easily by understanding the operation of just a few registers. There are
other ways of controlling signal transmission and reception but basic examples are given below:
Basic Transmit Operation (the DACs are operating)
The following is an example of the transmission of I/Q samples when the device is used in I/Q mode
Note: for this example, a ‘DAC1 sample’ refers to an I sample, and a ‘DAC2’ sample refers to a Q sample.
C-BUS Operation
Write $0080 to FIFO Control
- $50 write
Write $8010 to the Tx FIFO
Word (see Tx FIFO
Data/Control - $48, $49 and
$4A write)
Write $0020 to the Tx FIFO
Word (see Tx FIFO
Data/Control - $48, $49 and
$4A write)
Action
Flush the Tx FIFO
Write 2 DAC2 sample data
bytes: $30 and $40 to the
TxFIFO Data Byte - see Tx
FIFO Data/Control - $48,
$49 and $4A write
Write 8 groups of 4 data
bytes (32 bytes total) to the
TxFIFO Data Byte - see Tx
FIFO Data/Control - $48,
$49 and $4A write
Complete the
sample block
Write $0043 to Mode
Register- $6B write
Poll the Tx FIFO Level - $4B
read register, wait until there
are less than 32 data bytes
in the Tx FIFO
Start transmission
Write 8 groups of 4 data
bytes (32 bytes total) to the
TxFIFO Data Byte - see Tx
FIFO Data/Control - $48,
$49 and $4A write
Write $8600 to the Tx FIFO
Word (see Tx FIFO
Data/Control - $48, $49 and
$4A write)
Poll the IRQ Status - $7E
read register for bit 10 – Tx
Done = 1
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Set sample start
flag, set DAC1
upper =10
Clear sample start
flag, set DAC1
lower=$20
Create a buffer of 8
sample blocks
Wait until there is
space for new
samples to be
loaded into the Tx
FIFO.
Provide 8 more
sample blocks
Indicate end of
transmission
Wait until the
transmission ends
Description
To ensure that no data is remaining from
previous transmissions
The sample start flag indicates to the CMX7861
that this is the first word of a sample block. The
upper byte of the first DAC1 sample =$10.
The high to low transition of the sample start flag
indicates to the CMX7861 that this is the second
word of a sample block. The lower byte of the
first DAC1 sample =$20, so the first DAC1
sample =$1020.
DAC2 upper=$30, DAC2 lower=$40, so the first
DAC2 sample=$3040. Streaming C-BUS may
be used for faster data loading.
The sequence DAC1 upper, DAC1 lower, DAC2
upper, DAC2 lower is repeated 8 times, in order
to create a buffer, so that the host does not
need to write data as promptly for the rest of the
transmission. Streaming C-BUS may be used
for faster data loading. The sample start flag
may be left low.
Initiates a transmission beginning with the first
DAC1 and DAC2 sample pair
The choice of 32 data bytes as a level is fairly
arbitrary – here we want to make sure that there
is space for the amount of data that we provide
in the next step.
Provide more samples to continue the
transmission. Streaming C-BUS may be used
for faster data loading. The sample start flag
may be left low. This and the previous step
continue for as long as the transmission.
This indicates to the CMX7861 that DAC1 and
DAC2 samples are about to intentionally run out.
The transmission has completed. It is now
possible to transition to other modes, or transmit
another burst using the Mode Register- $6B
write register.
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The procedure described above can be adapted, providing DAC1 or DAC2 samples and servicing the Tx
FIFO with different fill levels. The FIFO Control - $50 write, IRQ Status - $7E read and IRQ Mask - $6C
write registers can be used to configure the CMX7861 to interrupt the host once the Tx FIFO fill level
drops below a specified threshold.
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Basic Receive Operation (the ADCs are operating)
The following is an example of receiving I/Q samples when the device is used in I/Q mode
Note: for this example, an ‘ADC1 sample’ refers to an I sample, and an ‘ADC2’ sample refers to a Q
sample.
C-BUS Operation
Write $8000 to FIFO
Control - $50 write
-
Action
Flush the Rx FIFO
Write $0403 to Mode
Register- $6B write
Start reception
Poll the Receive FIFO
Level - $4F read
register, wait until there
are at least 4 data bytes
in the Rx FIFO
Read the Rx FIFO Word
– see Receive FIFO
Data/Control - $4C,
$4D, $4E read
Wait until there is one
sample block in the Rx
FIFO
Read the Rx FIFO Data
Byte register – see
Receive FIFO
Data/Control - $4C,
$4D, $4E read
Read ADC1 lower
Read the Receive FIFO
Data Byte (see Receive
FIFO Data/Control $4C, $4D, $4E read) 2
more times
Poll the Receive FIFO
Level - $4F read
register, wait until there
are at least 4 data bytes
in the Rx FIFO
Read the Receive FIFO
Data Byte (see Receive
FIFO Data/Control $4C, $4D, $4E read) 4
more times
-
Retrieve the ADC2
sample: ADC2 upper,
ADC2 lower
-
End of reception
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Apply input signal
Read start flag, ADC1
upper
Description
To ensure that no data is remaining from
previous sample reception
The input signal should contain a waveform of
significant amplitude and within the bandwidth of
the CMX7861, given its ADC configuration
Initiates reception of ADC1/ADC2 samples.
These will propagate through the CMX7861 and
become available in the Rx FIFO
A sample block is available, this will be read in
the following steps
Read the Rx FIFO Word register and verify that
the most significant bit is set. This indicates the
start of a sample block. The lower 8 bits of the
value returned are the 8 most significant bits of
the ADC1 sample.
Reading the data byte only is more efficient than
reading the whole Rx FIFO Word. The value
returned is the 8 least significant bits of the
ADC1 sample. This step may be combined with
the one below using streaming C-BUS to
improve efficiency further.
The ADC2 sample is read from the Receive
Data FIFO.
Wait until there is a
second sample block in
the Rx FIFO
A sample block is available, this will be read in
the next step
Retrieve the ADC1 and
ADC2 samples: ADC1
upper, ADC1 lower,
ADC2 upper, ADC2
lower
Repeat as required
Another ADC1/ADC2 sample block is read from
the Rx FIFO. Streaming C-BUS may be used to
reduce transfer overhead.
The last 2 steps may be repeated as many
times as required. It is possible to wait for a
higher Rx FIFO fill level, and to stream many
sample blocks from the CMX7861 at once.
Once enough samples have been received a
mode change (using the Mode Register- $6B
write register) will stop reception.
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The procedure described above can be adapted, receiving ADC1 or ADC2 samples and servicing the Rx
FIFO with different fill levels. The FIFO Control - $50 write, IRQ Status - $7E read and IRQ Mask - $6C
write registers can be used to configure the CMX7861 to interrupt the host once the Rx FIFO fill level rises
above a specified threshold.
The registers used for basic transmission and reception are:
9.1.17 Mode Register- $6B write
9.1.34 IRQ Status - $7E read
9.1.3 Tx FIFO Data/Control - $48, $49 and $4A write
9.1.26 Receive FIFO Data/Control - $4C, $4D, $4E read
9.1.4 FIFO Control - $50 write.
7.4.3
Device Configuration (Using the Programming Register)
While in Idle mode the Programming register becomes active. The Programming register provides access
to the Program Blocks. Program Blocks allow configuration of the CMX7861 during major mode change.
Features that can be configured include:
Configuration of RAMDAC profile
Configuration of System Clock outputs
Configuration of SPI Thru-Port rate and word format
Configuration of transmit and receive filters.
Full details of how to configure these aspects of device operation are given in section 9.2, in the User
Manual.
7.4.4
Device Configuration (Using dedicated registers)
Some device features may be configured using dedicated registers. This allows for configuration outside
of Idle mode. Configuration of the following features is possible:
Auxiliary ADC detect thresholds
Auxiliary ADC input selection and averaging mode
Output gain
Output dc offsets.
The registers that allow configuration of these features are:
9.1.8 DAC1/DAC2 Output Control - $5D, $5E write
9.1.9 ADC1/ADC2 Input Control - $5F, $60 write
9.1.20 Input 1-4 Coarse Gain - $B1, $B2 write
9.1.22 Output 1 and 2 Coarse Gain - $B4, $B5 write
9.1.21 Output 1 - 4 Configuration - $B3 write
9.1.19 Input 1 - 4 Configuration - $B0 write
9.1.5 AuxADC1-4 Control - $51 to $54 write
9.1.6 AuxADC1-4 Threshold- $55 to $58 write
9.1.10 Signal Control - $61 write.
7.4.5
Interrupt Operation
The CMX7861 can produce an interrupt output when various events occur. Examples of such events
include FIFO threshold being reached, an overflow of the internal data buffering in receive, or completion
of transmission whilst in transmit.
Each event has an associated IRQ Status register bit and an IRQ Mask register bit. The IRQ Mask
register is used to select which status events will trigger an interrupt on the IRQN line. All events can be
masked using the IRQ mask bit (bit 15) or individually masked using the IRQ Mask register. Enabling an
interrupt by setting a mask bit (0 1) after the corresponding IRQ Status register bit has already been set
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to 1 will also cause an interrupt on the IRQN line. The IRQ bit (bit 15) of the IRQ Status register reflects
the IRQN line state.
All interrupt flag bits in the IRQ Status register are cleared and the interrupt request is cleared following
the command/address phase of a C-BUS read of the IRQ Status register. See:
9.1.34 IRQ Status - $7E read
9.1.18 IRQ Mask - $6C write.
7.4.6
Signal Control
The CMX7861 offers four signal inputs: Input 1 (or I in an I/Q-based system), Input 2 (or Q in an I/Q-based
system), Input 3 and Input 4. It offers four signal outputs: Output 1 (or I in an I/Q-based system), Output 2
(or Q in an I/Q-based system), Output 3 and Output 4.. The analogue gain/attenuation of each input and
output can be set individually.
During I/Q transmit, I Output and Q Output will output in-phase and quadrature output signals. They may
be independently inverted and their gains changed. During I/Q receive, I Input and Q Input will accept inphase and quadrature modulated signals. They may be independently inverted and their gains changed.
See:
9.1.8 DAC1/DAC2 Output Control - $5D, $5E write
9.1.9 ADC1/ADC2 Input Control - $5F, $60 write
9.1.20 Input 1-4 Coarse Gain - $B1, $B2 write
9.1.22 Output 1 and 2 Coarse Gain - $B4, $B5 write
9.1.23 Output 3 and 4 Coarse Gain - $B6 write
9.1.21 Output 1 - 4 Configuration - $B3 write
9.1.19 Input 1 - 4 Configuration - $B0 write.
7.4.7
Tx Mode Processing
In Tx mode the 7861FI-1.x provides two independent DAC outputs. Often these may be used to generate
In-phase and quadrature signal outputs for I/Q baseband modulation but they are general purpose and
can re-create two unrelated signals. The signal processing chain is shown below:
CDATA
IRQN
Registers
Host
µC
RDATA
CSN
SCLK
Tx FIFO
Buffer
De-Mux
Transmission
Samples
From Tx CBUS FIFO
DAC
1
Interpolate
Low Pass Filter
DAC
2
Interpolate
OUTPUT 1
(or I output for an
I/Q-based system)
OUTPUT 2
(or Q output for an
I/Q-based system)
Low Pass Filter
Figure 17 Tx Mode Processing
The Interpolation stage and user-programmable low-pass filter stage shown in Figure 17 Tx Mode
Processing are both optional. When deactivated, the host must provide samples at the sample rate which
the CMX7861 was configured to run at. This provides the ability to recreate any format of signal (subject
to bandwidth constraints), but requires a lot of data to be transferred between host and CMX7861.
When producing frequency modulation and using the CMX7861 to produce 2-point modulation of GFSK or
4FSK signals, it is beneficial to activate the interpolation stage and low pass filter. To do this the filter
must be designed correctly, with knowledge of the required number of samples per symbol and the
interpolation factor must be configured to match. Typical filter designs would be root raised cosine, raised
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cosine or Gaussian. The result is that the host may then feed mapped symbols (typically with 2, 4 or 8
levels) with the I symbol equal to the Q symbol into the CMX7861 which will interpolate and apply the
pulse shaping filtering. The result is two signals on the I and Q outputs, which are not a quadrature signal
but instead are suitable for providing two-point modulation to an FM modulator.
When producing phase or phase and amplitude modulations and using the CMX7861 to produce the I,Q
baseband signal, it is beneficial to activate the interpolation stage and low pass filter. Typical applications
are producing QPSK, QAM or /4DQPSK modulation. To do this the filter must be designed correctly,
with knowledge of the required number of samples per symbol, the interpolation factor must be configured
to match. Typical filter designs would be root raised cosine or raised cosine. The result is that the host
may then feed mapped symbols representing the mapped I/Q constellation points into the CMX7861
which will interpolate and apply the pulse shaping filtering. The result is a filtered baseband quadrature
signal on the I and Q outputs which are suitable for converting to RF.
In either the FM modulation or phase/amplitude modulation examples above the CMX7861 provides
additional processing- removing the requirement for filtering from the host, and reducing the data transfer
rate required from the chosen sample rate down to the symbol rate.
7.4.8
Rx Mode Processing
In Rx mode the 7861FI-1.x provides two independent ADC inputs. Often these may be used to sample inphase and quadrature signals for I/Q baseband demodulation by the host, but they are general purpose
and can sample two unrelated signals. The signal processing chain is shown below:
ADC
1
Magnitude
Mux
Samples For
loading into
C-BUS Rx
FIFO
Channel Filter
INPUT 2
(or Q input for an I/Qbased system)
ADC
2
Channel Filter
RSSI
Phase
CDATA
Buffer
Rx FIFO
Registers
INPUT 1
(or I input for an I/Qbased system)
Cartesian
to Polar
conversion
RDATA
CSN
SCLK
Host
µC
IRQN
Channel 2 DC offset
Channel 1 DC offset
Figure 18 Rx Mode Processing
The CMX7861 receive processing provides user programmable channel filtering in order to reduce host
processing load. In the general case, the filtered I/Q samples may simply be retrieved by the host from
the Rx FIFO. This is the expected configuration for sampling two arbitrary signals, or using the CMX7861
in a QPSK or QAM receiver. In the case of a QPSK or QAM receiver the channel filters often provide a
root raised cosine response matched to the transmit filtering. Built-in filters are provided which fulfil this
purpose.
When receiving FM signals using an I/Q input the CMX7861 provides part of the FM demodulation
process. Once filtered, I and Q dc offsets 1may be removed by the CMX7861 but must be computed by
the host. This allows a cartesian to polar conversion to take place and to correctly compute the
instantaneous phase of the received I,Q vector. The phase samples, along with I and Q samples, are
provided in the Rx FIFO for the host to use in the FM demodulation process.
When receiving FM signals using a limiter discriminator receiver the CMX7861 may be configured to
provide filtering matched to the transmitter modulating signal. This may be interfaced to either the I or Q
input (we are not sampling a quadrature signal in this case), with a typical RSSI signal from the receiver
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fed into the other ADC. The CMX7861 can be configured to average the RSSI samples and to provide
them to the host, alongside the filtered Limiter discriminator output.
7.4.9
Duplex Mode
The duplex mode combines transmit and receive modes.
Both transmit and receive operate
simultaneously with the same signal processing involved as described in sections 7.4.7 Tx Mode
Processing and 7.4.8 Rx Mode Processing.
1I/Q
dc offsets are often introduced by radio receiver hardware. It is essential to calculate and remove
them prior to demodulation. In the case of FM demodulation, they must be removed prior to calculation of
signal phase, so this correction is required within the CMX7861.
7.4.10
Other Modes
The CMX7861 provides a pass-through diagnostic mode. This results in the I/Q inputs being channel
filtered, any dc offsets subtracted and the resulting signal being passed out of the I and Q outputs.
When receiving QAM or QPSK signals the pass-through mode may be used to observe the matched
filtered I/Q constellation diagram. Note however that if a significant frequency error exists between
transmitter and receiver the constellation diagram will appear to rotate rapidly and be difficult to interpret.
Figure 19 Constellation
Diagram – no frequency or
phase error
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Figure 20 Constellation
Diagram – phase error
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Figure 21 Constellation
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When receiving FM modulated signals through a limiter discriminator receiver the pass-through mode may
be used to observe the matched filtered data (modulating signal) in an eye diagram. One of the
CMX7861 GPIO pins may be used as a trigger locked to the sample rate, in order to display an eye
diagram on an oscilloscope. Note that best results are often obtained with an analogue oscilloscope.
Figure 22 Received Eye Diagram
When enabled as an output, any of the GPIO signals can be configured to produce a pulse train locked to
the sample rate of the receiving CMX7861 to aid triggering whilst viewing the constellation or eye diagram
(I Output or Q Output alone vs time) or other diagnostic modes in receive. In some cases it is advisable to
obtain a trigger pulse that is synchronised to the transmitting modem symbol rate, for example if the
transmitted signal comes from a signal generator.
See:
9.1.17 Mode Register- $6B write
9.1.10 Signal Control - $61 write
9.1.13 GPIO Control - $64 write
9.2.3 Program Block 1 – Clock Control
7.4.11 Data Transfer
The payload data is transferred to and from the host via the C-BUS Tx and Rx Data FIFOs, each of which
provide efficient streaming C-BUS access. FIFO fill level can be determined by reading the Receive FIFO
Level and Tx FIFO Level registers and controlled using FIFO Control - $50 write register. Interrupts may
be provided on FIFO fill thresholds being reached.
Each FIFO word is 16 bits, with the least significant byte (LSByte) containing data, and the most
significant (MSByte) containing control information. The control and data bytes may be written or read
together using the Receive FIFO Word and Tx FIFO Word registers, or individually using their byte-wide
registers.
Word wide FIFO writes involve writing 16-bit words to the Tx FIFO Word register using either a single
write or streaming C-BUS. The whole word written is put into the Tx FIFO, with the upper byte interpreted
as control and the lower byte as data. This causes the control byte to be held in the Tx FIFO Control Byte
register.
Byte wide FIFO writes involve writing to the Tx FIFO Data Byte register using either single access or
streaming C-BUS. This causes the Tx FIFO Control Byte (MSByte) and data written to the Tx FIFO Data
Byte (LSByte) registers to be put into the Tx FIFO as one word. The control byte can be written separately
as a single byte (this does not result in anything being added to the FIFO) or is preserved from a previous
16-bit Tx FIFO Data Byte write.
Likewise a word read from the Rx Data FIFO will return the Receive FIFO Control Byte in the MSByte and
the Receive FIFO Data Byte at the top of the FIFO in the LSByte. Both registers will be updated so that
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when read next time they will provide details of the next item in the FIFO. Reading the Receive FIFO
Control Byte only will not change the FIFO content. Reading the Receive FIFO Data Byte only will provide
the data and remove the item from the FIFO – updating both control and data registers (see also Table 4).
Table 4 FIFO Transfer Summary
Operation
write Tx FIFO Control
Byte register
write Tx FIFO Data Byte
register
write Tx FIFO Word
register
Effect
Tx FIFO control word updated, nothing added to Tx FIFO
Tx FIFO control word + data byte written are added to Tx FIFO
data word (control and data bytes) is added to Tx FIFO.
Tx FIFO control word updated for future writes.
Rx FIFO control word is returned, no effect on Rx FIFO contents
read Receive FIFO
Control Byte register
read Receive FIFO Data
Byte register
read Receive FIFO Data
Word register
Tx
Level
Oldest Rx FIFO data byte is removed from FIFO and returned, Rx FIFO Word
updated
Oldest Rx FIFO data word (control and data bytes) is removed from FIFO and
returned, Rx FIFO control word updated
C-BUS
interface
Rx Level
TX FIFO LEVEL
RX FIFO LEVEL
TX FIFO CTRL
RX FIFO CTRL
RX FIFO
DATA BYTE
mux
mux
MSB
LSB
LSB
128x16 TX FIFO
bit 15-8
TX FIFO
DATA BYTE
bit 7-0
RX FIFO
DATA WORD
bit 7-0
bit 15-8
Tx Level
TX FIFO
DATA WORD
MSB
128x16 RX FIFO
Rx Level
Figure 23 Tx and Rx Data FIFOs
Single channel (DAC1 or DAC2) or dual channel (DAC1 and DAC2) samples may be transmitted using
the CMX7861, selected using the Mode Register- $6B write register. Likewise single or dual channels
may be received. Duplex operation provides simultaneous output and input. Relevant registers are:
9.1.17 Mode Register- $6B write
9.1.3 Tx FIFO Data/Control - $48, $49 and $4A write
9.1.26 Receive FIFO Data/Control - $4C, $4D, $4E read
9.1.25 Tx FIFO Level - $4B read
9.1.27 Receive FIFO Level - $4F read
9.1.4 FIFO Control - $50 write.
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7.4.12 Sample Format
The CMX7861 uses the Tx FIFOs to transmit several types of sample:
Single channel samples for DAC1 or DAC2, for example, an I or Q output
Dual channel DAC1/DAC2 sample pairs, for example an I/Q pair of samples
In receive there are more sample formats available, which include:
Single channel samples for ADC1 or ADC2, for example, an I or Q input
Dual channel ADC1/ADC2 sample pairs, for example, an I/Q pair of samples
Phase, magnitude samples computed by the CMX7861 from sampled I/Q data.
In order to package the variety of sample formats and to provide timing and synchronisation information
the CMX7861 uses sample blocks. A sample block consists of control/synchronisation information and
sample data. It is packaged so that the control information can be optionally read when it is required – so
that data throughput is maximised.
In receive the sample block control information can be read from the Rx FIFO control byte, the sample
data can be read from the data byte, or both together from the Rx FIFO Word register.
When read from the Rx FIFO Word register a sample pair will provide the information as shown in Table
5.
Table 5 Rx ADC1/ADC2 sample blocks
ADC1/ADC2 sample block
Rx FIFO control byte
Bit No
14
13
12
11
Rx FIFO data byte
Word1
15
1
10
9
8
0
0
0
7
6
5
4
3
2
1
Word2
0
Word3
0
Most significant byte of ADC2 sample (upper)
Word4
0
Least significant byte of ADC2 sample (lower)
0
Most significant byte of ADC1 sample (upper)
Rx sample number
Least significant byte of ADC1 sample (lower)
ADC1 sample block
Rx FIFO control byte
Bit No
Word1
15
1
Word2
0
14
13
12
11
Rx FIFO data byte
10
9
8
0
0
1
7
6
5
4
3
2
1
0
Most significant byte of ADC1 sample (upper)
Rx sample number
Least significant byte of ADC1 sample (lower)
ADC2 sample block
Rx FIFO control byte
Bit No
Word1
15
1
Word2
0
14
13
12
11
Rx FIFO data byte
10
9
8
0
1
0
Rx sample number
7
6
5
4
3
2
1
0
Most significant byte of ADC2 sample (upper)
Least significant byte of ADC2 sample (lower)
Bit 15 is a synchronisation bit. It will always be set in the first word of a sample block, and cleared in the
others. Its purpose is to provide an indication of the start of a sample, so if FIFOs or buffers have been
allowed to overflow and samples lost it becomes possible to establish (for example) which is an I and
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which is a Q sample. When synchronisation has been established, or if no overflow ever happened it is
possible to read only the Rx FIFO data byte and retrieve the raw sample data.
The sample number field is used to establish time of arrival of received sampled data. It provides a time
stamp for each received sample and allows the host driver to calculate a Tx sample number field to pass
to the CMX7861 to specify time of transmission.
The sample type is indicated using bits 10, 9, 8 of Word 1. This feature allows the host to ask the
CMX7861 to continually sample signals whilst dynamically changing the format of sample requested. For
example: initially request I/Q, phase, amplitude samples to establish the I/Q dc offset corrections required.
Then to provide more efficient operation by only requesting phase samples. The sample type field within
the sample block allows the host to establish which samples are from before the dynamic switch and
which are from after – ie to confirm the sample type.
A similar format applies to other sampled data types, as shown in Table 6.
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Table 6 Rx ADC1/ADC2, Phase/Magnitude sample blocks
Phase, Magnitude sample block
Rx FIFO control byte
Rx FIFO data byte
Bit No
Word1
15
1
14
13
12
11
10
9
8
1
0
0
7
6
5
4
3
2
1
0
Word2
0
Word3
0
Most significant byte of Magnitude sample (Mupper)
Word4
0
Least significant byte of Magnitude sample (Mlower)
Most significant byte of Phase sample (Pupper)
Rx sample number
Least significant byte of Phase sample (Plower)
Phase sample block
Rx FIFO control byte
Bit No
Word1
15
1
Word2
0
14
13
12
11
Rx FIFO data byte
10
9
8
1
0
1
7
6
5
4
3
2
1
0
Most significant byte of Phase sample (Pupper)
Rx sample number
Least significant byte of Phase sample (Plower)
Magnitude sample block
Rx FIFO control byte
Bit No
Word1
15
1
Word2
0
14
13
12
11
Rx FIFO data byte
10
9
8
7
1
1
0
Most significant byte of Magnitude sample (Mupper)
Rx sample number
6
5
4
3
2
1
0
Least significant byte of Magnitude sample (Mlower)
ADC1/ADC2, Phase, Magnitude sample block
Rx FIFO control byte
Rx FIFO data byte
Bit No
Word1
15
1
14
13
12
11
10
9
8
1
1
1
Word2
0
Word3
0
Most significant byte of ADC2 sample (upper)
Word4
0
Least significant byte of ADC2 sample (lower)
Word5
0
Most significant byte of Phase sample (Pupper)
Word6
0
Least significant byte of Phase sample (Plower)
Word7
0
Most significant byte of Magnitude sample (Mupper)
Word8
0
Least significant byte of Magnitude sample (Mlower)
Rx sample number
7
6
5
4
3
2
1
0
Most significant byte of ADC1 sample (upper)
Least significant byte of ADC1 sample (lower)
Similarly to the sample block format provided by the CMX7861, samples for transmission contain sampled
data and optional control information. See Table 7 for details.
Bit 15 is a synchronisation bit, which the CMX7861 will always process. When the CMX7861 detects a 1
to 0 transition in the synchronisation bit it will treat that as the start of a sample block. When no 1 to 0
transition is detected it will continue to count Tx FIFO entries and assume that each frame is complete.
This mechanism allows the host to optionally provide control information when required and to maximise
C-BUS throughput by just writing the Tx data byte at other times.
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Tx Time Block: This block instructs the CMX7861 to wait until a specified time before allowing further
samples to be output. ’Time’ is specified as the sample number at which to begin transmitting. This allows
synchronisation of the transmitted signal with received signals. For example, having detected a
framesync when processing sample N the host can specify that a transmission should occur at sample
number N+k to ensure transmit – receive synchronisation. This is of particular use in time division
multiple access (TDMA) slotted systems. The host can read the current time as seen by CMX7861 using
the Sample Time - $7D read register.
Tx End Block: This block allows that host to optionally specify the end of transmission. In situations where
the host needs to know the precise moment when the transmission ends, such as bursty transmissions,
the host may write a Tx End Block as the last data word in the Tx FIFO Data/Control - $48, $49 and $4A
write register.
When Tx End Block is written by the host, the CMX7861 signals a Tx Done status bit in the IRQ Status $7E read register after outputting the last Tx sample. This feature can be used by the host to ramp down
the power amplifier at the end of a transmission.
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CMX7861
Table 7 Tx DAC1/DAC2 sample blocks
DAC1/DAC2 Sample Pair
Tx FIFO control byte
Bit No
14
13
12
11
Tx FIFO data byte
Word1
15
1
10
9
8
0
0
0
7
6
5
4
3
2
1
Word2
0
Least significant byte of DAC1 sample (lower)
Word3
0
Most significant byte of DAC2 sample (upper)
Word4
0
Least significant byte of DAC2 sample (lower)
0
Most significant byte of DAC1 sample (upper)
DAC1 Sample Only
Tx FIFO control byte
Bit No
Word1
15
1
Word2
0
14
13
12
11
Tx FIFO data byte
10
9
8
0
0
1
7
6
5
4
3
2
1
0
Most significant byte of DAC1 sample (upper)
Least significant byte of DAC1 sample (lower)
DAC2 Sample Only
Tx FIFO control byte
Bit No
Word1
15
1
Word2
0
14
13
12
11
Tx FIFO data byte
10
9
8
0
1
0
7
6
5
4
3
2
1
0
Most significant byte of DAC2 sample (upper)
Least significant byte of DAC2 sample (lower)
Tx Time Block
Bit No
15
1
Word2 0
14
Word1
Tx FIFO control byte
13
12
11
10
1
9
1
8
1
7
6
Tx FIFO data byte
5
4
3
2
1
0
1
0
Most significant byte of Time
Least significant byte of Time
Tx End Block
Bit No
15
Word1 1
14
Tx FIFO control byte
13
12
11
10
1
9
1
8
0
7
6
5
Tx FIFO data byte
4
3
2
Don’t Care
7.4.13 Data Buffering
To expand the buffering capabilities of the CMX7861 two internal buffers are provided:
A Tx buffer which buffers transmit data from the Tx FIFO.
An Rx buffer which buffers received data yet to be loaded into the Rx data FIFO.
Transfer between the FIFOs and their respective buffers will occur regardless of mode. Such transfer is
not instantaneous so the FIFO fill levels should be used to indicate how much data the host may read or
write at any time.
The Internal Buffer Fill Level - $70 read register allows the buffer fill levels to be read; their contents will
be flushed when the respective FIFO is flushed.
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CMX7861
See:
9.1.4 FIFO Control - $50 write
9.1.28 Internal Buffer Fill Level - $70 read.
7.4.14 Managing Data Transfer
In transmit it is important to avoid an underflow – if an output sample is required and one is not available,
transmission will not be continuous. This is indicated by the Tx Empty flag in the IRQ Status - $7E read
becoming set. It is advisable to pre-load data into the Tx FIFO before transmission begins.
In receive it is important to avoid an overflow – if a sample is received and space to store it is not available
in the CMX7861, reception will not be continuous. This is indicated by the Rx OV flag in the IRQ Status $7E read becoming set.
FIFO levels or FIFO level IRQs may be used to manage the data flow. For both transmit and receive
operation.
7.4.15 GPIO Pin Operation
The CMX7861 provides four GPIO pins, each pin can be configured independently as an input or an
output.
See:
9.1.13 GPIO Control - $64 write
9.1.32 GPIO Input - $79 read.
7.4.16 Auxiliary ADC Operation
The inputs to the four Auxiliary ADCs can be independently routed from any of four dedicated AUXADC
input pins or the two main inputs. Auxiliary ADCs can be disabled to save power. BIAS in the VBIAS
Control - $B7 write register must be enabled for Auxiliary ADC operation.
Averaging can be applied to the ADC readings by selecting the relevant bits in the AuxADC1-4 Control $51 to $54 write registers. This is a rolling average system such that a proportion of the current data will
be added to the last value. The proportion is determined by the value of the average counter in the
AuxADC1-4 Control - $51 to $54 write registers. Setting the average counter to zero will disable the
averager, for an average value of 1; 50% of the current value will be applied, for a value of 2 = 25%, 3 =
12.5%, continuing up to the maximum useful value of 11 = 0.0488%.
High and low thresholds may be independently applied to both ADC channels (the comparison is applied
after averaging, if this is enabled) and an IRQ generated when an input exceeds the high or low threshold,
or on every sample as required. The thresholds are programmed via the AuxADC1-4 Threshold- $55 to
$58 write register.
Auxiliary ADC data is read back in the AuxADC1-4 Read - $71 to $74 read registers and includes the
threshold status as well as the actual conversion data (subject to averaging, if enabled).
The AuxADC sample rate is selected using Program Block 1 – Clock Control.
See:
9.1.5 AuxADC1-4 Control - $51 to $54 write
9.1.6 AuxADC1-4 Threshold- $55 to $58 write
9.1.29 AuxADC1-4 Read - $71 to $74 read
9.2.3 Program Block 1 – Clock Control
9.1.24 VBIAS Control - $B7 write.
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CMX7861
7.4.17 Auxiliary DAC/RAMDAC Operation
The four Auxiliary DACs are programmed via the AuxDAC1-4 Control - $59 to $5C write registers.
AuxDAC1 may also be programmed to operate as a RAMDAC which will autonomously output a preprogrammed profile at a programmed rate. The AuxDAC1-4 Control - $59 to $5C write register, with b12
set, controls the RAMDAC mode of operation. The RAMDAC ramp rate is controlled by the Internal
system clock rate, which changes between active CS/Tx/Rx modes and Idle mode. Therefore it is
inadvisable to return to Idle mode prior to RAMDAC ramp completion.
The default profile is a Raised Cosine (see Table 16 in the user manual), but this may be over-written with
a user-defined profile by writing to Program Block 0. The AuxDAC outputs hold the user-programmed
level during a powersave operation if left enabled, otherwise they will return to zero.
See:
9.1.7 AuxDAC1-4 Control - $59 to $5C write
9.2.2 Program Block 0 – RAMDAC
9.2.3 Program Block 1 – Clock Control
7.4.18 SPI Thru-Port
The CMX7861 offers an SPI Thru-Port which allows the host, using the main C-BUS interface, to
command the CMX7861 to read or write up to three external SPI/C-BUS devices attached to the
CMX7861. The CMX7861 acts as a SPI/C-BUS master in this mode, controlling three chip selects, clock
and data out (MOSI), and receiving data in (MISO).
Each individual SPI/C-BUS device can be independently configured using Program Block 6 – SPI ThruPort Configuration to have clock speed, inter-frame guard period and clock phase/polarity to match the
specification of the slave SPI/C-BUS device attached. In order to offer a simpler, more convenient
interface, a device can be designated C-BUS, rather than SPI. This means that data read/written is
assumed to be in the format:
Address byte, data byte1 (optional), data byte 2 (optional).
In each case the CMX7861, as the master, drives the address and data for a write operation, or drives the
address and receives the data for a read operation. Commands can be called 0, 1 or 2 byte reads or
writes – with a 0 byte write typically being a reset command. As the word format is known, then for
convenience only the desired read data is returned to the host.
SPI mode is a little more flexible. No assumption is made about the SPI word format, nor any assumption
that the length is a whole number of bytes.
See:
9.1.11 SPI Thru-Port Control - $62 write
9.1.12 SPI Thru-Port Write - $63 write
9.1.31 SPI Thru-Port Read - $78 read
9.2.8 Program Block 6 – SPI Thru-Port Configuration
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7.5
CMX7861
Digital System Clock Generators
The CMX7861 includes a two-pin Xtal oscillator circuit. This can either be configured as an oscillator, as
shown in section 5.1, or the XTAL/CLK input can be driven by an externally-generated clock. The crystal
(Xtal) source frequency is typically 9.6MHz and if an external oscillator is used, the input frequency is
typically 9.6 or 19.2 MHz. For both cases reference frequencies in the range specified in 8.1.2 Operating
Limits may be used.
7.5.1
Main Clock Operation
A digital PLL is used to create the main clock for the internal sections of the CMX7861. The configuration
of the main clock and the internal clocks derived from it are controlled using Program Block 1 – Clock
Control.
The CMX7861 defaults to settings appropriate for a 19.2MHz externally-generated clock with a sample
rate of 48000 samples/s, however if a different reference frequency is to be used, or a different sample
rate required, then Program Block entries P1.1 to P1.6 will need to be programmed appropriately at
power-on. A table of preferred values is provided in Table 17 and Table 18 in the User Manual along with
details of how to calculate settings for other sample rates and crystal frequencies.
Prog Reg P1.2
PLL ClkIn
(XTAL)
÷1 to Ref Clk
512
Ph
Det
Prog Reg P1.3
VCO
Q
Pump
÷1 to
4096
Loop
Filt
Lock
Timer
VCO Clk
MAIN PLL
PLL ClkOut
Tx/Rx (Active)
Prog Reg P1.5
SYMBOL
CLOCK
DIVIDER
÷1 to 256
(Idle)
Main PLL
out
Sample Clk
Prog Reg P1.1(Idle), P1.4(Active)
Internal
CLK
DIVIDER
÷1 to 64
Prog Reg P1.0
Aux ADC CLK
DIVIDER
÷3 to 1024
Internal
System Clk
Aux ADC
Clock
Figure 24 Main Clock Generation
See:
9.2.3 Program Block 1 – Clock Control.
7.5.2
System Clock Operation
Two System Clock outputs, SYSCLK1 and SYSCLK2, are available to drive additional circuits, as
required. The System Clock circuitry is shown in Figure 25 Digital System Clock Generation Schemes.
Having chosen the input frequency source, system clock generation may be by simply dividing the input
frequency source, or via its own phase locked loop. The system clock PLL does not affect any other
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CMX7861
internal operation of the CMX7861 – so if a frequency that is not a simple fraction of the Xtal is required, it
can be used with no side effects. There is one phase locked loop, with independent output dividers to
provide phase locked output signals.
SYSPLLCON0
SYSPLLCON1
÷1 to Ref Clk
512
Ph
Det
÷1 to
4096 Local Clk
SYSPLLCON2
VCO
Q
Pump
÷1 or
÷2
Loop
Filt
Lock
Timer
VCO Clk
SYSCLK PLL
PLL ClkIn
PLL ClkOut
SysClkIn
(XTAL)
1
SYSCLKDIV1 b15, 13, 5-0
0
2
SYSCLK1
DIVIDER
÷1 to 64
SYSCLKCON b1-0
1
0
SYSCLK1
SYSCLKDIV1 b11-6
SYSCLKCON b3-2
PHASE
SHIFT
SYSCLKDIV2 b15, 13, 5-0
2
SYSCLK2
DIVIDER
÷1 to 64
1
0
1
0
SYSCLK2
SYSCLKDIV1 b12
SYSCLKCON b5-4
Figure 25 Digital System Clock Generation Schemes
See:
9.2.3 Program Block 1 – Clock Control.
7.6
Signal Level Optimisation
The internal signal processing of the CMX7861 will operate with wide dynamic range and low distortion
only if the signal level at all stages in the signal processing chain is kept within the recommended limits.
For a device working from a 3.3V supply, the signal range which can be accommodated without distortion
is specified in 8.1.3 Operating Characteristics. Signal gain and dc offset can be manipulated as follows:
7.6.1
Transmit Path Levels
For the maximum signal out of Outputs1-4, the signal level at the output of the CMX7861 is set to be 0dB,
the Fine Output adjustment has a maximum attenuation of 6dB and no gain, whereas the Coarse Output
adjustment has a variable attenuation of up to 14.2dB and 6dB gain.
The signals output from DAC1 and DAC2 may be independently inverted. Inversion is achieved by
selecting a negative value for the (linear) Fine Output adjustment. When transmitting I/Q format signals
inverting one of the I/Q pair has a similar effect to swapping I with Q.
DC offsets may be added to the signal. However, care must be taken that the combination of gain and dc
offset does not cause the signal to clip at any point in the signal processing chain, which is: fine gain
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CMX7861
followed by dc offset addition, followed by coarse gain. Fine gain and dc offset addition are implemented
prior to digital to analogue conversion, coarse gain is applied after digital to analogue conversion.
See:
9.1.8 DAC1/DAC2 Output Control - $5D, $5E write
9.1.22 Output 1 and 2 Coarse Gain - $B4, $B5 write.
7.6.2
Receive Path Levels
Inputs 1 to 4 each have a variable gain of up to +22.4dB and no attenuation. With the lowest gain setting
(0dB), the maximum allowable input signal level at the Input pins is specified in section 8.1.3 Operating
Characteristics.
A fine input level adjustment is provided, although the CMX7861 should operate correctly with the default
level selected. The primary purpose of the Fine Input level adjustment is to allow independent inversion of
the sampled signals in ADC1 and 2. Inversion is achieved by selecting a negative value for the (linear)
Fine Input gain adjustment. When receiving I/Q format signals, inverting one of the I/Q pair has a similar
effect to swapping I with Q.
DC offsets can be removed by the CMX7861, the offset to remove is selected by the host. Fine gain and
dc offset addition are implemented after analogue to digital conversion, coarse gain is applied before
analogue to digital conversion.
It should be noted that if the maximum allowable signal input level is exceeded, signal distortion will occur
regardless of the internal dc offset removal or attenuation.
See:
9.1.9 ADC1/ADC2 Input Control - $5F, $60 write
9.1.19 Input 1 - 4 Configuration - $B0 write.
7.7
7.7.1
Application Information
ADC and DAC Filters
Information on how to design user-configurable filters for the CMX7861 will be the subject of a separate
application note. Contact CML Technical Support for further information.
ADC Filters
The ADC filter coefficients may be programmed using the Programming Registers (Program Block 8),
see:
9.2.10 Program Block 8 – Custom Rx Channel Filter
DAC Filters
The DAC filter coefficients may be programmed using the Programming Registers (Program Block 9),
see:
9.2.11 Program Block 9 – Custom Tx Filter
7.7.2
ADC and DAC Sample Timing Synchronisation
In applications where the timing of DAC samples has to be synchronised to signals processed on the ADC
(e.g. in a TDMA systems) it is essential to be able to measure the time of arrival of ADC samples, and to
synchronise samples output through the DAC to them. In order to achieve this the CMX7861 provides
sample synchronisation as shown in Figure 26 ADC/DAC Sample Timing Synchronisation.
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ADC/DAC
Sample
Synchroniser/Timer
ADC
1
ADC
Sample
Time
Stamp
Decimate
INPUT 2
(or Q for I/Q
based systems)
and INPUT 4
ADC
2
Filtering
Operations
Time Reg
Time Int Reg
FIFO
Registers C-BUS
INPUT 1
(or I for I/Q
based systems),
and INPUT 3
CMX7861
RSSI
Configuration and
Task Processor
OUTPUT 1 (or I for I/Q
based systems),
OUTPUT 3, OUTPUT 4
DAC
1
Interpolate
OUTPUT 2 (or Q for I/Q
based systems),
OUTPUT 3, OUTPUT 4
DAC
2
DAC
Sample
Sync
Filtering
Operations
FIFO
Figure 26 ADC/DAC Sample Timing Synchronisation
The CMX7861 will count at the selected sample rate and output the counter value in the Sample Time $7D read. When in receive each input sample will be time stamped with the sample time, the time stamp
can be optionally read using the Receive FIFO. Using this mechanism the time of arrival of a received
framesync can be determined.
Using the ‘Tx Time Block’, which is described in section 7.4.12, a transmission can be scheduled to
appear at a specified sample time. As the CMX7861 contains a single counter for input and output
samples the result is a transmission at a precise time delay from the received framesync.
The sample counter will run even when the ADCs or DACs are inactive, allowing low-power operation
without losing time synchronisation. To further save overall system power the counter can be compared
to the Sample Timer Interrupt - $65 write register by the CMX7861 and when the two are equal the
CMX7861 will interrupt the host microcontroller.
7.8
7.8.1
Codec And Modem Mode Descriptions
Codec Mode
Codec mode provides the ability to sample at rates up to 72kHz and provides a signal bandwidth of
30.96kHz with that sample rate. With this bandwidth constraint, the FirmCODEC provides ADCs and
DACs to sample or reproduce any arbitrary waveform, for example, left/right stereo or control signals.
Whilst in Codec mode the CMX7861 provides optional user-programmable filtering on the input signal,
and on the output signal. Filter design is straightforward, requiring an understanding of normal filter design
and interpolation by 2. ADC and DAC roll off can be ignored because compensation is automatic.
Limited filter choices are possible when in codec mode. When in transmit either the codec mode filter or a
user-programmable filter must be selected using Program Register P4.1. When in receive the ADC
Compensation filter must be selected using Program Register P4.1. These constraints limit the value of
Program Register P4.1 to $0102 or $0802. The receive user filter in codec mode is configured using
Program Block 10 – Custom Rx Codec Mode Filter. This filter becomes active by selecting codec mode,
and inactive when selecting modem mode.
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7.8.2
CMX7861
Modem Mode
Modem mode is intended to be used in a radio modem application where the DACs are used to produce
modulation and the ADCs to sample the received signal for reception. In both cases the number of
samples per modem symbol is often an important factor when deciding on a sample rate, rather than
simply the signal bandwidth. This often results in relatively narrow band signal when compared to the
sample rate, which can be up to 144kHz.
During transmit, filters are provided which allow production of any size QAM (4,16, 32 etc.) or PSK
(QPSK, pi/4DQPSK, pi/8D8PSK etc.). To do this the user provides mapped symbols in the form of I/Q
samples at their modem symbol rate. The FirmCODEC applies pulse shaping filters and produces the
transmit I/Q signal for up-conversion by radio hardware. In doing this it typically interpolates the signal by
a factor of 4 to 10. Various pulse-shaping filters are provided, with user-programmable filters and
interpolation rates. The same architecture provides pulse-shaping filtering for GFSK/4FSK type
modulations, where the resulting signal drives a 2-point modulation transmitter. Again the user provides
the sample at the symbol timing instant and the FirmCODEC provides pulse shaping filtering.
During receive, the FirmCODEC provides sampling and channel filtering (for an I/Q receiver) with a
sample rate of up to 144kHz. This is useful for both QAM/QPSK style modulations and FSK/GFSK type
signals. Samples and/or the phase and amplitude of received samples can be provided. Phase and
amplitude information is useful for FM demodulation which is completed by the controlling processor. In
some configurations the ADCs will provide matched filters for the modem receiver. In addition, short
bursty transmissions may be synchronised to received samples, providing TDMA support.
The use of user-programmable filters (in transmit) means that consideration needs to be given to DAC roll
off and compensation. This means that an output signal needs to have bandwidth considerably less than
0.5xFs. This is not uncommon in modem designs. In receive, consideration needs to be given to ADC roll
off and this must be compensated for over the bandwidth of the wanted input signal. For further
information, please contact CML Technical Support.
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7.9
CMX7861
C-BUS Register Summary
Table 8 C-BUS Registers
Word
Size
(bits)
User
Manual
Page
Section
C-BUS General Reset
0
65
9.1.2
W
W
W
R
R
R
R
R
W
W
W
W
R
Transmit FIFO Data Byte
Transmit FIFO Word
Transmit FIFO Control Byte
Transmit FIFO Level
Receive FIFO Data Byte
Receive FIFO Word
Receive FIFO Control Byte
Receive FIFO Level
FIFO Control
AuxADC1-4 Control
AuxADC1-4 Threshold
AuxDAC1-4 Control
AuxADC1-4 Read
8
16
8
8
8
16
8
8
16
16
16
16
16
66
66
66
78
78
78
78
79
66
67
67
68
79
9.1.3
9.1.3
9.1.3
9.1.25
9.1.26
9.1.26
9.1.26
9.1.27
9.1.4
9.1.5
9.1.6
9.1.7
9.1.29
$5D
$5E
$5F
$60
$61
$65
$69
$70
$77
W
W
W
W
W
W
W
R
R
DAC1 Output Control
DAC2 Output Control
ADC1 Input Control
ADC2 Input Control
Signal Control
Sample Timer Interrupt
Reg Done Select
Internal Buffer Fill Level
RSSI
16
16
16
16
16
16
16
16
16
68
68
69
69
70
72
73
79
79
9.1.8
9.1.8
9.1.9
9.1.9
9.1.10
9.1.14
9.1.15
9.1.28
9.1.30
$62
$63
$64
$78
$79
$7D
W
W
W
R
R
R
SPI Thru-Port Control
SPI Thru-Port Write
GPIO Control
SPI Thru-Port Read
GPIO Input
Sample Time
16
16
16
16
16
16
71
72
72
80
80
80
9.1.11
9.1.12
9.1.13
9.1.31
9.1.32
9.1.33
$6A
$6B
$6C
$7E
$7F
W
W
W
R
R
Programming
Mode
IRQ Mask
IRQ Status
Mode Readback
16
16
16
16
16
73
73
75
81
81
9.1.16
9.1.17
9.1.18
9.1.34
9.1.35
$B0
$B1
$B2
$B3
$B4
$B5
$B7
W
W
W
W
W
W
W
Input 1 to 4 Configuration
Input 1 to 4 Coarse Gain
Input 1 to 4 Coarse Gain
Output 1 to 4 Configuration
Output 1 and 2 Coarse Gain
Output 1 and 2 Coarse Gain
VBIAS Control
16
16
16
16
16
16
16
75
76
76
77
77
77
78
9.1.19
9.1.20
9.1.20
9.1.21
9.1.22
9.1.22
9.1.24
ADDR.
(hex)
Read/
Write
$01
W
$48
$49
$4A
$4B
$4C
$4D
$4E
$4F
$50
$51 to $54
$55 to $58
$59 to $5C
$71 to $74
REGISTER
All other C-BUS addresses are reserved and must not be accessed.
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CMX7861 FirmCODEC® Programmable Baseband Interface
8
CMX7861
Performance Specification
8.1
Electrical Performance
8.1.1
Absolute Maximum Ratings
Exceeding these maximum ratings can result in damage to the device.
Power Supplies
DVDD - DVSS
DVCORE - DVSS
AVDD - AVSS
Voltage on any digital pin to DVSS
Voltage on any analogue pin to AVSS
Current into or out of any pin except power supply pins:
OP4VDD and OP4VSS
Current in to or out of power supply pins: OP4VDD and
OP4VSS
Q1 Package (64-pin VQFN)
Total Allowable Power Dissipation at Tamb = 25ºC
... Derating
Storage Temperature
Operating Temperature
8.1.2
Min.
Max.
Units
-0.3
-0.3
-0.3
-0.3
-0.3
4.0
2.16
4.0
DVDD + 0.3
AVDD + 0.3
V
V
V
V
V
-20
+20
mA
-120
+120
mA
Min.
Max.
3500
35.0
+125
+85
Units
mW
mW/ºC
ºC
ºC
-55
-40
Operating Limits
Correct operation of the device outside these limits is not implied.
Min
3.0
1.7
3.0
3.0
-40
3.0
3.0
DVDD - DVSS
DVCORE - DVSS
AVDD - AVSS
OP4VDD – OP4Vss
Operating Temperature
Xtal Frequency
External Clock Frequency
2011 CML Microsystems Plc
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Typ
3.3
1.8
3.3
3.3
–
–
–
Max.
3.6
1.9
3.6
3.6
+85
12.288
24.576
Units
V
V
V
V
°C
MHz
MHz
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CMX7861 FirmCODEC® Programmable Baseband Interface
8.1.3
CMX7861
Operating Characteristics
For the following conditions unless otherwise specified:
External components as recommended in Section 5, External Components.
Maximum load on digital outputs = 30pF.
Xtal Frequency = 9.6MHz 0.002% (20ppm); Tamb = 40°C to +85°C.
AVDD = DVDD = 3.0V to 3.6V.
DC Parameters
Notes
Supply Current
All Powersaved
AIDD + DIDD
Idle Mode
DIDD
AIDD
Additional Current for One Auxiliary
System Clock (output running at 5MHz –
SysCLKPLL active)
DIDD (DVDD = 3.3V, DVCORE = 1.8V)
Additional Current for one Auxiliary
System Clock (output running at 4.8MHz –
SysCLKPLL not required)
DIDD (DVDD = 3.3V, DVCORE = 1.8V)
Additional Current for Each Auxiliary ADC
DIDD (DVDD = 3.3V, DVCORE = 1.8V)
Additional Current for Each Auxiliary DAC
AIDD (AVDD = 3.3V)
Notes:
1
2
3
4
5
Min.
Typ.
Max.
Unit
–
1.0
–
µA
–
–
550
17
–
–
µA
µA
–
900
–
µA
–
675
–
µA
–
190
–
µA
–
210 to 370
–
µA
2
1
3
4
5
Idle mode with VBIAS disabled.
Tamb = 25°C, not including any current drawn from the device pins by external circuitry.
System Clocks, Auxiliary circuits disabled, but all other digital circuits (including the
Main Clock PLL) enabled and VBIAS enabled.
Using external clock input, Xtal oscillator circuit powered down.
A lower current is measured when outputting the smallest possible dc level from an
Auxiliary DAC, a higher current is measured when outputting the largest possible dc
value.
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CMX7861 FirmCODEC® Programmable Baseband Interface
DC Parameters (continued)
XTAL/CLK
Input Logic ‘1’
Input Logic ‘0’
Input Current (Vin = DVDD)
Input Current (Vin = DVSS)
CMX7861
Notes
2
C-BUS Interface and Logic Outputs
Output Logic ‘1’ (IOH = 2mA)
Output Logic ‘0’ (IOL = -5mA)
“Off” State Leakage Current
Notes:
20
21
Typ.
Max.
Unit
70%
–
–
40
–
–
–
–
–
30%
40
–
DVDD
DVDD
µA
µA
70%
–
1.0
–
–
–
–
–
–
30%
1.0
7.5
DVDD
DVDD
µA
pF
90%
–
1.0
–
–
–
–
10%
1.0
DVDD
DVDD
µA
–
–
±2%
50
–
–
AVDD
k
20
C-BUS Interface and Logic Inputs
Input Logic ‘1’
Input Logic ‘0’
Input Leakage Current (Logic ‘1’ or ‘0’)
Input Capacitance
VBIAS
Output Voltage Offset wrt AVDD/2 (IOL < 1 A)
Output Impedance
Min.
2
21
Characteristics when driving the XTAL/CLK pin with an external clock source.
Applies when utilising VBIAS to provide a reference voltage to other parts of the
system. When using VBIAS as a reference, VBIAS must be buffered. VBIAS must
always be decoupled with a capacitor, as shown in section 4.
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CMX7861 FirmCODEC® Programmable Baseband Interface
AC Parameters
CMX7861
Notes
Min.
Typ.
Max.
Unit
30
30
15
15
–
–
–
–
ns
ns
–
–
–
–
–
150
20
300
20
20
–
–
–
–
–
k
pF
k
pF
ms
SYSCLK1/2 Outputs
SysPLL Operating Frequency
SysCLK1/2 Output Frequency
Rise Time
Fall Time
38
–
–
–
–
–
–
–
250
20
13.5
6
MHz
MHz
ns
ns
VBIAS
Start-up Time (from powersave)
–
30
–
ms
31
–
–
–
–
–
10
–
144
144
–
–
140
32
–
16
–
–
86
83
–
200
–
20 to 80
bits
ksps
ksps
dB
dB
k
k
%AVDD
31
32
–
–
>10
–
–
10 to 90
M
%AVDD
–
–
80
1.0
–
–
dB
M
33
0.5
0
+0.5
dB
33
1.0
0
+1.0
dB
XTAL/CLK Input
'High' Pulse Width
'Low' Pulse Width
Input Impedance (at 9.6MHz)
Powered-up
Resistance
Capacitance
Powered-down
Resistance
Capacitance
Xtal Start-up Time (from powersave)
Differential Inputs 1 and 2 (I/Q Inputs)
Resolution
Sample Rate
SNR
4 kHz bandwidth
8 kHz bandwidth
Input Impedance, Enabled
Input Impedance, Muted or Powersaved
Maximum Input Voltage Excursion
Single Ended Inputs 3 and 4
Input Impedance
Input Voltage Range
Amplifier Open Loop Voltage Gain
(I/P = 1mV rms at 100Hz)
Unity Gain Bandwidth
Programmable Input Gain Stage
Gain (at 0dB)
Cumulative Gain Error
(w.r.t. attenuation at 0dB)
Notes:
30
31
32
33
Timing for an external input to the XTAL/CLK pin.
With no external components connected.
For each input pin and for AVDD = 3.3V, the maximum allowed signal swing is:
(3.3 x 0.8) - (3.3 x 0.2) = 2.0V.
Design Value. Overall attenuation input to output has a design tolerance of 0dB
±1.0dB.
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CMX7861 FirmCODEC® Programmable Baseband Interface
AC Parameters
Differential Outputs 1 and 2 (I/Q Outputs),
Outputs 3 and 4
Power-up to Output Stable
SINAD (3.4 kHz bandwidth)
Output Voltage Range: Outputs 1 and 2
Output voltage Range: Output 3
Output Voltage Range: Output 4
Output Power: Output 3
Load Resistance:
Outputs 1 and 2
Output 3
Output 4
Output Impedance: Output 1 and 2
CMX7861
Notes
Min.
Typ.
Max.
Unit
40
41, 44
45
44, 46
47
–
–
0.3
0.5
0.75
–
50
78
–
–
–
–
100
–
AVDD - 0.3
AVDD - 0.5
AVDD - 0.75
140
µs
dB
V
V
V
mW
42
42
42
42
20
32
8
–
–
–
–
600
–
–
–
–
0.2
0
+0.2
dB
0.6
0
+0.6
dB
0.5
0
+0.5
dB
1.0
0
1.0
dB
Output 1 and 2, Course Gain Attenuators
Attenuation (at 0dB)
Cumulative Attenuation Error
(w.r.t. attenuation at 0dB)
43
Output 3 and 4, Course Gain Attenuators
Attenuation (at 0dB)
Cumulative Attenuation Error
(w.r.t. attenuation at 0dB)
43
Notes:
40
41
42
43
44
45
46
47
k
Power-up refers to issuing a C-BUS command to turn on an output. These limits
apply only if VBIAS is on and stable. At power supply switch-on, the default state is
for all blocks, except the XTAL and C-BUS interface, to be in placed in powersave
mode.
For each output pin. With respect to the output driving a 20k load to AVDD/2.
Small signal impedance, at AVDD = 3.3V and Tamb = 25°C.
Figures relate to attenuator block only. Design Value. Overall attenuation input to
output has a design tolerance of 0dB ±1.0dB.
The levels of I/Q Output Fine Gain and Offset (registers $5D and $5E) should be
adjusted so that the output voltage remains between 20% and 80% of AV DD on
each output pin (when 0dB of coarse output gain is used). This will produce the
best performance when the device operates with AVDD = 3.3V.
With respect to the output driving a 32 load to AVDD/2.
With respect to the outputs driving a differential load of 8 .
Differential power output into an 8 load at AVDD =3.0V.
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CMX7861 FirmCODEC® Programmable Baseband Interface
AC Parameters (cont.)
Auxiliary Signal Inputs (AuxADC1-4)
Source Output Impedance
Auxiliary 10-Bit ADC
Resolution
Conversion Time
Sample Rate
Input Impedance
Resistance
Capacitance
Offset Error
Integral Non-linearity
Differential Non-linearity
Auxiliary 10-Bit DACs
Resolution
Conversion Time
Settling Time to 0.5 LSB
Offset Error
Resistive Load
Integral Non-linearity
Differential Non-linearity
Notes:
50
51
52
53
54
8.1.4
CMX7861
Notes
Min.
Typ.
Max.
50
–
–
24
k
51
–
–
1
10
225
–
–
–
512
Bits
µs
Hz
–
–
–
–
–
TBD
5
–
–
–
–
–
±18
±2
±1
M
pF
mV
LSBs
LSBs
–
–
–
–
5
–
–
10
60
10
–
–
–
–
–
–
–
±20
–
±4
±1
Bits
µs
µs
mV
k
LSBs
LSBs
53, 54
53, 54
52, 53
51
53, 54
53, 54
52, 53
Unit
Denotes output impedance of the driver of the auxiliary input signal, to ensure
<1 bit additional error under nominal conditions.
Typical – based on 9.6MHz Xtal or external oscillator.
Guaranteed monotonic with no missing codes.
Specified between 2.5% and 97.5% of the full-scale range.
Calculated from the line of best fit of all the measured codes.
Performance Characteristics
For the following conditions unless otherwise specified:
External components as recommended in section 5.
Maximum load on digital outputs = 30pF.
Xtal Frequency = 9.6MHz 0.002% (20ppm); Tamb = 40°C to +85°C.
AVDD = DVDD = 3.0V to 3.6V.
Input stage gain = 0dB, Output stage attenuation = 0dB.
DC Parameters
Supply Current
Rx Mode
DIDD (96,000samples/s )
AIDD (AVDD = 3.3V)
Tx Mode
DIDD (96,000samples/s )
AIDD (AVDD = 3.3V)
Notes:
60
61
Notes
Min.
Typ.
Max.
Unit
60
60
–
–
TBD
7.7
–
–
mA
mA
61
61
–
–
TBD
8.0
–
–
mA
mA
Two signal ADC at specified sample rate, all auxiliary functions powersaved.
Two signal DAC at specified sample rate, all auxiliary functions powersaved.
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CMX7861 FirmCODEC® Programmable Baseband Interface
8.2
CMX7861
C-BUS Timing
Figure 29 C-BUS Timing
C-BUS Timing
tCSE
CSN Enable to SCLK high time
tCSH
Last SCLK high to CSN high time
tLOZ
SCLK low to RDATA output enable Time
tHIZ
CSN high to RDATA high impedance
tCSOFF
CSN high time between transactions
tNXT
Inter-byte time
tCK
SCLK cycle time
tCH
SCLK high time
tCL
SCLK low time
tCDS
CDATA set-up time
tCDH
CDATA hold time
tRDS
RDATA set-up time
tRDH
RDATA hold time
Notes:
Notes
Min.
100
100
0.0
–
1.0
100
100
50
50
75
25
50
0
Typ.
–
–
–
–
–
–
–
–
–
–
–
–
–
Max.
–
–
–
1.0
–
–
–
–
–
–
–
–
–
Unit
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
1. Depending on the command, 1 or 2 bytes of CDATA are transmitted to the peripheral MSB
(Bit 7) first, LSB (Bit 0) last. RDATA is read from the peripheral MSB (Bit 7) first, LSB (Bit 0)
last.
2. Data is clocked into the peripheral on the rising SCLK edge.
3. Commands are acted upon between the last rising edge of SCLK of each command and the
rising edge of the CSN signal.
4. To allow for differing µC serial interface formats C-BUS compatible ICs are able to work
with SCLK pulses starting and ending at either polarity.
5. Maximum 30pF load on IRQN pin and each C-BUS interface line.
These timings are for the latest version of C-BUS and allow faster transfers than the original C-BUS timing
specification. The CMX7861 can be used in conjunction with devices that comply with the slower timings,
subject to system throughput constraints.
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CMX7861 FirmCODEC® Programmable Baseband Interface
8.3
CMX7861
Packaging
Figure 27 Mechanical Outline of 64-pin VQFN (Q1)
Order as part no. CMX7861Q1
As package dimensions may change after publication of this datasheet, it is recommended that you check
for the latest packaging information from the Design Support/Package Information page of the CML
website: [www.cmlmicro.com].
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CMX7861 FirmCODEC® Programmable Baseband Interface
CMX7861
About FirmASIC
CML’s proprietary FirmASIC component technology reduces cost, time to market and development risk,
with increased flexibility for the designer and end application. FirmASIC combines Analogue, Digital,
Firmware and Memory technologies in a single silicon platform that can be focused to deliver the right
feature mix, performance and price for a target application family. Specific functions of a FirmASIC
device are determined by uploading its Function Image™ during device initialisation.
New
Function Images™ may be later provided to supplement and enhance device functions, expanding or
modifying end-product features without the need for expensive and time-consuming design changes.
FirmASIC devices provide significant time to market and commercial benefits over Custom ASIC,
Structured ASIC, FPGA and DSP solutions. They may also be exclusively customised where security or
intellectual property issues prevent the use of Application Specific Standard Products (ASSP’s).
Handling precautions: This product includes input protection, however, precautions should be taken to prevent device damage
from electro-static discharge. CML does not assume any responsibility for the use of any circuitry described. No IPR or circuit
patent licences are implied. CML reserves the right at any time without notice to change the said circuitry and this product
specification. CML has a policy of testing every product shipped using calibrated test equipment to ensure compliance with this
product specification. Specific testing of all circuit parameters is not necessarily performed.
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