74AVC32T245 32-bit dual supply translating transceiver with configurable voltage translation; 3-state Rev. 1 — 16 January 2013 Product data sheet 1. General description The 74AVC32T245 is a 32-bit transceiver with bidirectional level voltage translation and 3-state outputs. The device can be used as eight 8-bit input-output ports (nAn and nBn), two 16-bit transceiver or as a 32-bit transceiver. It has dual supplies (VCC(A) and VCC(B)) for voltage translation and four 8-bit input-output ports (nAn and nBn) each with its own output enable (nOE) and send/receive (nDIR) input for direction control. VCC(A) and VCC(B) can be independently supplied at any voltage between 0.8 V and 3.6 V making the device suitable for low voltage translation between any of the following voltages: 0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V. A HIGH on nDIR selects transmission from nAn to nBn while a LOW on nDIR selects transmission from nBn to nAn. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both nAn and nBn are in the high-impedance OFF-state. 2. Features and benefits Wide supply voltage range: VCC(A): 0.8 V to 3.6 V VCC(B): 0.8 V to 3.6 V Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F Class 3B exceeds 8000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101D exceeds 1000 V Maximum data rates: 380 Mbit/s ( 1.8 V to 3.3 V translation) 200 Mbit/s ( 1.1 V to 3.3 V translation) 200 Mbit/s ( 1.1 V to 2.5 V translation) 200 Mbit/s ( 1.1 V to 1.8 V translation) 150 Mbit/s ( 1.1 V to 1.5 V translation) 74AVC32T245 NXP Semiconductors 32-bit dual supply translating transceiver; 3-state 100 Mbit/s ( 1.1 V to 1.2 V translation) Suspend mode Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V IOFF circuitry provides partial Power-down mode operation Multiple package options Specified from 40 C to +85 C and 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package 74AVC32T245EC Temperature range Name Description Version 40 C to +125 C plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 5.5 1.05 mm SOT536-1 LFBGA96 4. Functional diagram ',5 ',5 2( $ 2( $ % 9&&$ % 9&&% 9&&$ WRRWKHUVHYHQFKDQQHOV 9&&% WRRWKHUVHYHQFKDQQHOV ',5 ',5 2( $ 2( $ % 9&&$ 9&&% % 9&&$ WRRWKHUVHYHQFKDQQHOV 9&&% WRRWKHUVHYHQFKDQQHOV DDD Fig 1. Logic diagram 74AVC32T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 January 2013 © NXP B.V. 2013. All rights reserved. 2 of 24 74AVC32T245 NXP Semiconductors 32-bit dual supply translating transceiver; 3-state $ ',5 + 2( $ $ ( ( ) % % $ & * % & * ' + % ' - $ % - - . . / / 0 0 ' + 7 $ % $ % $ % $ % $ % $ % $ % $ % % % 1 - 1 - 3 . 3 . 5 / 5 / 7 0 7 ) * $ % * $ % $ % + + ',5 2( - ) $ ' ',5 2( % $ & $ ( $ & $ % % % $ ( $ % ) % % $ $ + $ $ $ % % 2( $ $ % ',5 $ % $ % $ % $ % $ % $ % $ % $ 0 % 7 1 1 3 3 5 5 7 7 DDD Fig 2. Logic symbol 74AVC32T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 January 2013 © NXP B.V. 2013. All rights reserved. 3 of 24 74AVC32T245 NXP Semiconductors 32-bit dual supply translating transceiver; 3-state 5. Pinning information 5.1 Pinning EDOO$ LQGH[DUHD $9&7 $ % & ' ( ) * + . / 0 1 3 5 7 DDD 7UDQVSDUHQWWRSYLHZ Fig 3. Pin configuration SOT536-1 (LFBGA96) 5.2 Pin description Table 2. Pin description Symbol Ball Description 1DIR, 2DIR, 3DIR, 4DIR A3, H3, J3, T3 direction control 1OE, 2OE, 3OE, 4OE A4, H4, J4, T4 output enable input (active LOW) 1A1 to 1A8 A5, A6, B5, B6, C5, C6, D5, D6 input or output 1B1 to 1B8 A2, A1, B2, B1, C2, C1, D2, D1 input or output 2A1 to 2A8 E5, E6, F5, F6, G5, G6, H6, H5 input or output 2B1 to 2B8 E2, E1, F2, F1, G2, G1, H1, H2 input or output 3A1 to 3A8 J5, J6, K5, K6, L5, L6, M5, M6 input or output 3B1 to 3B8 J2, J1, K2, K1, L2, L1, M2, M1 input or output 4A1 to 4A8 N5, N6, P5, P6, R5, R6, T6, T5 input or output 4B1 to 4B8 N2, N1, P2, P1, R2, R1, T1, T2 input or output GND[1] B3, B4, D3, D4, E3, E4, G3, G4, ground (0 V) K3, K4, M3, M4, N3, N4, R3, R4 VCC(A) C4, F4, L4, P4 supply voltage A (nAn, nOE and nDIR inputs are referenced to VCC(A)) VCC(B) C3, F3, L3, P3 supply voltage B (nBn inputs are referenced to VCC(B)) [1] All GND pins must be connected to ground (0 V). 74AVC32T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 January 2013 © NXP B.V. 2013. All rights reserved. 4 of 24 74AVC32T245 NXP Semiconductors 32-bit dual supply translating transceiver; 3-state 6. Functional description Table 3. Function table[1] Input/output[3] Supply voltage Input VCC(A), VCC(B) nOE[2] nDIR[2] nAn[2] nBn[2] 0.8 V to 3.6 V L L nAn = nBn input 0.8 V to 3.6 V L H input nBn = nAn 0.8 V to 3.6 V H X Z Z GND[3] X X Z Z [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. [2] The nAn, nDIR and nOE input circuit is referenced to VCC(A); The nBn input circuit is referenced to VCC(B). [3] If at least one of VCC(A) or VCC(B) is at GND level, the device goes into suspend mode. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC(A) supply voltage A 0.5 +4.6 V VCC(B) supply voltage B 0.5 +4.6 V IIK input clamping current 50 - mA [1] 0.5 +4.6 V 50 - mA [1][2][3] 0.5 VCCO + 0.5 V Suspend or 3-state mode [1] 0.5 +4.6 V VO = 0 V to VCCO [2] - 50 mA VI < 0 V VI input voltage IOK output clamping current VO < 0 V VO output voltage Active mode IO output current ICC supply current per VCC(A) or VCC(B) pin - 100 mA IGND ground current per GND pin 100 - mA Tstg storage temperature 65 +150 C Ptot total power dissipation - 1000 mW Tamb = 40 C to +125 C LFBGA96 package [4] [1] The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] VCCO is the supply voltage associated with the output port. [3] VCCO + 0.5 V should not exceed 4.6 V. [4] Above 70 C the value of Ptot derates linearly with 1.8 mW/K. 74AVC32T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 January 2013 © NXP B.V. 2013. All rights reserved. 5 of 24 74AVC32T245 NXP Semiconductors 32-bit dual supply translating transceiver; 3-state 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VCC(A) Conditions Min Max Unit supply voltage A 0.8 3.6 V VCC(B) supply voltage B 0.8 3.6 V VI input voltage 0 3.6 V VO output voltage 0 VCCO V 0 3.6 V 40 +125 C - 5 ns/V Active mode [1] Suspend or 3-state mode Tamb t/V ambient temperature input transition rise and fall rate VCCI = 0.8 V to 3.6 V [1] VCCO is the supply voltage associated with the output port. [2] VCCI is the supply voltage associated with the input port. [2] 9. Static characteristics Table 6. Typical static characteristics at Tamb = 25 C[1][2] At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VOH HIGH-level output voltage Conditions LOW-level output voltage Typ Max Unit - 0.69 - V - 0.07 - V - 0.025 0.25 A VI = VIH or VIL IO = 1.5 mA; VCC(A) = VCC(B) = 0.8 V VOL Min VI = VIH or VIL IO = 1.5 mA; VCC(A) = VCC(B) = 0.8 V II input leakage current nDIR, nOE input; VI = 0 V or 3.6 V; VCC(A) = VCC(B) = 0.8 V to 3.6 V IOZ OFF-state output current A or B port; VO = 0 V or VCCO; VCC(A) = VCC(B) = 3.6 V [3] - 0.5 2.5 A suspend mode A port; VO = 0 V or VCCO; VCC(A) = 3.6 V; VCC(B) = 0 V [3] - 0.5 2.5 A suspend mode B port; VO = 0 V or VCCO; VCC(A) = 0 V; VCC(B) = 3.6 V [3] - 0.5 2.5 A A port; VI or VO = 0 V to 3.6 V; VCC(A) = 0 V; VCC(B) = 0.8 V to 3.6 V - 0.1 1 A B port; VI or VO = 0 V to 3.6 V; VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V - 0.1 1 A IOFF power-off leakage current CI input capacitance nDIR, nOE input; VI = 0 V or 3.3 V; VCC(A) = VCC(B) = 3.3 V - 2.0 - pF CI/O input/output capacitance A and B port; VO = 3.3 V or 0 V; VCC(A) = VCC(B) = 3.3 V - 4.5 - pF [1] VCCO is the supply voltage associated with the output port. [2] VCCI is the supply voltage associated with the data input port. [3] For I/O ports, the parameter IOZ includes the input leakage current. 74AVC32T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 January 2013 © NXP B.V. 2013. All rights reserved. 6 of 24 74AVC32T245 NXP Semiconductors 32-bit dual supply translating transceiver; 3-state Table 7. Static characteristics [1][2] At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH HIGH-level input voltage 40 C to +85 C Conditions 40 C to +125 C Unit Min Max Min Max VCCI = 0.8 V 0.70VCCI - 0.70VCCI - V VCCI = 1.1 V to 1.95 V 0.65VCCI - 0.65VCCI - V VCCI = 2.3 V to 2.7 V 1.6 - 1.6 - V VCCI = 3.0 V to 3.6 V 2 - 2 - V VCC(A) = 0.8 V 0.70VCC(A) - 0.70VCC(A) - V VCC(A) = 1.1 V to 1.95 V 0.65VCC(A) - 0.65VCC(A) - V VCC(A) = 2.3 V to 2.7 V 1.6 - 1.6 - V VCC(A) = 3.0 V to 3.6 V 2 - 2 - V data input nDIR, nOE input VIL LOW-level input voltage data input VCCI = 0.8 V - 0.30VCCI - 0.30VCCI V VCCI = 1.1 V to 1.95 V - 0.35VCCI - 0.35VCCI V VCCI = 2.3 V to 2.7 V - 0.7 - 0.7 V VCCI = 3.0 V to 3.6 V - 0.8 - 0.8 V VCC(A) = 0.8 V - 0.30VCC(A) - 0.30VCC(A) V VCC(A) = 1.1 V to 1.95 V - 0.35VCC(A) - 0.35VCC(A) V VCC(A) = 2.3 V to 2.7 V - 0.7 - 0.7 V VCC(A) = 3.0 V to 3.6 V - 0.8 - 0.8 V VCCO 0.1 - VCCO 0.1 - V IO = 3 mA; VCC(A) = VCC(B) = 1.1 V 0.85 - 0.85 - V IO = 6 mA; VCC(A) = VCC(B) = 1.4 V 1.05 - 1.05 - V IO = 8 mA; VCC(A) = VCC(B) = 1.65 V 1.2 - 1.2 - V IO = 9 mA; VCC(A) = VCC(B) = 2.3 V 1.75 - 1.75 - V IO = 12 mA; VCC(A) = VCC(B) = 3.0 V 2.3 - 2.3 - V nDIR, nOE input VOH HIGH-level VI = VIH or VIL output voltage IO = 100 A; VCC(A) = VCC(B) = 0.8 V to 3.6 V 74AVC32T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 January 2013 © NXP B.V. 2013. All rights reserved. 7 of 24 74AVC32T245 NXP Semiconductors 32-bit dual supply translating transceiver; 3-state Table 7. Static characteristics …continued[1][2] At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VOL 40 C to +85 C Conditions 40 C to +125 C Unit Min Max Min Max - 0.1 - 0.1 V IO = 3 mA; VCC(A) = VCC(B) = 1.1 V - 0.25 - 0.25 V IO = 6 mA; VCC(A) = VCC(B) = 1.4 V - 0.35 - 0.35 V IO = 8 mA; VCC(A) = VCC(B) = 1.65 V - 0.45 - 0.45 V IO = 9 mA; VCC(A) = VCC(B) = 2.3 V - 0.55 - 0.55 V IO = 12 mA; VCC(A) = VCC(B) = 3.0 V - 0.7 - 0.7 V - 1 - 5 A LOW-level VI = VIH or VIL output voltage IO = 100 A; VCC(A) = VCC(B) = 0.8 V to 3.6 V II input leakage current nDIR, nOE input; VI = 0 V or 3.6 V; VCC(A) = VCC(B) = 0.8 V to 3.6 V IOZ OFF-state output current A or B port; VO = 0 V or VCCO; VCC(A) = VCC(B) = 3.6 V [3] - 5 - 30 A suspend mode A port; VO = 0 V or VCCO; VCC(A) = 3.6 V; VCC(B) = 0 V [3] - 5 - 30 A suspend mode B port; VO = 0 V or VCCO; VCC(A) = 0 V; VCC(B) = 3.6 V [3] - 5 - 30 A A port; VI or VO = 0 V to 3.6 V; VCC(A) = 0 V; VCC(B) = 0.8 V to 3.6 V - 5 - 30 A B port; VI or VO = 0 V to 3.6 V; VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V - 5 - 30 A IOFF power-off leakage current 74AVC32T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 January 2013 © NXP B.V. 2013. All rights reserved. 8 of 24 74AVC32T245 NXP Semiconductors 32-bit dual supply translating transceiver; 3-state Table 7. Static characteristics …continued[1][2] At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter ICC 40 C to +85 C Conditions 40 C to +125 C Unit Min Max Min Max VCC(A) = 0.8 V to 3.6 V; VCC(B) = 0.8 V to 3.6 V - 60 - 250 A VCC(A) = 1.1 V to 3.6 V; VCC(B) = 1.1 V to 3.6 V - 50 - 200 A VCC(A) = 3.6 V; VCC(B) = 0 V - 50 - 200 A VCC(A) = 0 V; VCC(B) = 3.6 V 10 - 40 - A VCC(A) = 0.8 V to 3.6 V; VCC(B) = 0.8 V to 3.6 V - 60 - 250 A VCC(A) = 1.1 V to 3.6 V; VCC(B) = 1.1 V to 3.6 V - 50 - 200 A VCC(A) = 3.6 V; VCC(B) = 0 V 10 - 40 - A VCC(A) = 0 V; VCC(B) = 3.6 V supply current A port; VI = 0 V or VCCI; IO = 0 A B port; VI = 0 V or VCCI; IO = 0 A - 50 - 200 A A plus B port (ICC(A) + ICC(B)); IO = 0 A; VI = 0 V or VCCI; VCC(A) = 0.8 V to 3.6 V; VCC(B) = 0.8 V to 3.6 V - 110 - 370 A A plus B port (ICC(A) + ICC(B)); IO = 0 A; VI = 0 V or VCCI; VCC(A) = 1.1 V to 3.6 V; VCC(B) = 1.1 V to 3.6 V - 90 - 300 A [1] VCCO is the supply voltage associated with the output port. [2] VCCI is the supply voltage associated with the data input port. [3] For I/O ports, the parameter IOZ includes the input leakage current. Table 8. VCC(A) Typical total supply current (ICC(A) + ICC(B)) VCC(B) Unit 0V 0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 0V 0 0.2 0.2 0.2 0.2 0.2 0.2 A 0.8 V 0.2 0.2 0.2 0.2 0.2 0.6 3.2 A 1.2 V 0.2 0.2 0.2 0.2 0.2 0.2 1.6 A 1.5 V 0.2 0.2 0.2 0.2 0.2 0.2 0.8 A 1.8 V 0.2 0.2 0.2 0.2 0.2 0.2 0.4 A 2.5 V 0.2 0.6 0.2 0.2 0.2 0.2 0.2 A 3.3 V 0.2 3.2 1.6 0.8 0.4 0.2 0.2 A 74AVC32T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 January 2013 © NXP B.V. 2013. All rights reserved. 9 of 24 74AVC32T245 NXP Semiconductors 32-bit dual supply translating transceiver; 3-state 10. Dynamic characteristics Table 9. Typical power dissipation capacitance at VCC(A) = VCC(B) and Tamb = 25 C [1][2] Voltages are referenced to GND (ground = 0 V). Symbol Parameter power dissipation capacitance CPD [1] Conditions VCC(A) = VCC(B) Unit 0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V A port: (direction nAn to nBn); output enabled 0.2 0.2 0.2 0.2 0.3 0.4 pF A port: (direction nAn to nBn); output disabled 0.2 0.2 0.2 0.2 0.3 0.4 pF A port: (direction nBn to nAn); output enabled 9 9.7 9.8 10.3 11.7 13.7 pF A port: (direction nBn to nAn); output disabled 0.6 0.6 0.6 0.7 0.7 0.7 pF B port: (direction nAn to nBn); output enabled 9 9.7 9.8 10.3 11.7 13.7 pF B port: (direction nAn to nBn); output disabled 0.6 0.6 0.6 0.7 0.7 0.7 pF B port: (direction nBn to nAn); output enabled 0.2 0.2 0.2 0.2 0.3 0.4 pF B port: (direction nBn to nAn); output disabled 0.2 0.2 0.2 0.2 0.3 0.4 pF CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL VCC2 fo) = sum of the outputs. [2] fi = 10 MHz; VI = GND to VCC; tr = tf = 1 ns; CL = 0 pF; RL = . 74AVC32T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 January 2013 © NXP B.V. 2013. All rights reserved. 10 of 24 74AVC32T245 NXP Semiconductors 32-bit dual supply translating transceiver; 3-state Table 10. Typical dynamic characteristics at VCC(A) = 0.8 V and Tamb = 25 C [1] Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 6; for wave forms see Figure 4 and Figure 5 Symbol Parameter tpd VCC(B) Unit 0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V propagation delay nAn to nBn 14.4 7.0 6.2 6.0 5.9 6.0 ns nBn to nAn 14.4 12.4 12.1 11.9 11.8 11.8 ns nOE to nAn 16.2 16.2 16.2 16.2 16.2 16.2 ns tdis disable time ten enable time [1] Conditions nOE to nBn 17.6 10.0 9.0 9.1 8.7 9.3 ns nOE to nAn 21.9 21.9 21.9 21.9 21.9 21.9 ns nOE to nBn 22.2 11.1 9.8 9.4 9.4 9.6 ns tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. Table 11. Typical dynamic characteristics at VCC(B) = 0.8 V and Tamb = 25 C [1] Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 6; for wave forms see Figure 4 and Figure 5 Symbol Parameter tpd VCC(A) Unit 0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V propagation delay nAn to nBn 14.4 12.4 12.1 11.9 11.8 11.8 ns nBn to nAn 14.4 7.0 6.2 6.0 5.9 6.0 ns nOE to nAn 16.2 5.9 4.4 4.2 3.1 3.5 ns nOE to nBn 17.6 14.2 13.7 13.6 13.3 13.1 ns nOE to nAn 21.9 6.4 4.4 3.5 2.6 2.3 ns nOE to nBn 22.2 17.7 17.2 17.0 16.8 16.7 ns tdis disable time ten enable time [1] Conditions tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. 74AVC32T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 January 2013 © NXP B.V. 2013. All rights reserved. 11 of 24 74AVC32T245 NXP Semiconductors 32-bit dual supply translating transceiver; 3-state Table 12. Dynamic characteristics for temperature range 40 C to +85 C [1] Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 6; for wave forms see Figure 4 and Figure 5. Symbol Parameter Conditions VCC(B) Unit 1.2 V 0.1 V 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V Min Max Min Max Min Max Min Max Min Max 9.2 0.5 6.9 0.5 6.0 0.5 5.1 0.5 4.9 ns VCC(A) = 1.1 V to 1.3 V tpd propagation delay nAn to nBn 0.5 nBn to nAn 0.5 9.2 0.5 8.7 0.5 8.5 0.5 8.2 0.5 8.0 ns tdis disable time nOE to nAn 1.5 11.6 1.5 11.6 1.5 11.6 1.5 11.6 1.5 11.6 ns nOE to nBn 1.5 12.5 1.5 9.7 1.5 9.5 1.0 8.1 1.0 8.9 ns nOE to nAn 1.0 14.5 1.0 14.5 1.0 14.5 1.0 14.5 1.0 14.5 ns nOE to nBn 1.1 14.9 1.1 11.0 1.1 9.6 1.0 8.1 1.0 7.7 ns propagation delay nAn to nBn 0.5 8.7 0.5 6.2 0.5 5.2 0.5 4.1 0.5 3.7 ns nBn to nAn 0.5 6.9 0.5 6.2 0.5 5.9 0.5 5.6 0.5 5.5 ns disable time nOE to nAn 1.5 9.1 1.5 9.1 1.5 9.1 1.5 9.1 1.5 9.1 ns nOE to nBn 1.5 11.4 1.5 8.7 1.5 7.5 1.0 6.5 1.0 6.3 ns nOE to nAn 1.0 10.1 1.0 10.1 1.0 10.1 1.0 10.1 1.0 10.1 ns nOE to nBn 1.0 13.5 1.0 10.1 0.5 8.1 0.5 5.9 0.5 5.2 ns enable time ten VCC(A) = 1.4 V to 1.6 V tpd tdis enable time ten VCC(A) = 1.65 V to 1.95 V propagation delay nAn to nBn 0.5 8.5 0.5 5.9 0.5 4.8 0.5 3.7 0.5 3.3 ns nBn to nAn 0.5 6.0 0.5 5.2 0.5 4.8 0.5 4.5 0.5 4.4 ns tdis disable time nOE to nAn 1.5 7.7 1.5 7.7 1.5 7.7 1.5 7.7 1.5 7.7 ns nOE to nBn 1.5 11.1 1.5 8.4 1.5 7.1 1.0 5.9 1.0 5.7 ns ten enable time nOE to nAn 1.0 7.8 1.0 7.8 1.0 7.8 1.0 7.8 1.0 7.8 ns nOE to nBn 1.0 13.0 1.0 9.2 0.5 7.4 0.5 5.3 0.5 4.5 ns propagation delay nAn to nBn 0.5 8.2 0.5 5.6 0.5 4.6 0.5 3.3 0.5 2.8 ns nBn to nAn 0.5 5.1 0.5 4.1 0.5 3.7 0.5 3.4 0.5 3.2 ns disable time nOE to nAn 1.0 6.1 1.0 6.1 1.0 6.1 1.0 6.1 1.0 6.1 ns nOE to nBn 1.0 10.6 1.0 7.9 1.0 6.6 1.0 6.1 1.0 5.2 ns tpd VCC(A) = 2.3 V to 2.7 V tpd tdis enable time ten nOE to nAn 0.5 5.3 0.5 5.3 0.5 5.3 0.5 5.3 0.5 5.3 ns nOE to nBn 0.5 12.5 0.5 9.4 0.5 7.3 0.5 5.1 0.5 4.5 ns 0.5 8.0 0.5 5.5 0.5 4.4 0.5 3.2 0.5 2.7 ns VCC(A) = 3.0 V to 3.6 V tpd propagation delay nAn to nBn nBn to nAn 0.5 4.9 0.5 3.7 0.5 3.3 0.5 2.9 0.5 2.7 ns tdis disable time nOE to nAn 0.5 5.0 0.5 5.0 0.5 5.0 0.5 5.0 0.5 5.0 ns nOE to nBn 1.0 10.3 1.0 7.7 1.0 6.5 1.0 5.2 0.5 5.0 ns nOE to nAn 0.5 4.3 0.5 4.3 0.5 4.2 0.5 4.1 0.5 4.0 ns nOE to nBn 0.5 12.4 0.5 9.3 0.5 7.2 0.5 4.9 0.5 4.0 ns enable time ten [1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. 74AVC32T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 January 2013 © NXP B.V. 2013. All rights reserved. 12 of 24 74AVC32T245 NXP Semiconductors 32-bit dual supply translating transceiver; 3-state Table 13. Dynamic characteristics for temperature range 40 C to +125 C [1] Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 6; for wave forms see Figure 4 and Figure 5 Symbol Parameter Conditions VCC(B) Unit 1.2 V 0.1 V 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V Min Max Min Max Min Max Min Max Min Max 0.5 10.2 0.5 7.6 0.5 6.6 0.5 5.7 0.5 5.4 ns VCC(A) = 1.1 V to 1.3 V tpd propagation delay nAn to nBn nBn to nAn 0.5 10.2 0.5 9.6 0.5 9.4 0.5 9.1 0.5 8.8 ns tdis disable time nOE to nAn 1.5 12.8 1.5 12.8 1.5 12.8 1.5 12.8 1.5 12.8 ns nOE to nBn 1.5 13.8 1.5 10.7 1.5 10.5 1.0 9.0 1.5 9.8 ns nOE to nAn 1.0 16.0 1.0 16.0 1.0 16.0 1.0 16.0 1.0 16.0 ns nOE to nBn 1.1 16.4 1.1 12.1 1.1 10.6 1.0 9.0 1.0 8.5 ns propagation delay nAn to nBn 0.5 9.6 0.5 6.9 0.5 5.8 0.5 4.6 0.5 4.1 ns nBn to nAn 0.5 7.6 0.5 6.9 0.5 6.5 0.5 6.2 0.5 6.1 ns disable time nOE to nAn 1.5 10.1 1.5 10.1 1.5 10.1 1.5 10.1 1.5 10.1 ns nOE to nBn 1.5 12.6 1.5 9.6 1.5 8.3 1.0 7.2 1.0 7.0 ns nOE to nAn 1.0 11.2 1.0 11.2 1.0 11.2 1.0 11.2 1.0 11.2 ns nOE to nBn 1.0 14.9 1.0 11.2 0.5 9.0 0.5 6.5 0.5 5.8 ns enable time ten VCC(A) = 1.4 V to 1.6 V tpd tdis enable time ten VCC(A) = 1.65 V to 1.95 V propagation delay nAn to nBn 0.5 9.4 0.5 6.5 0.5 5.3 0.5 4.1 0.5 3.7 ns nBn to nAn 0.5 6.6 0.5 5.8 0.5 5.3 0.5 5.0 0.5 4.9 ns tdis disable time nOE to nAn 1.5 8.5 1.5 8.5 1.5 8.5 1.5 8.5 1.5 8.5 ns nOE to nBn 1.5 12.3 1.5 9.3 1.5 7.9 1.0 6.5 1.0 6.3 ns ten enable time nOE to nAn 1.0 8.6 1.0 8.6 1.0 8.6 1.0 8.6 1.0 8.6 ns nOE to nBn 1.0 14.3 1.0 10.2 0.5 8.2 0.5 5.9 0.5 5.0 ns propagation delay nAn to nBn 0.5 9.1 0.5 6.2 0.5 5.1 0.5 3.7 0.5 3.1 ns nBn to nAn 0.5 5.7 0.5 4.6 0.5 4.1 0.5 3.8 0.5 3.6 ns disable time nOE to nAn 1.0 6.8 1.0 6.8 1.0 6.8 1.0 6.8 1.0 6.8 ns nOE to nBn 1.0 11.7 1.0 8.7 1.0 7.3 1.0 6.8 1.0 5.8 ns nOE to nAn 0.5 5.9 0.5 5.9 0.5 5.9 0.5 5.9 0.5 5.9 ns nOE to nBn 0.5 13.8 0.5 10.4 0.5 8.1 0.5 5.7 0.5 5.0 ns 0.5 8.8 0.5 6.1 0.5 4.9 0.5 3.6 0.5 3.0 ns tpd VCC(A) = 2.3 V to 2.7 V tpd tdis enable time ten VCC(A) = 3.0 V to 3.6 V tpd propagation delay nAn to nBn nBn to nAn 0.5 5.4 0.5 4.1 0.5 3.7 0.5 3.2 0.5 3.0 ns tdis disable time nOE to nAn 0.5 5.5 0.5 5.5 0.5 5.5 0.5 5.5 0.5 5.5 ns nOE to nBn 1.0 11.4 1.0 8.5 1.0 7.2 1.0 5.8 0.5 5.5 ns nOE to nAn 0.5 4.8 0.5 4.8 0.5 4.7 0.5 4.6 0.5 4.4 ns nOE to nBn 0.5 13.7 0.5 10.3 0.5 8.0 0.5 5.4 0.5 4.4 ns enable time ten [1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. 74AVC32T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 January 2013 © NXP B.V. 2013. All rights reserved. 13 of 24 74AVC32T245 NXP Semiconductors 32-bit dual supply translating transceiver; 3-state 11. Waveforms VI nAn, nBn input VM GND tPHL tPLH VOH VM nBn, nAn output VOL 001aak285 Measurement points are given in Table 14. VOL and VOH are typical output voltage levels that occur with the output load. Fig 4. The data input (nAn, nBn) to output (nBn, nAn) propagation delay times VI VM nOE input GND tPLZ tPZL VCCO output LOW-to-OFF OFF-to-LOW VM VX VOL tPHZ VOH tPZH VY output HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs enabled outputs disabled 001aak286 Measurement points are given in Table 14. VOL and VOH are typical output voltage levels that occur with the output load. Fig 5. Table 14. Enable and disable times Measurement points Supply voltage Input[1] Output[2] VCC(A), VCC(B) VM VM VX VY 0.8 V to 1.6 V 0.5VCCI 0.5VCCO VOL + 0.1 V VOH 0.1 V 1.65 V to 2.7 V 0.5VCCI 0.5VCCO VOL + 0.15 V VOH 0.15 V 3.0 V to 3.6 V 0.5VCCI 0.5VCCO VOL + 0.3 V VOH 0.3 V [1] VCCI is the supply voltage associated with the data input port. [2] VCCO is the supply voltage associated with the output port. 74AVC32T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 January 2013 © NXP B.V. 2013. All rights reserved. 14 of 24 74AVC32T245 NXP Semiconductors 32-bit dual supply translating transceiver; 3-state tW VI 90 % negative pulse VM VM 10 % 0V tf tr tr tf VI 90 % positive pulse VM VM 10 % 0V tW VEXT VCC VI RL VO G DUT RT RL CL 001aae331 Test data is given in Table 15. RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance. VEXT = External voltage for measuring switching times. Fig 6. Table 15. Test circuit for measuring switching times Test data Supply voltage Input VCC(A), VCC(B) VI[1] t/V[2] Load CL RL tPLH, tPHL tPZH, tPHZ tPZL, tPLZ[3] 0.8 V to 1.6 V VCCI 1.0 ns/V 15 pF 2 k open GND 2VCCO 1.65 V to 2.7 V VCCI 1.0 ns/V 15 pF 2 k open GND 2VCCO 3.0 V to 3.6 V VCCI 1.0 ns/V 15 pF 2 k open GND 2VCCO [1] VCCI is the supply voltage associated with the data input port. [2] dV/dt 1.0 V/ns [3] VCCO is the supply voltage associated with the output port. 74AVC32T245 Product data sheet VEXT All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 January 2013 © NXP B.V. 2013. All rights reserved. 15 of 24 74AVC32T245 NXP Semiconductors 32-bit dual supply translating transceiver; 3-state 12. Typical propagation delay characteristics 001aai476 24 tpd (ns) (1) (2) (3) (4) (5) (6) tpd (ns) (1) 20 001aai477 21 17 16 12 13 (2) (3) (4) (5) (6) 8 4 9 0 20 40 60 0 20 CL (pF) 40 60 CL (pF) a. Propagation delay (nAn to nBn); VCC(A) = 0.8 V b. Propagation delay (nAn to nBn); VCC(B) = 0.8 V (1) VCC(B) = 0.8 V. (1) VCC(A) = 0.8 V. (2) VCC(B) = 1.2 V. (2) VCC(A) = 1.2 V. (3) VCC(B) = 1.5 V. (3) VCC(A) = 1.5 V. (4) VCC(B) = 1.8 V. (4) VCC(A) = 1.8 V. (5) VCC(B) = 2.5 V. (5) VCC(A) = 2.5 V. (6) VCC(B) = 3.3 V. (6) VCC(A) = 3.3 V. Fig 7. Typical propagation delay versus load capacitance; Tamb = 25 C 74AVC32T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 January 2013 © NXP B.V. 2013. All rights reserved. 16 of 24 74AVC32T245 NXP Semiconductors 32-bit dual supply translating transceiver; 3-state 001aai478 7 001aai491 7 (1) tPLH (ns) tPHL (ns) (2) 5 (1) 5 (3) (2) (3) (4) (4) (5) (5) 3 3 1 1 0 20 40 60 0 20 40 CL (pF) a. LOW to HIGH propagation delay (nAn to nBn); VCC(A) = 1.2 V b. HIGH to LOW propagation delay (nAn to nBn); VCC(A) = 1.2 V 001aai479 7 60 CL (pF) 001aai480 7 (1) tPLH (ns) tPHL (ns) (1) 5 5 (2) (3) (2) (3) (4) (5) 3 (4) (5) 3 1 1 0 20 40 60 0 CL (pF) 20 40 60 CL (pF) c. LOW to HIGH propagation delay (nAn to nBn); VCC(A) = 1.5 V d. HIGH to LOW propagation delay (nAn to nBn); VCC(A) = 1.5 V (1) VCC(B) = 1.2 V. (2) VCC(B) = 1.5 V. (3) VCC(B) = 1.8 V. (4) VCC(B) = 2.5 V. (5) VCC(B) = 3.3 V. Fig 8. Typical propagation delay versus load capacitance; Tamb = 25 C 74AVC32T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 January 2013 © NXP B.V. 2013. All rights reserved. 17 of 24 74AVC32T245 NXP Semiconductors 32-bit dual supply translating transceiver; 3-state 001aai481 7 (1) tPLH (ns) 001aai482 7 tPHL (ns) 5 (1) 5 (2) (3) (2) (3) (4) 3 (4) (5) 3 (5) 1 1 0 20 40 60 0 20 40 CL (pF) a. LOW to HIGH propagation delay (nAn to nBn); VCC(A) = 1.8 V b. HIGH to LOW propagation delay (nAn to nBn); VCC(A) = 1.8 V 001aai483 7 tPLH (ns) 60 CL (pF) 001aai486 7 tPHL (ns) (1) 5 (1) 5 (2) (2) (3) (3) (4) 3 3 (4) (5) (5) 1 1 0 20 40 60 0 CL (pF) 20 40 60 CL (pF) c. LOW to HIGH propagation delay (nAn to nBn); VCC(A) = 2.5 V d. HIGH to LOW propagation delay (nAn to nBn); VCC(A) = 2.5 V (1) VCC(B) = 1.2 V. (2) VCC(B) = 1.5 V. (3) VCC(B) = 1.8 V. (4) VCC(B) = 2.5 V. (5) VCC(B) = 3.3 V. Fig 9. Typical propagation delay versus load capacitance; Tamb = 25 C 74AVC32T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 January 2013 © NXP B.V. 2013. All rights reserved. 18 of 24 74AVC32T245 NXP Semiconductors 32-bit dual supply translating transceiver; 3-state 001aai485 7 tPLH (ns) 001aai484 7 tPHL (ns) (1) 5 (1) 5 (2) (2) (3) (3) 3 3 (4) (4) (5) (5) 1 1 0 20 40 60 0 CL (pF) 20 40 60 CL (pF) a. LOW to HIGH propagation delay (nAn to nBn); VCC(A) = 3.3 V b. HIGH to LOW propagation delay (nAn to nBn); VCC(A) = 3.3 V (1) VCC(B) = 1.2 V. (2) VCC(B) = 1.5 V. (3) VCC(B) = 1.8 V. (4) VCC(B) = 2.5 V. (5) VCC(B) = 3.3 V. Fig 10. Typical propagation delay versus load capacitance; Tamb = 25 C 74AVC32T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 January 2013 © NXP B.V. 2013. All rights reserved. 19 of 24 74AVC32T245 NXP Semiconductors 32-bit dual supply translating transceiver; 3-state 13. Package outline LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm SOT536-1 A B D ball A1 index area A A2 E A1 detail X e1 1/2 C e ∅v M e ∅w M b T R P N M L K J H G F E D C B A ball A1 index area y1 C C A B C y e e2 1/2 e 1 2 3 4 5 6 X 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 b D E e e1 e2 v w y y1 mm 1.5 0.41 0.31 1.2 0.9 0.51 0.41 5.6 5.4 13.6 13.4 0.8 4 12 0.15 0.1 0.1 0.2 OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 00-03-04 03-02-05 SOT536-1 Fig 11. Package outline SOT536-1 (LFBGA96) 74AVC32T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 January 2013 © NXP B.V. 2013. All rights reserved. 20 of 24 74AVC32T245 NXP Semiconductors 32-bit dual supply translating transceiver; 3-state 14. Abbreviations Table 16. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 15. Revision history Table 17. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AVC32T245 v.1 20130116 Product data sheet - - 74AVC32T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 January 2013 © NXP B.V. 2013. All rights reserved. 21 of 24 74AVC32T245 NXP Semiconductors 32-bit dual supply translating transceiver; 3-state 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. 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Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 January 2013 © NXP B.V. 2013. All rights reserved. 22 of 24 74AVC32T245 NXP Semiconductors 32-bit dual supply translating transceiver; 3-state Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74AVC32T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 January 2013 © NXP B.V. 2013. All rights reserved. 23 of 24 74AVC32T245 NXP Semiconductors 32-bit dual supply translating transceiver; 3-state 18. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Typical propagation delay characteristics . . 16 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 20 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 21 Legal information. . . . . . . . . . . . . . . . . . . . . . . 22 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 22 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Contact information. . . . . . . . . . . . . . . . . . . . . 23 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 16 January 2013 Document identifier: 74AVC32T245