74AVCH1T45 Dual supply translating transceiver; 3-state Rev. 01 — 25 October 2007 Product data sheet 1. General description The 74AVCH1T45 is a single bit, dual supply transceiver that enables bidirectional level translation. It features two data input-output ports (A and B), a direction control input (DIR) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 0.8 V and 3.6 V making the device suitable for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins A and DIR are referenced to VCC(A) and pin B is referenced to VCC(B). A HIGH on DIR allows transmission from A to B and a LOW on DIR allows transmission from B to A. The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both A and B are in the high-impedance OFF-state. The 74AVCH1T45 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors. 2. Features ■ Wide supply voltage range: ◆ VCC(A): 0.8 V to 3.6 V ◆ VCC(B): 0.8 V to 3.6 V ■ High noise immunity ■ Complies with JEDEC standards: ◆ JESD8-12 (0.8 V to 1.3 V) ◆ JESD8-11 (0.9 V to 1.65 V) ◆ JESD8-7 (1.2 V to 1.95 V) ◆ JESD8-5 (1.8 V to 2.7 V) ◆ JESD8-B (2.7 V to 3.6 V) ■ ESD protection: ◆ HBM JESD22-A114E Class 3B exceeds 8000 V ◆ MM JESD22-A115-A exceeds 200 V ◆ CDM JESD22-C101C exceeds 1000 V ■ Maximum data rates: ◆ 500 Mbit/s (1.8 V to 3.3 V translation) ◆ 320 Mbit/s (< 1.8 V to 3.3 V translation) ◆ 320 Mbit/s (translate to 2.5 V or 1.8 V) ◆ 280 Mbit/s (translate to 1.5 V) 74AVCH1T45 NXP Semiconductors Dual supply translating transceiver; 3-state ■ ■ ■ ■ ■ ■ ■ ■ ◆ 240 Mbit/s (translate to 1.2 V) Suspend mode Bus hold on data inputs Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial Power-down mode operation Multiple package options Specified from −40 °C to +85 °C and −40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AVCH1T45GW −40 °C to +125 °C SC-88 plastic surface-mounted package; 6 leads SOT363 74AVCH1T45GM −40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads; SOT886 6 terminals; body 1 × 1.45 × 0.5 mm 4. Marking Table 2. Marking Type number Marking code 74AVCH1T45GW K5 74AVCH1T45GM K5 5. Functional diagram DIR 5 DIR A 3 A 4 VCC(A) B B VCC(B) VCC(A) 001aag885 Fig 1. Logic symbol 001aag886 Fig 2. Logic diagram 74AVCH1T45_1 Product data sheet VCC(B) © NXP B.V. 2007. All rights reserved. Rev. 01 — 25 October 2007 2 of 22 74AVCH1T45 NXP Semiconductors Dual supply translating transceiver; 3-state 6. Pinning information 6.1 Pinning 74AVCH1T45 74AVCH1T45 VCC(A) 1 6 GND 2 5 DIR A 3 4 B VCC(A) 1 6 VCC(B) GND 2 5 DIR A 3 4 B VCC(B) 001aag888 Transparent top view 001aag887 Fig 3. Pin configuration SOT363 Fig 4. Pin configuration SOT886 6.2 Pin description Table 3. Pin description Symbol Pin Description VCC(A) 1 supply voltage port A and DIR GND 2 ground (0 V) A 3 data input or output B 4 data input or output DIR 5 direction control VCC(B) 6 supply voltage port B 7. Functional description Table 4. Function table[1] Supply voltage Input Input/output[3] VCC(A), VCC(B) DIR[2] A B 0.8 V to 3.6 V L A=B input 0.8 V to 3.6 V H input B=A GND[4] X Z Z [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. [2] The DIR input circuit is referenced to VCC(A). [3] The input circuit of the data I/O is always active. [4] If at least one of VCC(A) or VCC(B) is at GND level, the device goes into suspend mode. 74AVCH1T45_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 25 October 2007 3 of 22 74AVCH1T45 NXP Semiconductors Dual supply translating transceiver; 3-state 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC(A) supply voltage port A VCC(B) supply voltage port B IIK input clamping current VI input voltage IOK output clamping current output voltage VO Conditions VI < 0 V [1] Suspend or 3-state mode Max Unit −0.5 +4.6 V −0.5 +4.6 V −50 - mA −0.5 +4.6 V mA −50 - [1][2][3] −0.5 VCCO + 0.5 V [1] −0.5 +4.6 V VO < 0 V Active mode Min IO output current VO = 0 V to VCC - ±50 mA ICC supply current ICC(A) or ICC(B) - 100 mA IGND ground current −100 - mA Tstg storage temperature −65 +150 °C - 250 mW total power dissipation Ptot [1] Tamb = −40 °C to +125 °C [4] The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] VCCO is the supply voltage associated with the output port. [3] VCCO + 0.5 V should not exceed 4.6 V. [4] For SC-88 packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K. For XSON6 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K. 9. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter Min Max Unit VCC(A) supply voltage port A 0.8 3.6 V VCC(B) supply voltage port B 0.8 3.6 V VI input voltage 0 3.6 V 0 VCCO V 0 3.6 V −40 +125 °C - 5 ns/V output voltage VO Conditions Active mode [1] Suspend or 3-state mode Tamb ∆t/∆V ambient temperature input transition rise and fall rate VCCI = 0.8 V to 3.6 V [1] VCCO is the supply voltage associated with the output port. [2] VCCI is the supply voltage associated with the input port. 74AVCH1T45_1 Product data sheet [2] © NXP B.V. 2007. All rights reserved. Rev. 01 — 25 October 2007 4 of 22 74AVCH1T45 NXP Semiconductors Dual supply translating transceiver; 3-state 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit - 0.69 - V - 0.07 - V Tamb = 25 °C HIGH-level output voltage VI = VIH or VIL LOW-level output voltage VI = VIH or VIL II input leakage current DIR input; VI = 0 V to 3.6 V; VCC(A) = VCC(B) = 0.8 V to 3.6 V - ±0.025 ±0.25 µA IBHL bus hold LOW current A or B port; VI = 0.42 V; VCC(A) = VCC(B) = 1.2 V - 26 - µA IBHH bus hold HIGH current A or B port; VI = 0.78 V; VCC(A) = VCC(B) = 1.2 V - −24 - µA IBHLO bus hold LOW overdrive current A or B port; VCC(A) = VCC(B) = 1.2 V [1] - 28 - µA IBHHO bus hold HIGH overdrive current A or B port; VCC(A) = VCC(B) = 1.2 V [1] - −26 - µA IOZ OFF-state output current A or B port; VO = 0 V or VCCO; VCC(A) = VCC(B) = 0.8 V to 3.6 V [2] - ±0.5 ±2.5 µA IOFF power-off leakage current A port; VI or VO = 0 V to 3.6 V; VCC(A) = 0 V; VCC(B) = 0.8 V to 3.6 V - ±0.1 ±1 µA B port; VI or VO = 0 V to 3.6 V; VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V - ±0.1 ±1 µA VOH VOL IO = −1.5 mA; VCC(A) = VCC(B) = 0.8 V IO = 1.5 mA; VCC(A) = VCC(B) = 0.8 V CI input capacitance DIR input; VI = 0 V or 3.3 V; VCC(A) = VCC(B) = 3.3 V - 1 - pF CI/O input/output capacitance A and B port; suspend mode; VO = 3.3 V or 0 V; VCC(A) = VCC(B) = 3.3 V - 4 - pF VCCI = 0.8 V 0.70 × VCCI - - V VCCI = 1.1 V to 1.95 V 0.65 × VCCI - - V VCCI = 2.3 V to 2.7 V 1.6 - - V VCCI = 3.0 V to 3.6 V 2 - - V VCCI = 0.8 V 0.70 × VCC(A) - - V VCCI = 1.1 V to 1.95 V 0.65 × VCC(A) - - V VCCI = 2.3 V to 2.7 V 1.6 - - V VCCI = 3.0 V to 3.6 V 2 - - V Tamb = −40 °C to +85 °C VIH HIGH-level input voltage [3] data input DIR input 74AVCH1T45_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 25 October 2007 5 of 22 74AVCH1T45 NXP Semiconductors Dual supply translating transceiver; 3-state Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VIL LOW-level input voltage Conditions Min Typ Max Unit VCCI = 0.8 V - - 0.30 × VCCI V VCCI = 1.1 V to 1.95 V - - 0.35 × VCCI V VCCI = 2.3 V to 2.7 V - - 0.7 V VCCI = 3.0 V to 3.6 V - - 0.9 V VCCI = 0.8 V - - 0.30 × VCC(A) V VCCI = 1.1 V to 1.95 V - - 0.35 × VCC(A) V VCCI = 2.3 V to 2.7 V - - 0.7 V VCCI = 3.0 V to 3.6 V - - 0.9 V VCCO − 0.1 - - V IO = −3 mA; VCC(A) = VCC(B) = 1.1 V 0.85 - - V IO = −6 mA; VCC(A) = VCC(B) = 1.4 V 1.05 - - V IO = −8 mA; VCC(A) = VCC(B) = 1.65 V 1.2 - - V IO = −9 mA; VCC(A) = VCC(B) = 2.3 V 1.75 - - V IO = −12 mA; VCC(A) = VCC(B) = 3.0 V 2.3 - - V IO = 100 µA; VCC(A) = VCC(B) = 0.8 V to 3.6 V - - 0.1 V IO = 3 mA; VCC(A) = VCC(B) = 1.1 V - - 0.25 V IO = 6 mA; VCC(A) = VCC(B) = 1.4 V - - 0.35 V IO = 8 mA; VCC(A) = VCC(B) = 1.65 V - - 0.45 V IO = 9 mA; VCC(A) = VCC(B) = 2.3 V - - 0.55 V IO = 12 mA; VCC(A) = VCC(B) = 3.0 V - - 0.7 V - - ±1 µA 15 - - µA [3] data input DIR input VOH VOL HIGH-level output voltage LOW-level output voltage VI = VIH or VIL IO = −100 µA; VCC(A) = VCC(B) = 0.8 V to 3.6 V VI = VIH or VIL II input leakage current DIR input; VI = 0 V to 3.6 V; VCC(A) = VCC(B) = 0.8 V to 3.6 V IBHL bus hold LOW current A or B port IBHH bus hold HIGH current VI = 0.49 V; VCC(A) = VCC(B) = 1.4 V VI = 0.58 V; VCC(A) = VCC(B) = 1.65 V 25 - - µA VI = 0.70 V; VCC(A) = VCC(B) = 2.3 V 45 - - µA VI = 0.80 V; VCC(A) = VCC(B) = 3.0 V 100 - - µA VI = 0.91 V; VCC(A) = VCC(B) = 1.4 V −15 - - µA VI = 1.07 V; VCC(A) = VCC(B) = 1.65 V −25 - - µA VI = 1.60 V; VCC(A) = VCC(B) = 2.3 V −45 - - µA VI = 2.00 V; VCC(A) = VCC(B) = 3.0 V −100 - - µA A or B port 74AVCH1T45_1 Product data sheet [2] © NXP B.V. 2007. All rights reserved. Rev. 01 — 25 October 2007 6 of 22 74AVCH1T45 NXP Semiconductors Dual supply translating transceiver; 3-state Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter IBHLO bus hold LOW overdrive current Conditions Min Typ Max Unit VCC(A) = VCC(B) = 1.6 V 125 - - µA VCC(A) = VCC(B) = 1.95 V 200 - - µA VCC(A) = VCC(B) = 2.7 V 300 - - µA 500 - - µA VCC(A) = VCC(B) = 1.6 V −125 - - µA VCC(A) = VCC(B) = 1.95 V −200 - - µA VCC(A) = VCC(B) = 2.7 V −300 - - µA −500 - - µA - - ±5 µA [1] A or B port VCC(A) = VCC(B) = 3.6 V IBHHO bus hold HIGH overdrive current [1] A or B port VCC(A) = VCC(B) = 3.6 V [2] IOZ OFF-state output current A or B port; VO = 0 V or VCCO; VCC(A) = VCC(B) = 0.8 V to 3.6 V IOFF power-off leakage current A port; VI or VO = 0 V to 3.6 V; VCC(A) = 0 V; VCC(B) = 0.8 V to 3.6 V - - ±5 µA B port; VI or VO = 0 V to 3.6 V; VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V - - ±5 µA - - 8 µA ICC supply current A port; VI = 0 V or VCCI; IO = 0 A [3] VCC(A) = VCC(B) = 0.8 V to 3.6 V VCC(A) = 3.6 V; VCC(B) = 0 V - - 8 µA VCC(A) = 0 V; VCC(B) = 3.6 V −2 0 - µA VCC(A) = VCC(B) = 0.8 V to 3.6 V - - 8 µA VCC(A) = 3.6 V; VCC(B) = 0 V −2 0 - µA VCC(A) = 0 V; VCC(B) = 3.6 V - - 8 µA - - 16 µA VCCI = 0.8 V 0.70 × VCCI - - V VCCI = 1.1 V to 1.95 V 0.65 × VCCI - - V VCCI = 2.3 V to 2.7 V 1.6 - - V VCCI = 3.0 V to 3.6 V 2 - - V VCCI = 0.8 V 0.70 × VCC(A) - - V VCCI = 1.1 V to 1.95 V 0.65 × VCC(A) - - V VCCI = 2.3 V to 2.7 V 1.6 - - V VCCI = 3.0 V to 3.6 V 2 - - V B port; VI = 0 V or VCCI; IO = 0 A A plus B port (ICC(A) + ICC(B)); IO = 0 A; VI = 0 V or VCCI; VCC(A) = VCC(B) = 0.8 V to 3.6 V Tamb = −40 °C to +125 °C VIH HIGH-level input voltage [3] data input DIR input 74AVCH1T45_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 25 October 2007 7 of 22 74AVCH1T45 NXP Semiconductors Dual supply translating transceiver; 3-state Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VIL LOW-level input voltage Conditions Min Typ Max Unit VCCI = 0.8 V - - 0.30 × VCCI V VCCI = 1.1 V to 1.95 V - - 0.35 × VCCI V VCCI = 2.3 V to 2.7 V - - 0.7 V VCCI = 3.0 V to 3.6 V - - 0.9 V VCCI = 0.8 V - - 0.30 × VCC(A) V VCCI = 1.1 V to 1.95 V - - 0.35 × VCC(A) V VCCI = 2.3 V to 2.7 V - - 0.7 V VCCI = 3.0 V to 3.6 V - - 0.9 V VCCO − 0.1 - - V IO = −3 mA; VCC(A) = VCC(B) = 1.1 V 0.85 - - V IO = −6 mA; VCC(A) = VCC(B) = 1.4 V 1.05 - - V IO = −8 mA; VCC(A) = VCC(B) = 1.65 V 1.2 - - V IO = −9 mA; VCC(A) = VCC(B) = 2.3 V 1.75 - - V IO = −12 mA; VCC(A) = VCC(B) = 3.0 V 2.3 - - V IO = 100 µA; VCC(A) = VCC(B) = 0.8 V to 3.6 V - - 0.1 V IO = 3 mA; VCC(A) = VCC(B) = 1.1 V - - 0.25 V IO = 6 mA; VCC(A) = VCC(B) = 1.4 V - - 0.35 V IO = 8 mA; VCC(A) = VCC(B) = 1.65 V - - 0.45 V IO = 9 mA; VCC(A) = VCC(B) = 2.3 V - - 0.55 V IO = 12 mA; VCC(A) = VCC(B) = 3.0 V - - 0.7 V - - ±1.5 µA 15 - - µA [3] data input DIR input VOH VOL HIGH-level output voltage LOW-level output voltage VI = VIH or VIL IO = −100 µA; VCC(A) = VCC(B) = 0.8 V to 3.6 V VI = VIH or VIL II input leakage current DIR input; VI = 0 V to 3.6 V; VCC(A) = VCC(B) = 0.8 V to 3.6 V IBHL bus hold LOW current A or B port IBHH bus hold HIGH current VI = 0.49 V; VCC(A) = VCC(B) = 1.4 V VI = 0.58 V; VCC(A) = VCC(B) = 1.65 V 25 - - µA VI = 0.70 V; VCC(A) = VCC(B) = 2.3 V 45 - - µA VI = 0.80 V; VCC(A) = VCC(B) = 3.0 V 90 - - µA VI = 0.91 V; VCC(A) = VCC(B) = 1.4 V −15 - - µA VI = 1.07 V; VCC(A) = VCC(B) = 1.65 V −25 - - µA VI = 1.60 V; VCC(A) = VCC(B) = 2.3 V −45 - - µA VI = 2.00 V; VCC(A) = VCC(B) = 3.0 V −100 - - µA A or B port 74AVCH1T45_1 Product data sheet [2] © NXP B.V. 2007. All rights reserved. Rev. 01 — 25 October 2007 8 of 22 74AVCH1T45 NXP Semiconductors Dual supply translating transceiver; 3-state Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter IBHLO bus hold LOW overdrive current Conditions Min Typ Max Unit VCC(A) = VCC(B) = 1.6 V 125 - - µA VCC(A) = VCC(B) = 1.95 V 200 - - µA VCC(A) = VCC(B) = 2.7 V 300 - - µA 500 - - µA VCC(A) = VCC(B) = 1.6 V −125 - - µA VCC(A) = VCC(B) = 1.95 V −200 - - µA VCC(A) = VCC(B) = 2.7 V −300 - - µA −500 - - µA - - ±7.5 µA [1] A or B port VCC(A) = VCC(B) = 3.6 V IBHHO bus hold HIGH overdrive current [1] A or B port VCC(A) = VCC(B) = 3.6 V [2] IOZ OFF-state output current A or B port; VO = 0 V or VCCO; VCC(A) = VCC(B) = 0.8 V to 3.6 V IOFF power-off leakage current A port; VI or VO = 0 V to 3.6 V; VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V - - ±35 µA B port; VI or VO = 0 V to 3.6 V; VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V - - ±35 µA - - 12 µA supply current ICC A port; VI = 0 V or VCCI; IO = 0 A VCC(A) = VCC(B) = 0.8 V to 3.6 V [3] VCC(A) = 3.6 V; VCC(B) = 0 V - - 12 µA VCC(A) = 0 V; VCC(B) = 3.6 V −8 0 - µA VCC(A) = VCC(B) = 0.8 V to 3.6 V - - 12 µA VCC(A) = 3.6 V; VCC(B) = 0 V −8 0 - µA VCC(A) = 0 V; VCC(B) = 3.6 V - - 12 µA - - 24 µA B port; VI = 0 V or VCCI; IO = 0 A A plus B port (ICC(A) + ICC(B)); IO = 0 A; VI = 0 V or VCCI; VCC(A) = VCC(B) = 0.8 V to 3.6 V [1] In order to guarantee the node switches, an external driver must source/sink at least IBHLO / IBHHO when the input is in the range VIL to VIH. [2] VCCO is the supply voltage associated with the output port. [3] VCCI is the supply voltage associated with the data input port. 74AVCH1T45_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 25 October 2007 9 of 22 74AVCH1T45 NXP Semiconductors Dual supply translating transceiver; 3-state 11. Dynamic characteristics Table 8. Typical dynamic characteristics at VCC(A) = 0.8 V and Tamb = 25 °C [1] Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6 Symbol Parameter Conditions VCC(B) 0.8 V tpd [1] 1.8 V 2.5 V 3.3 V 15.8 8.4 8.0 8.0 8.7 9.5 ns B to A 15.8 12.7 12.4 12.2 12.0 11.8 ns DIR to A 12.2 12.2 12.2 12.2 12.2 12.2 ns DIR to B 11.7 7.9 7.6 8.2 8.7 10.2 ns enable time ten 1.5 V propagation delay A to B disable time tdis 1.2 V Unit DIR to A 27.5 20.6 20.0 20.4 20.7 22.0 ns DIR to B 28.0 20.6 20.2 20.2 20.9 21.7 ns tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. ten is a calculated value using the formula shown in Section 13.4 “Enable times” Table 9. Typical dynamic characteristics at VCC(B) = 0.8 V and Tamb = 25 °C [1] Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6 Symbol Parameter tpd [1] Unit 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V propagation delay A to B 15.8 12.7 12.4 12.2 12.0 11.8 ns B to A 15.8 8.4 8.0 8.0 8.7 9.5 ns DIR to A 12.2 4.9 3.8 3.7 2.8 3.4 ns DIR to B 11.7 9.2 9.0 8.8 8.7 8.6 ns DIR to A 27.5 17.6 17.0 16.8 17.4 18.1 ns DIR to B 28.0 17.6 16.2 15.9 14.8 15.2 ns enable time ten VCC(A) 0.8 V disable time tdis Conditions tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. ten is a calculated value using the formula shown in Section 13.4 “Enable times” Table 10. Typical power dissipation capacitance at VCC(A) = VCC(B) and Tamb = 25 °C [1][2] Voltages are referenced to GND (ground = 0 V). Symbol Parameter power dissipation capacitance CPD Conditions VCC(A) and VCC(B) 0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V A port: (direction A to B); B port: (direction B to A) 1 2 2 2 2 2 pF A port: (direction B to A); B port: (direction A to B) 9 11 11 12 14 17 pF [1] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. [2] fi = 10 MHz; VI = GND to VCC; tr = tf = 1 ns; CL = 0 pF; RL = ∞ Ω. 74AVCH1T45_1 Product data sheet Unit © NXP B.V. 2007. All rights reserved. Rev. 01 — 25 October 2007 10 of 22 74AVCH1T45 NXP Semiconductors Dual supply translating transceiver; 3-state Table 11. Dynamic characteristics for temperature range −40 °C to +85 °C [1] Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6. Symbol Parameter Conditions VCC(B) Unit 1.2 V ± 0.1 V 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V Min Max Min Max Min Max Min Max Min Max 1.0 9.0 0.7 6.8 0.6 6.1 0.5 5.7 0.5 6.1 VCC(A) = 1.1 V to 1.3 V tpd propagation delay A to B B to A 1.0 9.0 0.8 8.0 0.7 7.7 0.6 7.2 0.5 7.1 ns tdis disable time DIR to A 2.2 8.8 2.2 8.8 2.2 8.8 2.2 8.8 2.2 8.8 ns DIR to B 2.2 8.4 1.8 6.7 2.0 6.9 1.7 6.2 2.4 7.2 ns DIR to A - 17.4 - 14.7 - 14.6 - 13.4 - 14.3 ns DIR to B - 17.8 - 15.6 - 14.9 - 14.5 - 14.9 ns A to B 1.0 8.0 0.7 5.4 0.6 4.6 0.5 3.7 0.5 3.5 ns B to A 1.0 6.8 0.8 5.4 0.7 5.1 0.6 4.7 0.5 4.5 ns enable time ten ns VCC(A) = 1.4 V to 1.6 V propagation delay tpd disable time tdis enable time ten DIR to A 1.6 6.3 1.6 6.3 1.6 6.3 1.6 6.3 1.6 6.3 ns DIR to B 2.0 7.6 1.8 5.9 1.6 6.0 1.2 4.8 1.7 5.5 ns DIR to A - 14.4 - 11.3 - 11.1 - 9.5 - 10.0 ns DIR to B - 14.3 - 11.7 - 10.9 - 10.0 - 9.8 ns VCC(A) = 1.65 V to 1.95 V propagation delay A to B 1.0 7.7 0.6 5.1 0.5 4.3 0.5 3.4 0.5 3.1 ns B to A 1.0 6.1 0.7 4.6 0.5 4.4 0.5 3.9 0.5 3.7 ns tdis disable time DIR to A 1.6 5.5 1.6 5.5 1.6 5.5 1.6 5.5 1.6 5.5 ns DIR to B 1.8 7.8 1.8 5.7 1.4 5.8 1.0 4.5 1.5 5.2 ns ten enable time DIR to A - 13.9 - 10.3 - 10.2 - 8.4 - 8.9 ns DIR to B - 13.2 - 10.6 - 9.8 - 8.9 - 8.6 ns tpd VCC(A) = 2.3 V to 2.7 V tpd tdis propagation delay A to B 1.0 7.2 0.5 4.7 0.5 3.9 0.5 3.0 0.5 2.6 ns B to A 1.0 5.7 0.6 3.8 0.5 3.4 0.5 3.0 0.5 2.8 ns disable time DIR to A 1.5 4.2 1.5 4.2 1.5 4.2 1.5 4.2 1.5 4.2 ns DIR to B 1.7 7.3 2.0 5.2 1.5 5.1 0.6 4.2 1.1 4.8 ns enable time ten DIR to A - 13.0 - 9.0 - 8.5 - 7.2 - 7.6 ns DIR to B - 11.4 - 8.9 - 8.1 - 7.2 - 6.8 ns 1.0 7.1 0.5 4.5 0.5 3.7 0.5 2.8 0.5 2.4 ns VCC(A) = 3.0 V to 3.6 V tpd propagation delay A to B B to A 1.0 6.1 0.6 3.6 0.5 3.1 0.5 2.6 0.5 2.4 ns tdis disable time DIR to A 1.5 4.7 1.5 4.7 1.5 4.7 1.5 4.7 1.5 4.7 ns DIR to B 1.7 7.2 0.7 5.5 0.6 5.5 0.7 4.1 1.7 4.7 ns DIR to A - 13.3 - 9.1 - 8.6 - 6.7 - 7.1 ns DIR to B - 11.8 - 9.2 - 8.4 - 7.5 - 7.1 ns enable time ten [1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. ten is a calculated value using the formula shown in Section 13.4 “Enable times” 74AVCH1T45_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 25 October 2007 11 of 22 74AVCH1T45 NXP Semiconductors Dual supply translating transceiver; 3-state Table 12. Dynamic characteristics for temperature range −40 °C to +125 °C [1] Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6 Symbol Parameter Conditions VCC(B) Unit 1.2 V ± 0.1 V 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V Min Max Min Max Min Max Min Max Min Max 1.0 9.9 0.7 7.5 0.6 6.8 0.5 6.3 0.5 6.8 VCC(A) = 1.1 V to 1.3 V tpd propagation delay A to B B to A 1.0 9.9 0.8 8.8 0.7 8.5 0.6 8.0 0.5 7.9 ns tdis disable time DIR to A 2.2 9.7 2.2 9.7 2.2 9.7 2.2 9.7 2.2 9.7 ns DIR to B 2.2 9.2 1.8 7.4 2.0 7.6 1.7 6.9 2.4 8.0 ns DIR to A - 19.1 - 16.2 - 16.1 - 14.9 - 15.9 ns DIR to B - 19.6 - 17.2 - 16.5 - 16.0 - 16.5 ns enable time ten ns VCC(A) = 1.4 V to 1.6 V tpd tdis propagation delay A to B 1.0 8.8 0.7 6.0 0.6 5.1 0.5 4.1 0.5 3.9 ns B to A 1.0 7.5 0.8 6.0 0.7 5.7 0.6 5.2 0.5 5.0 ns disable time DIR to A 1.6 7.0 1.6 7.0 1.6 7.0 1.6 7.0 1.6 7.0 ns DIR to B 2.0 8.3 1.8 6.5 1.6 6.6 1.2 5.3 1.7 6.1 ns DIR to A - 15.8 - 12.5 - 12.3 - 10.5 - 11.1 ns DIR to B - 15.8 - 13.0 - 12.7 - 11.1 - 10.9 ns enable time ten VCC(A) = 1.65 V to 1.95 V propagation delay A to B 1.0 8.5 0.6 5.7 0.5 4.8 0.5 3.8 0.5 3.5 ns B to A 1.0 6.8 0.7 5.1 0.5 4.9 0.5 4.3 0.5 4.1 ns tdis disable time DIR to A 1.6 6.1 1.6 6.1 1.6 6.1 1.6 6.1 1.6 6.1 ns DIR to B 1.8 8.6 1.8 6.3 1.4 6.4 1.0 5.0 1.5 5.8 ns ten enable time DIR to A - 15.4 - 11.4 - 11.3 - 9.3 - 9.9 ns DIR to B - 14.6 - 11.8 - 10.9 - 9.9 - 9.6 ns tpd VCC(A) = 2.3 V to 2.7 V tpd tdis propagation delay A to B 1.0 8.0 0.5 5.2 0.5 4.3 0.5 3.3 0.5 2.9 ns B to A 1.0 6.3 0.6 4.2 0.5 3.8 0.5 3.3 0.5 3.1 ns disable time DIR to A 1.5 4.7 1.5 4.7 1.5 4.7 1.5 4.7 1.5 4.7 ns DIR to B 1.7 8.0 2.0 5.8 1.5 5.7 0.6 4.7 1.1 5.3 ns enable time ten DIR to A - 14.3 - 10.0 - 9.5 - 8.0 - 8.4 ns DIR to B - 12.7 - 9.9 - 9.0 - 8.0 - 7.6 ns 1.0 7.9 0.5 5.0 0.5 4.1 0.5 3.1 0.5 2.7 ns VCC(A) = 3.0 V to 3.6 V tpd propagation delay A to B B to A 1.0 6.8 0.6 4.0 0.5 3.5 0.5 2.9 0.5 2.7 ns tdis disable time DIR to A 1.5 5.2 1.5 5.2 1.5 5.2 1.5 5.2 1.5 5.2 ns DIR to B 1.7 7.9 0.7 6.0 0.6 6.1 0.7 4.6 1.7 5.2 ns DIR to A - 14.7 - 10.1 - 9.6 - 7.5 - 7.9 ns DIR to B - 13.1 - 10.2 - 9.3 - 8.3 - 7.9 ns enable time ten [1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. ten is a calculated value using the formula shown in Section 13.4 “Enable times” 74AVCH1T45_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 25 October 2007 12 of 22 74AVCH1T45 NXP Semiconductors Dual supply translating transceiver; 3-state 12. Waveforms VI VM A, B input GND t PLH t PHL VOH B, A output VM 001aae967 VOL Measurement points are given in Table 13. VOL and VOH are typical output voltage drops that occur with the output load. Fig 5. The data input (A, B) to output (B, A) propagation delay times VI DIR input VM GND t PLZ output LOW-to-OFF OFF-to-LOW t PZL VCCO VM VX VOL t PHZ VOH t PZH VY output HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs disabled outputs enabled 001aae968 Measurement points are given in Table 13. VOL and VOH are typical output voltage drops that occur with the output load. Fig 6. Enable and disable times Table 13. Measurement points Supply voltage Input[1] Output[2] VCC(A), VCC(B) VM VM VX VY 1.1 V to 1.6 V 0.5 × VCCI 0.5 × VCCO VOL + 0.1 V VOH − 0.1 V 1.65 V to 2.7 V 0.5 × VCCI 0.5 × VCCO VOL + 0.15 V VOH − 0.15 V 3.0 V to 3.6 V 0.5 × VCCI 0.5 × VCCO VOL + 0.3 V VOH − 0.3 V [1] VCCI is the supply voltage associated with the data input port. [2] VCCO is the supply voltage associated with the output port. 74AVCH1T45_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 25 October 2007 13 of 22 74AVCH1T45 NXP Semiconductors Dual supply translating transceiver; 3-state VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VEXT VCC VI RL VO G DUT RT CL RL 001aae331 Test data is given in Table 14. RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance. VEXT = External voltage for measuring switching times. Fig 7. Load circuitry for switching times Table 14. Test data Supply voltage Input VCC(A), VCC(B) VI[1] ∆t/∆V Load CL RL tPLH, tPHL tPZH, tPHZ tPZL, tPLZ[2] 1.1 V to 1.6 V VCCI ≤ 1.0 ns/V 15 pF 2 kΩ open GND 2 × VCCO 1.65 V to 2.7 V VCCI ≤ 1.0 ns/V 15 pF 2 kΩ open GND 2 × VCCO 3.0 V to 3.6 V VCCI ≤ 1.0 ns/V 15 pF 2 kΩ open GND 2 × VCCO [1] VCCI is the supply voltage associated with the data input port. [2] VCCO is the supply voltage associated with the output port. VEXT 74AVCH1T45_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 25 October 2007 14 of 22 74AVCH1T45 NXP Semiconductors Dual supply translating transceiver; 3-state 13. Application information 13.1 Unidirectional logic level-shifting application The circuit given in Figure 8 is an example of the 74AVCH1T45 being used in an unidirectional logic level-shifting application. 74AVCH1T45 VCC1 VCC(A) GND VCC1 A 1 6 2 5 3 4 system-1 VCC(B) VCC2 DIR VCC2 B system-2 001aag889 Fig 8. Unidirectional logic level-shifting application Table 15. Description unidirectional logic level-shifting application Pin Name Function Description 1 VCC(A) VCC1 supply voltage of system-1 (0.8 V to 3.6 V) 2 GND GND device GND 3 A OUT output level depends on VCC1 voltage 4 DIR DIR the GND (LOW level) determines B port to A port direction 5 B IN input threshold value depends on VCC2 voltage 6 VCC(B) VCC2 supply voltage of system-2 (0.8 V to 3.6 V) 74AVCH1T45_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 25 October 2007 15 of 22 74AVCH1T45 NXP Semiconductors Dual supply translating transceiver; 3-state 13.2 Bidirectional logic level-shifting application Figure 9 shows the 74AVCH1T45 being used in a bidirectional logic level-shifting application. Since the device does not have an output enable pin, the system designer should take precautions to avoid bus contention between system-1 and system-2 when changing directions. 74AVCH1T45 VCC1 VCC1 VCC(A) GND I/O-1 A 1 6 2 5 3 4 VCC(B) VCC2 DIR VCC2 I/O-2 B DIR CTRL system-1 system-2 001aag890 Fig 9. Bidirectional logic level-shifting application Table 16 gives a sequence that will illustrate data transmission from system-1 to system-2 and then from system-2 to system-1. Table 16. Description bidirectional logic level-shifting application[1] State DIR CTRL I/O-1 I/O-2 Description 1 H output input system-1 data to system-2 2 H Z Z system-2 is getting ready to send data to system-1. I/O-1 and I/O-2 are disabled. The bus-line state depends on bus hold. 3 L Z Z DIR bit is set LOW. I/O-1 and I/O-2 still are disabled. The bus-line state depends on bus hold. 4 L input output system-2 data to system-1 [1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state. 74AVCH1T45_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 25 October 2007 16 of 22 74AVCH1T45 NXP Semiconductors Dual supply translating transceiver; 3-state 13.3 Power-up considerations The device is designed such that no special power-up sequence is required other than GND being applied first. Table 17. Typical total supply current (ICC(A) + ICC(B)) VCC(A) VCC(B) Unit 0V 0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 0V 0 0.1 0.1 0.1 0.1 0.1 0.1 µA 0.8 V 0.1 0.1 0.1 0.1 0.1 0.7 2.3 µA 1.2 V 0.1 0.1 0.1 0.1 0.1 0.3 1.4 µA 1.5 V 0.1 0.1 0.1 0.1 0.1 0.1 0.9 µA 1.8 V 0.1 0.1 0.1 0.1 0.1 0.1 0.5 µA 2.5 V 0.1 0.7 0.3 0.1 0.1 0.1 0.1 µA 3.3 V 0.1 2.3 1.4 0.9 0.5 0.1 0.1 µA 13.4 Enable times Calculate the enable times for the 74AVCH1T45 using the following formulas: • ten (DIR to A) = tdis (DIR to B) + tpd (B to A) • ten (DIR to B) = tdis (DIR to A) + tpd (A to B) In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is switched until an output is expected. For example, if the 74AVCH1T45 initially is transmitting from A to B, then the DIR bit is switched, the B port of the device must be disabled before presenting it with an input. After the B port has been disabled, an input signal applied to it appears on the corresponding A port after the specified propagation delay. 74AVCH1T45_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 25 October 2007 17 of 22 74AVCH1T45 NXP Semiconductors Dual supply translating transceiver; 3-state 14. Package outline Plastic surface-mounted package; 6 leads SOT363 D E B y X A HE 6 5 v M A 4 Q pin 1 index A A1 1 2 e1 3 bp c Lp w M B e detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp c D E e e1 HE Lp Q v w y mm 1.1 0.8 0.1 0.30 0.20 0.25 0.10 2.2 1.8 1.35 1.15 1.3 0.65 2.2 2.0 0.45 0.15 0.25 0.15 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC SOT363 JEDEC JEITA SC-88 EUROPEAN PROJECTION ISSUE DATE 04-11-08 06-03-16 Fig 10. Package outline SOT363 (SC-88) 74AVCH1T45_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 25 October 2007 18 of 22 74AVCH1T45 NXP Semiconductors Dual supply translating transceiver; 3-state XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm SOT886 b 1 2 3 4× (2) L L1 e 6 5 4 e1 e1 6× A (2) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A (1) max A1 max b D E e e1 L L1 mm 0.5 0.04 0.25 0.17 1.5 1.4 1.05 0.95 0.6 0.5 0.35 0.27 0.40 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT886 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 04-07-15 04-07-22 MO-252 Fig 11. Package outline SOT886 (XSON6) 74AVCH1T45_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 25 October 2007 19 of 22 74AVCH1T45 NXP Semiconductors Dual supply translating transceiver; 3-state 15. Abbreviations Table 18. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 16. Revision history Table 19. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AVCH1T45_1 20071025 Product data sheet - - 74AVCH1T45_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 25 October 2007 20 of 22 74AVCH1T45 NXP Semiconductors Dual supply translating transceiver; 3-state 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 17.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 18. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: [email protected] 74AVCH1T45_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 25 October 2007 21 of 22 74AVCH1T45 NXP Semiconductors Dual supply translating transceiver; 3-state 19. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 13.1 13.2 13.3 13.4 14 15 16 17 17.1 17.2 17.3 17.4 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Application information. . . . . . . . . . . . . . . . . . 15 Unidirectional logic level-shifting application. . 15 Bidirectional logic level-shifting application. . . 16 Power-up considerations . . . . . . . . . . . . . . . . 17 Enable times . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 20 Legal information. . . . . . . . . . . . . . . . . . . . . . . 21 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Contact information. . . . . . . . . . . . . . . . . . . . . 21 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 25 October 2007 Document identifier: 74AVCH1T45_1