BL7431A 256-Bit EEPROM Logical Encrypted Chip Description Pin Diagram BL7431A is the memory card chip developed by Shanghai Belling Co.,Ltd.. The chip uses Shanghai Belling’s 1.2um CMOS & EEPROM process. It has 256 bits EEPROM(A type) or 512 bits EEPROM(B type) with logical encryption function, its contact configuration is in accordance to ISO standard 78163(Synchronous Transmission). It can be used widely in intelligent public telephone area. V CC C1 C5 GND RST C2 C6 N.C. CLK C3 C7 I/O Features 2 2 256X 1bit E PROM(A Type)；512 X 1bit E PROM(B Type) Read and write by bit, erase by byte Logical encryption ensure the security of data and password Typical EEPROM program time is 5ms Operation Voltage：5V Operation Current：<1mA 5 Minimal Erase/Write Cycle：10 Data Retention: no less than 10 year In accordance to ISO standard 7816-3(Synchronous Transmission) Pin Description Pin No. 1 2 3 4 5 6 Parameter C1 C2 C3 C5 C6 C7 Symbol VCC RST CLK GND N.C. I/O Test Condition Supply Voltage Control input (reset signal) Clock input Ground Not connected Bidrectional data line (open drain) Function Description Block Diagram http://www.belling.com.cn -1Total 4 Pages 8/16/2006 BL7431A 256-Bit EEPROM Logical Encrypted Chip Partition of EEPROM Memory Function Type Address Before personalize （transmissio n password not verified） Before personalize （Transmissio n password verified） After personalize Second password not verified Function Second password verified Area1 0~15 ROM ROM ROM Area2 16~23 ROM PROM ROM Area3 Area4 24~63 64 65~71 ROM ROM ROM PROM PROM PROM ROM ROM ROM 72~79 PROM EEPROM ROM 80~103 ROM(can not be read) EEPROM ROM Area5 Area6 104~143 144 145~151 ROM ROM ROM EEPROM EEPROM EEPROM Area7 152~159 ROM Area8 160~183 ROM EEPROM Area9 184~255 ROM EEPROM Area10 256~511 ROM EEPROM http://www.belling.com.cn EEPROM ROM ROM PROM ROM （can not be read） ROM （can not be read） -2Total 4 Pages FG=1 EEPROM EEPROM EEPROM Chip Manufacture Code Card Manufacture Code Issue Code Personalized Flag Used as error counter before personalization Store the transmission password before personalization After personalization, used as common memory Issue Extend Code FG Flag EEPROM Second Error Counter EEPROM Password of User Data EEPROM User Data EEPROM User Data(only in BL7431B ) 8/16/2006 BL7431A 256-Bit EEPROM Logical Encrypted Chip Read/Write Operation Reading Operation The address counter inside the chip use bit as counter-unit, at every clock’s rising edge, it increases 1. At the falling edge of every clock, data in current address will be sent to I/O port. When CLK is high and RST also is high, the address counter will be cleared to zero. ts tR RST RST td1 tr tf CLK tH tL td3 CLK td7 tHW td4 IO DO1 DO0 Add td6 td5 td2 A0 A1 Add n IO n n+1 n+2 n+1 A2 n+1 Address reset and data output writing operation timing diagram Writing Operation When RST is high and CLK is low, “R” flag inside the chip will be set. Under such condition, when next CLK arrived, the chip will enter writing process with address counter no increasing. During writing operation, CLK keep high. When writing operation is finished, at the falling edge of CLK, address counter will be effective again, at the same time, “R” flag will be reset. To chip manufacture area, “R” flag has no use. Erasing Operation When writing operation is finished, if again comes a “RST pulse” and CLK keep low, “R” flag will be set again and the chip enter erasing status. Such operation to any bit of same byte has same effect. To PROM area, erase is invalid. tS tS RST td7 td6 CLK tHW Add n tHE n+1 n n IO n Erasing operation timing diagram Power on reset Address is reset after power on. At this time, RST must keep high than one CLK period. When RST goes low, data in address zero will be sent to I/O port. About Comparison of Transmission Password Password comparison must be executed immediately after write “0” operation RST tHW CLK ADDRESS 0 1 EC(LSB-1) ~EC(MSB-1) EC bit addr 80 td8 I/O D0 Bit output Write one bit EC D8 0 81 td9 D8 1 82 D8 2 103 td10 D103 104 Comparison of Transmission Password timing diagram http://www.belling.com.cn -3Total 4 Pages 8/16/2006 BL7431A 256-Bit EEPROM Logical Encrypted Chip Electrical Parameter Absolute Maximum Parameter Parameter Symbol Power Voltage Input Voltage Storage Temperature ESD Protection Power dissipation VCC VI TS Vs Ptot - Unit Max 6.0 6.0 125 V V ℃ V mW 50 DC Characteristic Parameter Min Limited Value Typ Max VH 3.5 - VCC V VL - - 0.8 V IH -I L IL IH CI VCC ICC 4.75 - 5 1 1 1 0.5 10 10 5.5 - µA µA mA µA pF V mA Symbol H Input Voltage (I/O,CLK,RST) L Input Voltage (I/O,CLK,RST) RST,CLK H Input Current RST,CLK L Input Current L Output Current H Output Current Input Capacitance Power Voltage Power Current Limited Value Typ 4000 - Min -0.3 -0.3 -40 Unit AC Characteristic Parameter Symbol Clock Frequency Clock H Level Clock L Level Rise Time Fall Time Reset Hold Time Writing Time Erasing Time http://www.belling.com.cn CLK tH tL tr tf tR tS tHW tHE Min Limited Value Typ Max 50 10 10 1 1 50 10 5 5 -4Total 4 Pages Unit KHz µs µs µs µs µs µs ms ms 8/16/2006