BL1302A57/S

BL1302A57/S
General Description
The BL1302A57/S is an A-law
monolithic PCM
Pin Assignment
CODEC/filter which has the A/D and D/A
conversion and a serial PCM interface. The device is
1
16
VFXI+
GNDA
2
15
VFXI-
VFRO
3
14
GSX
VCC
4
13
TSX
FSR
5
12
FS X
DR
6
11
DX
BCLKR/CLKSEL
7
10
BCLKX
MCLKR/PDN
8
9
MCLKX
CMOS process. It is pin compatible with TP3057.
The encode portion of each device consists of an
input gain adjust amplifier, an active RC pre-filter
which eliminates very high frequency noise prior to
entering a switched-capacitor band-pass filter that
rejects signals below 200 Hz and above 3400 Hz.
Also included are auto-zero circuitry and a
BL1302A57
VBB
fabricated using the advanced double-poly nwell
companding coder which samples the filtered signal
and encodes it in the companded A-law PCM format.
The decode portion consists of an expanding
decoder, which reconstructs the
Analog signal from the companded A-law code, a low-pass filter which corrects for the sinx/x
response of the decoder output and rejects signals above 3400 Hz followed by a single-ended
power amplifier capable of driving low impedance loads. The device requires two 1.536 MHz,
1.544 MHz or 2.048 MHz transmit and receive master
clocks, which may be asynchronous;
transmit and receive bit clocks , which may vary from 64 KHz to 2.048 MHz; and transmit and
receive frame sync pulses. The timing of the frame sync pulses and PCM data is compatible with
both industry standard formats.
.
Features
•
Complete CODEC and filtering system (COMBO) including:
--- Transmit high-pass and low-pass filtering
--- Receive low-pass filter with sinx/x correction
--- Active RC noise filters
--- A-law compatible COder and DECoder
--- Internal precision voltage reference
--- Serial I/O interface
--- Internal auto-zero circuitry
•
•
16 pin DIP or SOP
Designed for ITU application
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Total 17 Pages
8/28/2006
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BL1302A57/S
•
•
•
•
±5V operation
Low power: Typical
50mW
Stand-by
3mW
Automatic power-down
TTL or CMOS compatible digital interfaces
Block Diagram
GSX
R2
14
Analog
in
15
R1
VFXI
Auto zero
logic
VFXI +
RC
active
filter
-
_
+
Switched
capacitor
band-pass filter
S/H
DAC
16
Voltage
reference
11
A/D
control logic
XMT
REG
Comparator
VFRO
CE
OE
Switched
capacitor
low-pass
filter
3
RC
active filter
Power
amplifier
DX
6
RCV
REG
S/H
DAC
DR
CLK
CLK
Timing and control
5V
-5V
GND
1
2
VCC
VBB
13
4
GNDA
8
10
MCLKR/PDN
TSX
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9
MCLKX
-2-
Total 17 Pages
BLCKX
7
BLCKR/
CLKSEL
12
5
FSX FSR
8/28/2006
Wrote by 2006
BL1302A57/S
Pin Description
Symbol
Function
VBB
Negative power supply pin. VBB= - 5V ±5%
GNDA
Analog ground. All signals are referenced to this pin.
VFRO
Analog output of the receive power amplifier.
VCC
Positive power supply pin. Vcc= +5V±5%
FSR
Receive frame sync pulse which enables BCLKR to shift PCM data into DR.FSR is an 8kHz
pulse train.
DR
Receive data input. PCM data is shifted into DR following the FSR leading edge.
BLCLKR/CLKSEL
The bit clock which shifts data into DR after the FSR leading edge. May vary from 64kHz to
2.048 MHz. Alternatively , may be a logic input which selects either 1.536 MHz/1.544 MHz
or 2.048 MHz for master clock in synchronous mode and BCLKx is used for both transmit
and receive directions(see Table 1).
MCLKR/PDN
Receive master clock. Must be 1.536 MHz, 1.544 MHz or 2.048 MHz. In synchronous
mode, it may be needed as a power-down control. When MCLKR is connected continuously
low, MCLKx is selected for all internal timing. When MCLKR is connected continuously
high, the device is powered down.
MCLKx
Transmit master clock. Must be 1.536 MHz, 1.544 MHz or 2.048 MHz.
In synchronous
mode, it is also used as receive master clock.
FSx
Transmit frame sync pulse input which enables BCLKx to shift out the PCM data on Dx. FSx
is an 8 KHz pulse train.
BCLKx
The bit clock which shifts out the PCM data on Dx. May vary from 64 kHz to 2.048 MHz, but
must be synchronous with MCLKx.
Dx
The TRI-STATE PCM data output which is enabled by FSx.
TSx
Open drain output which pulses low during the encoder time slot.
GSx
Analog output of the transmit input amplifier. Used to externally set gain.
VFx I-
Inverting input of the transmit input amplifier.
VFx I+
Non-inverting input of the transmit input amplifier.
Functional Description
•
Power-up
When power is first applied, the internal power-on reset circuitry initializes the device and places
it into a power-down state. Most of the analog and digital circuits are deactivated, and the DX
and VFRO outputs are put in high impedance states. To power-up the device, a logical low level
or clock must be applied to the MCLKR/PDN pin and FSx and/or FSR pulses must be present.
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BL1302A57/S
Thus, 2 power-down control modes are available. The first is to pull the MCLKR/PDN pin high;
the alternative is to hold both FSX and FSR input continuously low---the device will power-down
approximately 2 ms after the last FSX or FSR pulse. Power-up will occur on the first FSx or FSR
pulse. The TRI-STATE PCM data output, Dx, will remain in the high impedance state until the
second FSx pulse.
• Synchronous operation
For synchronous operation, the same master clock should be used for both the transmit and
receive directions. In this mode , a clock must be applied to MCLKx and the MCLKR/PDN pin
can be used as a power-down control. A low level on MCLKR/PDN powers up the device and a
high level powers down the device. In either case, MCLKx will be selected as the master clock
for both the transmit and receive circuits. A bit clock must also be applied to BCLKx and the
BCLKR/CLKSEL can be used to select the proper internal divider for a master clock of 1.536
MHz, 1.544MHz or 2.048MHz. For 1.544MHz operation, the device automatically compensates
for the 193rd clock pulse each frame.
With a fixed level on the BCLKR/CLKSEL pin, BCLKx will be selected as the bit clock for both
the transmit and receive directions. Table 1 indicates the frequencies of operation which can be
selected, depending on the state of BCLKR/CLKSEL . In this synchronous mode, the bit clock,
BCLKx and BCLKR, may be from 64kHz to 2.048 MHz. The frequency of BCLKx and BCLKR
are not necessary to be equal, but must be synchronous with MCLKx.
Each FSx pulse begins the encoding cycle and the PCM data from the previous encode cycle is
shifted out of the enabled Dx output on the positive edge of BCLKx. After 8 bit clock periods,
the TRI-STATE Dx output is returned to a high impedance state. With an FSR pulse, PCM data is
latched via the DR input on the negative edge of BCLKx (or BCLKR if running ). FSx and FSR
must be synchronous with MCLKX/R .
Table Selection of Master Clock Frequencies
•
BCLKR/CLKSEL
Master Clock Frequency Selected
Clocked
2.048MHz
0
1.536MHz or 1.544MHz
1
2.048MHz
Short frame operation
The device can utilize either a short frame sync pulse or a long frame sync pulse. Upon power
initialization, the device assumes a short frame mode. In this mode, frame sync pulse, FSx and
FS R , must be one bit clock period long, with timing relationships specified in Figure 1. With
FSx high during a falling edge of BCLKx, the next rising edge of BCLKx enables the Dx
TRI-STATE output buffer, which will output the sign bit. The following seven rising edges clock
out the remaining seven bits, and the next falling edge disables the Dx output. With FS R high
during a falling edge of BCLK R (BCLKx, if BCLKR is a fixed level), the next falling edge
of BCLK R latches in the sign bit. The following seven falling edges latch in the seven remaining
bits.
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BL1302A57/S
• Long frame operation
To use the long frame mode, the frame sync pulse, FSx and FS R , must be three or more bit clock
periods long, with timing relationships specified in Figure 2. Based on the transmit frame sync,
FSx, the device will sense whether short or long frame sync pulse are being used. For 64 kHz
operation, the frame sync pulse must be kept low for a minimum of 160ns. The Dx tri-state
output buffer is enabled with the rising edge of FSx or the rising edge of BCLKx , whichever
comes later, and the first bit clocked out is the sign bit. The following seven BCLKx rising edges
clock out the remaining seven bits. The Dx output is disabled by the falling BCLKx edge
following the eighth rising edge, or by FSx going low, whichever comes later. A rising edge on
the receive frame sync pulse, FS R, will cause the PCM data at DR to be latched in on the next
eight falling edges of BCLK R (BCLKx if BCLKR is a fixed level ).
•
Single channel operation
Keeping FSR input continuously low, the device enters into transmit channel operation, the
data at DR input will be ignored. Keeping FSX input continuously low, the device enters into
receive channel operation. The most part of transmit circuitry ceases to work, DX and TSX
output will be in high impedance. If MCLKR input is a clock, it is the internal master clock. If
MCLKR input is not a clock, MCLKX is the internal master clock, and MCLKX must be
synchronous with FSR. If BCLKR input is not a clock, BCLKX is the internal bit clock. In receive
channel operation, the length of FSR determines whether it is short or long frame.
•
Switch of operation
See picture below, it is not recommended that the switching from both channels to receive only or
switching from receive channel only to transmit channel only.
transmit
POWER
DOWN
both
receive
•
Transmit section
The transmit section input is an operational amplifier with provision for gain adjustment using
two external resistors. The low noise and wide bandwidth allow gains in excess of 20 dB across
the audio passband to be realized. The op amp drives a unity-gain filter consisting of RC active
pre-filter, followed by an eighth order switched-capacitor bandpass filter clocked at 256 kHz.
The output of this filter directly drives the encoder sample-and-hold circuit. The A/D is of
companding type according to A-law coding conventions. A built-in bandgap voltage reference is
used to provide an input overload of nominally 2.492V peak. The FSx frame pulse controls the
sampling of the filter output, and then the successive-approximation encoding cycle begins. The
8-bit code is then loaded into a buffer and shifted out through Dx at the next FSx pulse. The total
encoding delay will be approximately 165us (due to transmit filter) plus 125us (due to encoding
delay), which totals 290us. Any offset voltage due to the filters or comparator is cancelled by
sign bit integration.
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Total 17 Pages
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BL1302A57/S
•
Receive section
The receive section consists of an expanding DAC which drives a fifth order switched-capacitor
low pass filter clocked at 256 kHz. The decoder is A-law and the 5th order low pass filter
corrects for the sinx/x attenuation due to the 8 kHz sample/hold. The filter is then followed by a
2nd order RC active post-filter/power amplifier capable of driving a 600ohm load to a level of
7.2 dBm. The receive section is unity-gain. Upon the occurrence of FS R , the data at the D R input
is clocked in on the falling edge of the next eight BCLK R (BCLKx) periods. At the end of the
decoder time slot, the decoding cycle begins. The total decoder delay approximately 280 us.
Electrical parameters and timing
Absolute Maximum Ratings
Rating
Value
Unit
V CC to GNDA
7
V
V BB to GNDA
-7
V
Voltage at any Analog Input or Output
VCC+0.3 to VBB-0.3
V
Voltage at any Digital Input or Output
VCC+0.3 to GNDA-0.3
°C
Operating Temperature Range
-25 to +125
°C
Storage Temperature Range
-65 to +150
°C
ESD (Human Body Model)
1000
V
Latch-Up Immunity at any Pins
100
mA
Electrical Characteristics: VCC = +5.0V±5%, VBB = -5.0V±5%, TA = 0°C to +70°C. All
signals referenced to GNDA. Typicals specified at VCC = +5.0V, VBB =
Symbol
Digital
Parameter
Conditions
-5.0V, TA = 25°C.
Min
Typ
Max
Units
INTERFACE
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
0.6
2.2
V
V
Dx, IL=3.2mA
0.4
V
TSx, IL=3.2mA, Open Drain
0.4
V
VOH
Output High Voltage
Dx, IH= - 3.2mA
2.4
V
IIL
Input Low Current
GNDA≤VIN≤VIL,All digital inputs
-10
10
µA
IIH
Input High Current
VIH≤VIN≤Vcc
-10
10
µA
IOZ
Output Current in High
Dx, GNDA≤V O≤Vcc
-10
10
µA
Impedance State
(TRI-STATE)
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BL1302A57/S
Ananalog Interface with transmit input amplifier
I IXA
Input Leakage Current
-2.5V≤V≤+2.5V, VFxI+ or VFxI-
-200
200
nA
R IXA
Input Resistance
-2.5V≤V≤+2.5V, VFxI+ or VFxI-
10
R OXA
Output Resistance
Closed Loop, Unity Gain
R LXA
Load Resistance
GSx
C LXA
Load Capacitance
GSx
V OXA
Output Dynamic Range
GSx, RL ≥10kΩ
-2.8
A VXA
Voltage Gain
VFxI+ to GSx
5000
F UXA
Unity Gain Bandwidth
1
V OSXA
Offset Voltage
-20
20
mV
V CMXA
Common-Mode Voltage
CMRRXA>60dB
-2.5
2.5
V
CMRRXA
Common-Mode Rejection
DC Test
60
dB
DC Test
60
dB
MΩ
1
Ω
3
10
kΩ
50
pF
2.8
V
V/V
2
MHz
Ratio
PSRRXA
Power
Supply
Rejection Ratio
ANALOG INTERFACE WITH RECEIVE FILTER
R ORF
Output Resistance
Pin VF R O
R LRF
Load Resistance
VF RO=±2.5V
CLRF
Load Capacitance
VOS RO
Output
DC
1
Ω
3
Ω
600
-200
500
pF
200
mV
Offset Voltage
POWER DISSIPATION
I CC0
Power-Down Current
No Load (Note)
0.14
0.3
mA
I BB0
Power-Down Current
No Load(Note)
0.20
1.5
mA
ICC1
Power-Up
Active
No Load
5.0
10
mA
Active
No Load
5.0
10
mA
Current
IBB1
Power-Up
Current
Note: Icc0 and I BB0 are measured after first achieving a power-up state.
Timing Specifications: VCC =+5.0±5%, VBB = -5.0±5%, Ta = 0°C ~+70 °C. All signals
referenced to GNDA. Typicals specified at VOH =+5.0V, VBB = -5.0V, TH = 25°C. All timing
parameters are assured at VOH =2.0V and VOL = 0.7V.
Symbol
Parameter
Conditions
1/tPM
Frequency of Master Clock
Depends on
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Total 17 Pages
Min
Typ
1.536
Max
Units
MHz
8/28/2006
Wrote by 2006
BL1302A57/S
tRM
Rise Time of
tFM
Fall Time of Master Clock
tPB
Period of
tRB
Rise Time of Bit Clock
tFB
Fall Time of
tWMH
Width of
tWML
tSBFM
tSFFM
Master Clock
BCLK R/CLKSEL Pin.
1.544
MHz
MCLKx and MCLK R
2.048
MHz
MCLKx and MCLKR
50
ns
MCLKx and MCLKR
50
ns
15725
ns
BCLKx and BCLKR
50
ns
BCLKx and BCLKR
50
ns
Bit Clock
Bit Clock
Master Clock High
485
488
MCLKx and MCLK R
160
ns
Width of Master Clock Low
MCLKx and MCLK R
160
ns
Set-Up Time from BCLKx High
First Bit Clock after the
100
ns
to MCLKx Falling Edge
Leading Edge of
Set-up Time from FSx High
Long Frame Only
100
ns
FSx
to MCLKx Falling Edge
t WBH
Width of Bit Clock High
VIH=2.2V
160
ns
t WBL
Width of Bit Clock Low
VIL=0.6V
160
ns
t HBFL
Holding Time from Bit Clock
Long Frame Only
0
ns
Short Frame Only
0
ns
Long Frame Only
80
ns
Load=150 pF plus
0
140
ns
0
140
ns
CL=0 pF to 150 pF
50
165
ns
CL=0 pF to 150 pF
20
165
ns
Low to Frame Sync
t HBFS
Holding Time from Bit Clock
High to Frame Sync
t SFB
Set-Up Time from Frame Sync
to Bit Clock Low
t DBD
Delay Time from BCLKx High
to Data Valid
t DBTS
Delay Time to TSx
2 LSTTL
Low
Load=150 pF plus
2 LSTTL Loads
t DZC
Delay Time from BCLKx Low to
Data Output Disabled
t DZF
Delay Time to Valid Data from
FSx or BCLKx, Whichever
Comes Later
t SDB
Set-Up time from DR Valid to
50
ns
50
ns
50
ns
BCLK R/ X Low
t HBD
Hold Time from BCLKR/X Low to
D R Invalid
tSF
Set-Up Time from FSX/R to
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Short Frame Sync Pulse
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BL1302A57/S
BCLK X/R
t HF
t HBFI
t WFL
Low
(1 Bit Clock Period Long)
Hold Time from BCLKX/R Low to
Short Frame Sync Pulse
FS X/R
(1 bit Clock Period Long)
Low
Hold Time from 3rd Period of Bit
Long Frame Sync Pulse
Clock Low to Frame Sync
(from 3 to 8 Bit Clock
(FSx or FS R)
Periods Long)
Minimum Width of the Frame
64K Bit/s Operating Mode
100
ns
100
ns
160
ns
Sync Pulse (Low Level)
Timing diagrams
Figure 1. Short Frame Sync Timing
tDBTS
TSX
tDZC
tFM
tRM
tWML
MCLKR
MCLKX
BCLKX
tWMH
t
tSBFMPM
1
tHBFS
2
3
4
5
6
7
8
tHF
tSF
FSX
1
DX
BCLKR
FSR
tHBFS
tSF
1
tHF
2
2
tDBD
4
3
3
4
tDZC
5
5
6
6
7
tSDB
DR
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2
3
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Total 17 Pages
4
5
7
8
8
tHBD
6
7
tHBD
8
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BL1302A57/S
Figure 2. Long Frame Sync Timing
tRM
tWML
tPM
tFM
MCLKX
MCLKR
tSFFM
tSBFM
tWMH t tWBH
tWBL
FB
1
BCLKX
tHBFL
2
tRB
tSFB
FSX
3
tPB
4
5
tDZF
7
8
tDZC
tDBD
1
9
tHBFI
tDZF
DX
6
2
3
4
5
6
7
8
tDZF
BCLKR
1
tHBFL
2
tSFB
3
4
5
6
7
8
tHBFI
FSR
tSDB
1
DR
2
tHBD
tHBD
3
4
5
6
7
8
Transmission Characteristics: VCC = +5.0V±5%, VBB = -5.0V±5%, GNDA=0V,TA = 0°C to
+70 °C, f=1.02kHz, Vin=0dBm0, transmit input amplifier connected for unity gain inverting.
Typicals are specified at VCC = +5V, VBB = -5.0V, TA = 25°C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Amplitude resopnse
Absolute Levels
Nominal 0 dBm0 Level is
(Definition
4 dBm(600Ω)
0 dBm0
1.2276
Vrms
2.492
VPK
of Nominal Gain)
tMAX
Virtual Decision Valve Defined Per CCITT Rec.
Max Overload Level
(3.14 dBm0)
G711
GXA
Transmit Gain, Absolute
TA=25 0C,Vcc=5V,
VBB= -5V Input at
Gsx=0 dBm0 at 1020 Hz
GXR
-0.25
0.25
dB
Transmit Gain, Relative to
f=16Hz
-40
dB
GXA
f=50Hz
-30
dB
f=60Hz
-26
dB
-0.1
dB
f=200Hz
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BL1302A57/S
f=300Hz-3000Hz
-0.15
0.15
dB
f=3300Hz
-0.35
0.05
dB
f=3400Hz
-0.7
0
dB
f=4000Hz
-14
dB
f=4600Hz and Up, Measure
-32
dB
Response from 0 Hz to 4000 Hz
GXAT
Absolute Transmit Gain
Relative to GXA
-0.1
0.1
dB
Relative to GXA
-0.05
0.05
dB
VFxI+=-40dBm0 to +3dBm0
-0.2
0.2
dB
VFxI+=-50dBm0 to-40dBm0
-0.4
0.4
dB
VFxI+=-55dBm0 to-50dBm0
-1.2
1.2
dB
-0.25
0.25
dB
Variation with Temperature
GXAV
Absolute Transmit Gain
Variation with Supply
Voltage
GXRL
GRA
Transmit Gain Variations
Sinusoidal Test Method
with Level
Reference Level=-10dBm0
Receive Gain, Absolute
TA=25 0C,Vcc=5V,VBB=-5V
Input=Digital Code Sequence for 0 dBm0 Signal at
1020 Hz
GRR
Receive Gain, Relative to
f=0Hz to 3000 Hz
-0.15
0.15
dB
GRA
f=3300Hz
-0.35
0.05
dB
f=3400Hz
-0.7
0
dB
-14
dB
f=4000Hz
GRAT
Absolute Receive Gain
Variation
Relative to GRA
-0.1
0.1
dB
Relative to GRA
-0.05
0.05
dB
with Tempera-
ture
GRAV
Absolute Receive Gain
Variation with Supply
Voltage
GRRL
Receive Gain Variations
Sinusoidal Test Method;
with Level
Reference Input PCM Code
Corresponds to an Ideally
Encoded PCM Level
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BL1302A57/S
VRO
Receive Output Drive Level
=-40 dBm0 to +3 dBm0
-0.2
0.2
dB
=-50 dBm0 to -40 dBm0
-0.4
0.4
dB
=-55 dBm0 to -50 dBm0
-1.2
1.2
dB
RL=600Ω
-2.5
2.5
V
Envelope delay distortion with frequency
DXA
Transmit Delay, Absolute
f=1600 Hz
290
315
us
DxR
Transmit Delay, Relative to
f=500 Hz - 600 Hz
195
220
us
DXA
f=600 Hz - 800 Hz
120
145
us
f=800 Hz - 1000 Hz
50
75
us
f=1000 Hz - 1600 Hz
20
40
us
f=1600 Hz - 2600 Hz
55
75
us
f=2600 Hz - 2800 Hz
80
105
us
f=2800 Hz - 3000 Hz
130
155
us
270
290
us
DRA
Receive Delay, Absolute
f=1600 Hz
DRR
Receive Delay, Relative to
f=500 Hz - 1000 Hz
-40
-25
us
DRA
f=1000 Hz - 1600 Hz
-30
-20
us
f=1600 Hz - 2600 Hz
70
90
us
f=2600 Hz - 2800 Hz
100
125
us
f=2800 Hz - 3000 Hz
145
175
us
-74
-67
dBm0p
-82
-79
dBm0p
-53
dBm0
Noise
NXP
Transmit Noise, P
Message Weighted
NRP
Receive Noise, P
PCM Code Equals Positive Zero
Message Weighted
NRS
Noise, Single Frequency
f=0kHz to 100 kHz, Loop
Around Measurement,
VFxI+=0 Vrms
PPSRx
Positive Power Supply
VFxI+= -50 dBm0
Rejection, Transmit
Vcc=5.0 VDC+100 mVrms
f=0 kHz - 50 kHz (Note 2)
NPSRx
Negative
Power
Supply
Rejection, Transmit
Positive Power Supply
Rejection, Receive
dBC
40
dBC
VFxl+= -50 dBm0
Vcc=-5.0 VDC+100 mVrms
f=0 kHz - 50 kHz (Note 2)
PPSRR
40
PCM
Code
Equals
Positive
Zero,Vcc=5.0VDC+100mVrms
Measure VFRO
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Wrote by 2006
BL1302A57/S
NPSRR
Negative
Power
Supply
f=0 Hz - 4000 Hz
40
dBC
f=4 kHz - 25 kHz
40
dB
f=25 kHz - 50 kHz
36
dB
f=0 Hz - 4000 Hz
40
dBC
f=4 kHz - 25 kHz
40
dB
f=25 kHz - 50 kHz
36
dB
PCM
code
Equals
Positive
Zero,VBB=-5.0VDC+100mVrms
Rejection, Receive
Measure VFRO
SOS
Spurious
Signals
Out-of-Band
at
the
Channel
Output
Loop Around Measurement, 0
dBm0, 300 Hz to 3400 Hz Input
PCM Code Applied at DR.
4600 Hz - 7600 Hz
7600 Hz - 8400 Hz
-30
dB
8400 Hz - 100,000 Hz
-40
dB
-30
dB
Distortion
STDx
Signal to Total Distortion
Sinusoidal Test Method
STDR
Transmit or Receive
(Note 3)
Half-Channel
Level=3.0 dBm0
=0 dBm0 to - 30
dBm0
=-40 dBm0 XMT
RCV
=-55 dBm0
33
dBC
36
dBC
29
dBC
30
dBC
14
dBC
15
dBC
XMT
RCV
SFDx
Single Frequency Distor-
-46
dB
-46
dB
-41
dB
tion, Transmit
SFDR
Single frequency Distortion,
Receive
IMD
Intermodulation Distortion
Loop Around Measurement,
VFx+=-4dBm0 to -21 dBm0,
Two Frequencies in the
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Total 17 Pages
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BL1302A57/S
Range 300 Hz-3400Hz
Crosstalk
CTx-R
Transmit
to Receive
Crosstalk, 0 dBm0
CTR-x
f=300Hz-3400Hz
DR=Quiet PCM Code
Transmit Level
(Note 2)
Receive to Transmit
f=300Hz-3400Hz,
Crosstalk, 0 dBm0
VFxI=Multitone (Note1)
-90
-75
dB
-90
-70
dB
Receive Level
Note 1: Measured by extrapolation from the distortion test result at -50 dBm0.
Note 2: PPSRx, NPSRx, and CTR-X are measured with a -50 dBm0 activation signal applied to VFxl+ .
Note 3: Device is measured using psophometric-weighted filter.
Encoding Format at Dx Output
Vin (at GSx) = +Full-Scale
1
0
Vin (at GSx) = 0V
1
1
0
1
Vin (at GSx) = -Full-Scale
0
0
0
1
0
1
0
0
1
0
1
0
1
1
0
1
1
1
1
0
0
0
1
0
1
0
Applications Information
Power supplies
While the pins of the device are well protected against electrical misuse, it is recommended that
ground is connected to the device before any other connections are made. In applications where
the printed circuit board may be plugged into a “hot” socket with power and clocks already
present, an extra long ground pin in the connector should be used.
All ground connections to each device should meet at a common point as close as possible to the
GNDA pin. This minimizes the interaction of ground return currents flowing through a common
bus impedance. 0.1 µF supply decoupling capacitors should be connected from this common
ground point to Vcc and VBB, as close to the device as possible.
For best performance, the ground point of each CODEC/FILTER on a card should be connected
to a common card ground in star formation, rather than via a ground bus.
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BL1302A57/S
This common ground point should be decoupled to Vcc and VBB with 10µF capacitors.
Receive gain adjustment
For applications where a device CODEC/filter receive output must drive a 600Ω load, but a peak
swing lower than ±2.5V is required, the receive gain can be easily adjusted by inserting a
matched T-pad or π-pad at the output. The followed table lists the required resistor values for
600Ω terminations. As these are generally non-standard values, the equations can be used to
compute the attenuation of the closest practical set of resistors. It may be necessary to use
unequal values for the R1 or R4 arms of the attenuators to achieve a precise attenuation.
Generally it is tolerable to allow a small deviation of the input impedance from nominal while
still maintaining a good return loss.
Attenuator diagram and table
T-Pad attenuator
300
R1
R1
Z1
R2
1:
2
Z2
600
π - Pad attenuator
300
Z1
R3
R4
1:
R4
Z2
2
600
Where
R 1= Z1
N 2+ 1
N
-2 Z 1Z 2
N 2-1
N 2-1
N=
P ow er in
P ow er out
N
S=
Z1
Z2
R 2= 2 Z1Z 2
R 3=
Z 1Z 2
2
2
N -1
2
( NN -1 )
N 2-1
R 4= Z1 (N 2 -2N S+ 1
Z=
Z SC Z O C
Z SC = inpedance w ith short circuitterm ination
)
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Z O C = inpedance w ith open circuitterm ination
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Total 17 Pages
8/28/2006
Wrote by 2006
BL1302A57/S
Attenuator Table for Z1=Z2=300W, all values in W
dB
R1
R2
R3
R4
dB
R1
R2
R3
R4
0.1
1.7
26k
3.5
52k
6
100
402
224
900
0.2
3.5
13k
6.9
26k
7
115
380
269
785
0.3
5.2
8.7k
10.4
17.4k
8
379
284
317
698
0.4
6.9
6.5k
13.8
13k
9
143
244
370
630
0.5
8.5
5.2k
17.3
10.5k
10
156
211
427
527
0.6
10.4
4.4k
21.3
8.7k
11
168
184
490
535
0.7
12.1
3.7k
24.2
7.5k
12
180
161
550
500
0.8
13.8
3.3k
27.7
6.5k
13
190
142
635
473
0.9
15.5
2.9k
31.1
5.8k
14
200
125
720
450
1.0
17.3
2.6k
34.6
5.2k
15
210
110
816
430
2
34.4
1.3k
70
2.6k
16
218
98
924
413
3
51.3
850
107
1.8k
18
233
77
1.17k
386
4
68
650
144
1.3k
20
246
61
1.5k
366
5
84
494
183
1.1k
Typical synchronous application
-5V
0.1µF
1
VFXI + 16
VBB
-
2
GNDA
To SLIC
3
VFRO
+5V
4
VCC
5
FSR
6
DR
7
BCLKR/CLKSEL
BCLKX 10
8
MCLKR/PDN
MCLKX 9
VFXI
15
0.1µF
5V or GNDA
PDN
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From SLIC
BL1302A57
R1
R2
GSX 14
TSX 13
FSX 12
DX 11
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Total 17 Pages
ö
2.048MHz/1.544MHz
8/28/2006
Wrote by 2006
BL1302A57/S
Print Information
Physical Dimensions inches (millimeters)
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