1 CHIP CODEC S5T8554B/7B INTRODUCTION 16-CERDIP The S5T8554B/7B are single-chip PCM encoders and decoders (PCM CODECs) and PCM line filters. These devices provide all the functions required to interface a full-duplex voice telephone circuit with a time-division-multiplex (TDM) system. These devices are designed to perform the transmit encoding and receive decoding as well as the transmit and receive filtering functions in PCM system. They are intended to be used at the analog termination of a PCM line or trunk. These devices provide the bandpass filtering of the analog signals prior to encoding and after decoding. These combination devices perform the encoding and decoding of voice and call progress tones as well as the signalling and supervision information. 16-DIP-300A 8−DIP−300 FEATURES • Complete CODEC and filtering system • Meets or exceeds AT&T D3/D4 and CCITT specifications µ-Law: S5T8554B, A-Law: S5T8557B • On-chip auto zero, sample and hold, and precision voltage references • Low power dissipation: 60mW (operating), 3mW (standby) • ± 5V operation • TTL or CMOS compatible • Automatic power down ORDERING INFORMATION Device Package Operating Temperature S5T8554B02-L0B0 S5T8557B02-L0B0 16-CERDIP −25°C to 125°C S5T8554B01-D0B0 S5T8557B01-D0B0 16-DIP-300A −25°C to +70°C S5T8554B01-S0B0 S5T8557B01-S0B0 16-SOP-BD300 −25°C to +70°C 1 S5T8554B/7B 1 CHIP CODEC PIN CONFIGURATION V BB 1 16 VFXI+ GNDA 2 15 VFXI- VFRO 3 14 GSX V CC 4 13 TSX KT8554/7 S5T8554B/7B FSR 5 12 FSXS DR 6 11 DX BCLKR/CLKSEL 7 10 BCLKX MCLKR/PDN 8 9 MCLK X PIN DISCRIPTION 2 Pin No Symbol 1 VBB VBB = −5V ± 5% 2 GNDA Analog ground. 3 VFRO Analog output of the receive power Amp. 4 VCC VCC = +5 V ± 5% 5 FSR Receive frame sync pulse. 8kHz pulse train 6 DR PCM data input. 7 BLCKR/ CLKSEL Logic input which selects either 1.536MHz/1.544MHz or 2.048MHz for master clock in normal operation and BCLKX is used for both TX and RX directions. Alternately direct clock input available, vary from 60kHz to 2.048MHz. 8 MCLKR/ PDN When MCLK R is connected continuously high, the device is powered down. Normally connected continuously low, MCLKX is selected for all DAC timing. Alternately direct 1.536MHz/1.544MHz or 2.048MHz clock input available. 9 MCLKX Must be 1.536MHz/1.544MHz or 2.048MHz. 10 BLCKX May be vary from 64kHz to 2.048MHz but BCLKX is externally tied with MCLKX in normal operation. 11 DX PCM data output. 12 FSX TX frame sync pulse. 8kHz pulse train. 13 TSX Changed from high to low during the encoder timeslot. Open drain output. 14 GSX Analog output of the TX input amplifier. Used to set gain through external resistor. − 15 VFXI 16 VFXI+ Description Inverting input stage of the TX analog signal. Non-inverting input stage of the TX analog signal. 1 CHIP CODEC S5T8554B/7B ABSOLUTE MAXIMUM RATING Characteristic Symbol Value Unit Positive Supply Voltage VCC 7 V Negative Supply Voltage VBB −7 V Voltage at Any Analog Input or Output VI (A) VCC + 0.3 ~ VBB - 0.3 V Voltage at Any Digital Input or Output VI (D) VCC + 0.3 ~ GNDA - 0.3 V Ta −25 ~ +125 °C Storage Temperature Range TSTG −65 ~ +150 °C Lead Temperature (Soldering, 10 secs) TLEAD 300 °C Operating Temperature Range ELECTRICAL CHARACTERISTICS (Unless otherwise noted, VCC = 5.0V ± 5%, VBB = −5.0V ± 5%, GNDA = 0V, Ta = 0°C to 70°C; typical characteristics specified at VCC = 5.0V, VBB = −5.0V, Ta=25°C; all signals referenced to GNDA) Characteristic Symbol Test Conditions Min. Typ. Max. Unit POWER DISSIPATION Power-Down Current ICC (DOWN) No Load − 0.5 1.5 mA Power-Down Current IBB (DOWN) No Load − 0.05 0.3 mA Active Current ICC (A) No Load − 6.0 9.0 mA Active Current IBB (A) No Load − 6.0 9.0 mA DIGITAL INTERFACE Input Low Voltage VIL − − − 0.6 V Input High Voltage VIH − 2.2 − − V Input Low Current IIL GNDA≤ VIN ≤ VIL, all digital input −10 − 10 µA Input High Current IIH VIH ≤ VIN ≤ VCC −10 − 10 µA − − 0.4 0.4 0.4 V V V Output Low Voltage VOL DX, IL = 3.2mA SIGR, IL = 1.0mA TSX, IL = 3.2mA, open drain Output High Voltage IO (HZ) DX, IH = −3.2mA SIGR, IH = −1.0mA 2.4 2.4 − − V V Output Current in High Impedance State (Tri -state) IO (HZ) DX, GNDA ≤ VO ≤ VCC −10 − 10 µA − 1 3 Ω ANALOG INTERFACE WITH RECEIVE FILTER Output Resistance RO Pin VFRO 3 S5T8554B/7B 1 CHIP CODEC ELECTRICAL CHARACTERISTICS (Unless otherwise noted, VCC = 5.0V ± 5%, VBB = −5.0V ± 5%, GNDA = 0V, Ta = 0°C to 70°C; typical characteristics specified at VCC = 5.0V, VBB = −5.0V, Ta=25°C; all signals referenced to GNDA) Characteristic Symbol Test Conditions Typ. Max. Unit 600 − − Ω Load Resistance RL Load Capacitance CL − − − 500 pF VOO (RX) − −200 − 200 mV ILKG -2.5V≤V≤+2.5V, VFXI+ or VFXI- −200 − 200 nA Input Resistance RI -2.5V≤V≤+2.5V, VFXI+ or VFXI- 10 − − MΩ Output Resistance RO Closed loop, unity gain − 1 3 Ω Load Resistance RL GSX 10 − − kΩ Load Capacitance CL GSX − − 50 pF GSX, RL≤10KW ± 2.8 − − V VFXI+ to GSX 5,000 − − V/N Output DC Offset Voltage VFRO = ± 2.5V Min. ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER Input Leakage Current Output Dynamic Range VOD (TX) Voltage Gain GV Unity Gain Bandwidth BW − 1 2 − MHz Offset Voltage VIO (TX) − −20 − 20 mV Common-Mode Voltage VCM (TX) −2.5 − 2.5 V CMRRXA > 60dB Common-Mode Rejection Ratio CMRR DC Test 60 − − dB Power Supply Rejection Ratio PSRR DC Test 60 − − dB 4 1 CHIP CODEC S5T8554B/7B TIMING CHARACTERISTICS (Unless otherwise noted, VCC = 5.0V ± 5%, VBB = −5.0V ± 5%, GNDA = 0V, Ta = 0°C to 70°C; typical characteristics specified at VCC = 5.0V, VBB = −5.0V, Ta=25°C; all signals referenced to GNDA) Characteristic Frequency of Master Clock Symbol fMCK Test Conditions Min. Typ. Max. Unit Depends on the device used and the BCLKR/CLKSEL Pin. MCLKX and MCLKR − 1.536 1.544 2.048 − nS Rise Time of Bit Clock tR (BCK) tPB = 488ns − − 50 nS Fall Time of Bit Clock tF (BCK) tPB = 488ns − − 50 nS Holding Time from Bit Clock Low to Frame Sync tH (LFS) Long frame only 0 − − nS Holding Time from Bit Clock High to Frame Sync tH (RFS) Short frame only 0 − − nS Set-Up Time from Frame Sync to Bit Clock Low tSU (FBCL) Long frame only 80 − − nS Delay Time from BCLKX High to Data Valid tD (HDV) Load = 150pF plse 2 LSTTL loads 0 − 180 nS Delay Time to TSX Low tD (TSXL) Load = 150pF plse 2 LSTTL loads − − 140 nS Delay Time from BCLKX Low to Data Output Disabled tD (LDD) 50 − 165 nS Delay Time to Valid Data from FSX or BCLKX, Whichever Comes Later tD (VD) 20 − 165 nS Set-Up Time from DR Valid to BCLKR/X Low tSU (DRBL) − 50 − − nS Hold Time from FSR/X Low to DR Invalid tH (BLDR) − 50 − − nS Set-Up Time from FSR/X to BCLKR/X Low tSU (FBLS) Short frame sync pulse (1 or 2 bit clock periods long) (Note 1) 50 − − nS Width of Master Clock High tW (MCKH) MCLKX and MCLKR 160 − − nS Width of Master Clock Low tW (MCKL) MCLKX and MCLKR 160 − − nS Rise Time of Master Clock tR (MCK) MCLKX and MCLKR − − 50 nS Fall Time of Master Clock tF (MCK) MCLKX and MCLKR − − 50 nS First bit clock after the leading edge FSX − − − − Set-Up Time from BCLKX High (and FSX In Long Frame Sync Mode) to MCLKX Falling Edge tSU (BHMF) − CL = 0pF to 150pF 5 S5T8554B/7B 1 CHIP CODEC TIMING CHARACTERISTICS (Unless otherwise noted, VCC = 5.0V ± 5%, VBB = −5.0V ± 5%, GNDA = 0V, Ta = 0°C to 70°C; typical characteristics specified at VCC = 5.0V, VBB = −5.0V, Ta=25°C; all signals referenced to GNDA) Characteristic Symbol Test Conditions Min. Typ. Max. Unit − 485 488 15,725 nS Period of Bit Clock tCK Width of Bit Clock High tW (BCKH) VIH = 2.2 160 − − nS Width of Bit Clock Low tW (BCKL) VIL = 0.6V 160 − − nS Hold Time from BCLKX/R Low to FSX/R Low tH (BLFL) Short frame sync pulse (1 or 2 bit clock periods long) (Note 1) − − − nS Hold Time from 3rd Period of Bit Clock Low to Frame Sync (FSX or FSR) tH (3rd) Long frame sync pulse (From 3 to 8 bit clock periods long) 100 − − nS Minimum Width of the Frame Sync Pulse (Low Level) tWFL 64K bit/s operating mode − − − nS NOTE: For short frame sync timing, FSX and FSR must go high while their respective bit clocks are high. 6 1 CHIP CODEC S5T8554B/7B TIMING DIAGRAM tD(TSXL) TSx tF(MCK) tR(MCK) tW(MCK) t CK MCLKR MCLKX tW(MCKH) BCLKX FSX tSU(BHMF) 1 tH(HFS) tSU(FBLS) 3 4 5 6 7 tD(LDD) tD(HDV) 1 BCLKR 1 tH(HFS) 2 2 3 3 4 4 5 5 6 6 7 7 8 8 tH(BLFL) tSU(FBLS) t tH(BLDR)H(BLDR) tSU(DRBL) DR 8 tH(BLFL) DX FSR 2 1 2 3 4 5 6 7 8 Figure 1. Short Frame Sync Timing 7 S5T8554B/7B 1 CHIP CODEC TIMING DIAGRAM (Continued) tW(MCKL) tR(MCK) tF(MCK) tCK MCLKR MCLKX tSU(BHML) BCLKX tW(MCKH) tSBFM 1 tW(BCKH) 2 tH(HFS) t SU(FBCK) tW(BCKL) tF(BCK) 3 4 5 8 9 tH(3rd) FSX tD(HDV) tD(VD) DX 7 tCK tRB tD(VD) 6 1 2 3 4 tD(LDD) 5 6 7 8 tD(VD) BCLKR 1 3 4 5 6 7 8 9 tH(HFS) tH(3rd) tSU(FBLK) FSR tSU(DRBL) tH(BLDL) tH(BLDL) DR 1 2 3 4 5 6 Figure 2. Long Frame Sync Timing 8 7 8 1 CHIP CODEC S5T8554B/7B TRANSMISSION CHARACTERISTICS (Unless otherwise specified: Ta = 0°C to 70°C, VCC = 5V ± 5%, VBB = −5V ± 5%, GNDA = 0V, f = 1.02kHz, VIN = 0dBm0, transmit input amplifier connected for unity-gain non-inverting.) Characteristic Symbol Test Conditions Min. Typ. Max. Unit AMPLITUDE RESPONSE Receive Gain, Absolute GV (ARX) Ta=25°C, VCC=5V, VBB=−5V Input = Digital code sequence for 0dBm signal at 1020Hz −0.15 − 0.15 dB Receive Gain, Relative to GV (ARX) GV (RRX) f = 0Hz to 3000Hz f = 3300Hz f = 3400Hz f = 4000Hz −0.15 −0.35 −0.7 − 0.15 0.05 0 −14 dB dB dB dB Absolute Receive Gain Variation with Temperature ∆GV (ARX) /∆T Ta = 0°C to 70°C − − ±0.1 dB VCC=5V ± 5%, VBB=−5V ± 5% − − ±0.05 dB 0.2 0.4 1.2 dB dB dB Absolute Receive gain ∆GV (ARX) Variation with Supply Voltage /∆V Receive Gain Variations with Level ∆GV (RXL) − Sinusoidal test method, reference input PCM code corresponds to an ideally encoded −10dB0 signal PCM level = −40dBm0 to +3dBm0 PCM level = −50dBm0 to −10dBm0 PCM level = −55dBm0 to −50dBm0 −0.2 −0.4 −1.2 −2.5 − 2.5 V Receive Output Drive Level VO (RX) RL = 600Ω Absolute Level VAL Norminal 0dBm0 level is 4dBm (600Ω) 0dBm0 − 1.2276 − Vrms Max Overload Level VOL (AMX) Max overload level (3.17dBm0): S5T8554B Max overload level (3.14dBm0): S5T8557B − 2.501 − VPK Transmit Gain, Absolute GV (ATX) Ta = 25°C, VCC = 5V, VBB = −5V Input at GSX = 0dBm0 at 1020Hz −0.15 − 0.15 dB Transmit Gain, Relative to GV (ARX) GV (RTX) f = 16Hz f = 50Hz f = 60Hz f = 200Hz f = 300Hz - 3000Hz f = 3300Hz f = 3400Hz f = 4000Hz f = 4600Hz and up, measure response from 0Hz to 4000Hz − −40 −30 −26 −0.1 0.15 0.05 0 − −14 −32 dB dB dB dB dB dB dB dB dB dB −1.8 −0.15 −0.35 −0.7 9 S5T8554B/7B 1 CHIP CODEC TRANSMISSION CHARACTERISTICS (Unless otherwise specified: Ta = 0°C to 70°C, VCC = 5V ± 5%, VBB = −5V ± 5%, GNDA = 0V, f = 1.02kHz, VIN = 0dBm0, transmit input amplifier connected for unity-gain non-inverting.) Characteristic Absolute Transmit Gain Variation with Temperature Symbol ∆GV(ATX) Ta = 0°C to 70°C /∆T Absolute Transmit Gain ∆GV Variation with Supply Voltage (ATX) /∆V Transmit Gain Variations with Level Test Conditions − VCC = 5V ±5%, VBB = −5V ±5% Sinusoldal test method Reference level = − 10dBm0 VFXI + = − 40dBm0 to +3dBm0 VFX + = − 50dBm0 to − 40dBm0 VFXI + = − 55dBm0 to − 50dBm0 Min. Typ. Max. Unit − − ±0.1 dB − − ±0.05 dB 0.2 0.4 1.2 dB dB dB 200 µs − −0.2 −0.4 −1.2 ENVELOPE DELAY DISTORTION WITH FREQUENCY Receive Delay, Absolute tD (ARX) f = 1600Hz Receive Delay, Relative to tD (ARX) tD (RRX) f = 500Hz - 1000Hz f = 1000Hz - 1600Hz f = 1600Hz - 2600Hz f = 2600Hz - 2800Hz f = 2800Hz - 3000Hz − 180 −40 −30 −25 −120 70 100 145 90 125 175 µs µs µs µs µs Transmit Delay, Absolute tD (ATX) f = 1600Hz − 290 315 µs Transmit Delay, Relative to tD (ATX) tD (RTX) f = 500Hz - 600Hz f = 600Hz - 800Hz f = 800Hz - 1000Hz f = 1000Hz - 1600Hz f = 1600Hz - 2600Hz f = 2600Hz - 2800Hz f = 2800Hz - 3000Hz − 195 120 50 20 55 80 130 220 145 75 40 75 105 155 µs µs µs µs µs µs µs Receive Noise, CMessage Weighted NRXC PCM code equals alternating positive and negative zero, S5T8554B − 8 11 dBrnc0 Receive Noise, PMessage Weighted NRXP PCM code equals, positive zero, S5T8557B − −82 −79 dBm0p Transmit Noise, CMessage Weighted NTXC S5T8554B − 12 15 dBrnc0 Transmit Noise, PMessage Weighted NTXP S5T8557B − 74 −67 dBm0p Noise, Single Frequency NSF f = 0kHz to 100kHz, loop around measurement, VFXI + = 0Vrms − − −53 dBm0 Positive Power Supply Rejection, Transmit PSRR VFXI + = 0Vrms, VCC = 5.0VDC + 100mVrms f = 0kHz - 50kHz 40 − − dBC NOISE 10 (PTX) 1 CHIP CODEC S5T8554B/7B TRANSMISSION CHARACTERISTICS (Unless otherwise specified: Ta = 0°C to 70°C, VCC = 5V ± 5%, VBB = −5V ± 5%, GNDA = 0V, f = 1.02kHz, VIN = 0dBm0, transmit input amplifier connected for unity-gain non-inverting.) Characteristic Symbol Negative Power Supply Rejection, Transmit PSRR Positive Power Supply Rejection, Receive PSRR Negative Power Supply Rejection, Receive Spurious Out-of-Band Signals at the Channel Output (NTX) (PRX) PSRR (NRX) SOS Test Conditions Min. Typ. Max. Unit VFXI + = 0Vrms, VBB = −5.0VDC + 100mVrms f = 0kHz - 50kHz 40 − − dBC − − PCM code equals positive zero VCC = 5.0VDC + 100mVrms f = 0Hz - 4000Hz f = 4kHz - 25kHz f = 25kHz - 50kHz PCM code equals positive zero VBB = 5.0VDC + 100mVrms f = 0Hz - 4000Hz f = 4kHz - 25kHz f = 25kHz - 50kHz Loop around measurement, 0dBm0, 300Hz - 3400Hz input PCM applied to DR, Measure individual image signals at VFRO 4600Hz - 760Hz 7600Hz - 8400Hz 8400Hz - 100,000Hz 40 40 36 dBC dB dB − − 40 40 36 − dBC dB dB − −32 −40 −32 dB dB dB DISTORTION Signal to Total Distortion Transmit or Receive HalfChannel THDTX THDRX Single Frequency Distortion, Transmit THDSF Single Frequency Distortion, Receive THDSF Intermodulation Distortion THDIMD Sinusoidal test method Level = 3.0dBm0 = 0dBm0 to 30dBm0 = −40dBm0 XMT RCV = −55dBm0 XMT RCV − − 33 26 29 30 14 15 dBC dBC dBC dBC dBC dBC − − − −46 dB − − − −46 dB − − −41 dB − −90 −75 dB (TDO) (RX) Loop around measurement, VFXI + = −4dBm0 to −21dBm0, two frequencies in the range 300Hz - 3400Hz CROSSTALK Transmit to Receive Crosstalk, 0dB0 Transmit Level CT (TX-RX) f = 300Hz - 3400Hz DR = Steady PCM code 11 S5T8554B/7B 1 CHIP CODEC TRANSMISSION CHARACTERISTICS (Unless otherwise specified: Ta = 0°C to 70°C, VCC = 5V ± 5%, VBB = −5V ± 5%, GNDA = 0V, f = 1.02kHz, VIN = 0dBm0, transmit input amplifier connected for unity-gain non-inverting.) Characteristic Receive to Transmit Crosstalk, 0dBm0 Receive Level Symbol Test Conditions Min. Typ. Max. Unit CT (RX-TX) − − −90 −70 (Note1) dB NOTE: CT (RX-TX) is measured with a - 40dBm0 activating signal applied at VFXI + Encoding Format At DX Output µ-Law KT8554 A-Law KT8557 VIN (at GSX) = + Full Scale 10000000 10101010 VIN (at GSX) = 0V 11111111 01111111 11010101 01010101 VIN (at GSX) = -Full Scale 0000000 00101010 12 1 CHIP CODEC S5T8554B/7B APPLICATION CIRCUIT +5V -5V 0.1µF 0.1µF 4 2 1 VCC GND V BB DX 11 DX DR 6 DR MCLKX 9 CLOCK BCLK X 10 BCLKR/CLKSEL 7 FSXS 12 R2 14 GS X S5T8554B/7B KT8554/7 R1 FROM SLIC 15 VFXIR4 TO SLIC R3 3 VFRO 16 VFXI+ R6 u-low only FS PDN 8 MCLK R/PDN FSR X/R 5 NOTES: 1. Supposing Desired Line Termination Impedance RL = 600ohm It is 0dBm = 0.77459Vrms 2. TX Gain 20 log (R2/R1), R1 + R2 < 100Kohm, or The Correspondence of 1-CHIP CODEC 0dBm 0 = 4dBm. SELECTION OF MASTER CLOCK FREQUENCY BCLKR/CLKSEL S5T8554B S5T8557B Clocked 1.536 / 1.544MHz 2.048MHz 0 2.048MHz 1.536 / 1.544MHz 1 (or open) 1.536 / 1.544MHz 2.048MHz 13 S5T8554B/7B 1 CHIP CODEC NOTES 14