User Guide for FEBFAN9611_S01U300A Evaluation Board FAN9611 300W Interleaved Dual-BCM, Low-Profile, PFC Evaluation Board Featured Fairchild Product: FAN9611 Direct questions or comments about this evaluation board to: “Worldwide Direct Support” Fairchild Semiconductor.com © 2012 Fairchild Semiconductor Corporation 1 FEBFAN9611_S01U300A • Rev. 0.0.1 Table of Contents 1. Overview of the Evaluation Board ............................................................................................. 3 2. Key Features ............................................................................................................................... 5 3. Specifications ............................................................................................................................. 6 4. Test Procedure ............................................................................................................................ 7 4.1. Safety Precautions .............................................................................................................7 5. Schematic ................................................................................................................................... 9 6. Boost Inductor Specification .................................................................................................... 10 7. Four-Layer PCB and Assembly Images ................................................................................... 11 8. Bill of Materials (BOM) ........................................................................................................... 14 9. Inrush Current Limiting............................................................................................................ 16 10. Test Results ............................................................................................................................. 18 10.1. Startup .............................................................................................................................18 10.2. Steady State Operation....................................................................................................20 10.3. Line Transient .................................................................................................................24 10.4. Load Transient ................................................................................................................25 10.5. Brownout Protection .......................................................................................................27 10.6. Phase Management .........................................................................................................28 10.7. Efficiency ........................................................................................................................30 10.8. Harmonic Distortion and Power Factor ..........................................................................32 10.9. EMI .................................................................................................................................33 11. References ............................................................................................................................... 34 12. Ordering Information .............................................................................................................. 34 13. Revision History ..................................................................................................................... 34 © 2012 Fairchild Semiconductor Corporation 2 FEBFAN9611_S01U300A • Rev. 0.0.1 The following user guide supports the FAN9611 300W evaluation board for interleaved boundary-conduction-mode power-factor-corrected supply. It should be used in conjunction with the FAN9611 datasheet, Fairchild application note AN-6086 —Design Considerations for Interleaved Boundary-Conduction Mode PFC Using FAN9611 / FAN9612 and FAN9611/12 PFC Excel®-based Design Tool. 1. Overview of the Evaluation Board The FAN9611 interleaved, dual Boundary-Conduction-Mode (BCM), Power-FactorCorrection (PFC) controllers operate two parallel-connected boost power trains 180º out of phase. Interleaving extends the maximum practical power level of the control technique from about 300W to greater than 800W. Unlike the Continuous Conduction Mode (CCM) technique often used at higher power levels, BCM offers inherent zerocurrent switching of the boost diodes (no reverse-recovery losses), which permits the use of less expensive diodes without sacrificing efficiency. Furthermore, the input and output filters can be smaller due to ripple current cancellation between the power trains and doubling of effective switching frequency. The advanced line feed-forward with peak detection circuit minimizes the output voltage variation during line transients. To guarantee stable operation with less switching loss at light load, the maximum switching frequency is clamped at 525kHz. Synchronization is maintained under all operating conditions. Protection functions include output over-voltage, over-current, open-feedback, undervoltage lockout, brownout, and redundant latching over-voltage protection. FAN9611 is available in a lead-free, 16-lead, Small-Outline Integrated-Circuit (SOIC) package. This FAN9611 evaluation board uses a four-layer Printed Circuit Board (PCB) designed for 300W (400V/0.75A) rated power. The maximum rated power is 350W and the Maximum On-Time (MOT) power limit is set to 360W. The FEBFAN9611_S01U300A is optimized to demonstrate all the FAN9611 efficiency and protection features in a lowprofile height form factor less than 18mm. © 2012 Fairchild Semiconductor Corporation 3 FEBFAN9611_S01U300A • Rev. 0.0.1 Figure 1. FEBFAN9611_S01U300A, Top View, 152mm x 105mm Figure 2. FEBFAN9611_S01U300A, Side View (Low Profile), Cross Section=18mm Figure 3. FEBFAN9611_S01U300A, Bottom View, 152mm x 105mm © 2012 Fairchild Semiconductor Corporation 4 FEBFAN9611_S01U300A • Rev. 0.0.1 2. Key Features ZCD1 180° Out-of-Phase Synchronization Automatic Phase Disable at Light Load 1.8A Sink, 1.0A Source, High-Current Gate Drivers Transconductance (gM) Error Amplifier for Reduced Overshoot Voltage-Mode Control with (VIN)2 Feed-Forward Closed-Loop Soft-Start with Programmable Soft-Start Time for Reduced Overshoot Minimum Restart Timer Frequency to Avoid Audible Noise Maximum Switching Frequency Clamp Brownout Protection with Soft Recovery Non-Latching OVP on FB Pin and Second-Level Latching Protection on OVP Pin Open-Feedback Protection Over-Current and Power-Limit Protection for Each Phase Low Startup Current: 80µA Typical Works with DC input or 50Hz to 400Hz AC Input CHANNEL 1 VALLEY DETECTOR 1 SYNCHRONIZATION A 16 CS1 15 CS2 14 VDD 13 DRV1 12 DRV2 11 PGND 10 VIN 9 OVP B RESTART TIMERS FREQUENCY CLAMPS ZCD2 CHANNEL 2 VALLEY DETECTOR 2 0.2V VDD VDD 5V 5VB 5V 5V BIAS 3 0.195V UVLO 2 K1 VIN IMOT A IMOT MOT 4 R Q A 1.25V S Q R Q S Q 5V 0.195V AGND K1 5 2 VIN IMOT B B 5V 5µA SS 6 3VREF COMP gm FB INPUT VOLTAGE SENSE (Input Voltage Squarer, Input UVLO, Brownout) 7 8 Phase Management 2µA PROTECTION LOGIC (Open FB, Brownout Protection, OVP, Latched OVP) Figure 4. Block Diagram © 2012 Fairchild Semiconductor Corporation 5 FEBFAN9611_S01U300A • Rev. 0.0.1 3. Specifications This evaluation board has been designed and optimized for the conditions in Table 1. Table 1. Electrical and Mechanical Requirements VIN_AC Min. Typ. Max. 80V 120V 265V VIN_AC(ON) 90V VIN_AC(OFF) 80V fVIN_AC 50Hz 60Hz 65Hz VOUT_PFC 395V 400V 405V VOUT_PFC_RIPPLE 10V 11V POUT_PFC 300W 350W POUT_PFC(MOT LIMIT) 360W fSW_PFC 18kHz tHOLD_UP 20ms tSOFT_START 300kHz 250ms tON_OVERSHOOT 300ms 10V η_PFC_120V POUT>30%POUT(TYP) 96% 96.5% η_PFC_230V POUT>30%POUT(TYP) 95% 98% PF_120V 0.991 PF_230V 0.980 Mechanical and Thermal Height 18mm θJC 60⁰C The trip points for the built-in protections are set as below in the evaluation board. The line UVLO (brownout protection) trip point is set at 80VAC (10VAC hysteresis). The pulse-by-pulse current limit for each MOSFET is set at 6A. The current-limit function can be observed by measuring the individual inductor current waveforms while operating at 85VAC and increasing the load to 360W. The maximum power limit is set at ~120% of the rated output power. The power-limit function can be observed while operating at >115VAC and increasing the load beyond 360W. When operating in power limit, the output voltage drops and the COMP voltage is saturated, but the AC line current remains sinusoidal. The phase-management function permits phase shedding / adding ~18% of the nominal output power for high line (230VAC). This level can be increased by modifying the MOT resistor (R6) as described in Fairchild Application Note AN-6086 —Design Considerations for Interleaved BoundaryConduction Mode PFC Using FAN9611 / FAN9612. © 2012 Fairchild Semiconductor Corporation 6 FEBFAN9611_S01U300A • Rev. 0.0.1 4. Test Procedure Before applying power to the FEBFAN9611_S01U300A evaluation board; the DC bias supply for VDD, AC voltage supply for line input, and DC electronic load for output should be connected to the board as shown in Figure 5. Table 2. Specification Excerpt from FAN9611 Datasheet Symbol Parameter Conditions Min. Typ. Max. Unit Supply Startup Supply Current VDD = VON – 0.2V 80 110 µA Operating Current Output Not Switching 3.7 5.2 mA Dynamic Operating Current fSW = 50kHz; CLOAD = 2nF 4 6 mA VON UVLO Start Threshold VDD Increasing 9.5 10.0 10.5 V VOFF UVLO Stop Threshold Voltage VDD Decreasing 7.0 7.5 8.0 V VHYS UVLO Hysteresis VON – VOFF ISTARTUP IDD IDD_DYM 4.1. 2.5 V Safety Precautions The FEBFAN9611_S01U300A evaluation module produces lethal voltages and the bulk output capacitors store significant charge. Please be extra careful when probing and handling the module and observe a few precautions: Start with a clean working surface, clear of any conductive material. Be careful while turning on the power switch to the AC source. Never probe or move a probe on the DUT while the AC line voltage is present. Ensure the output capacitors are discharged before disconnecting the test leads. One way to do this is to remove the AC power with the DC output load still switched on. The load then discharges the output capacitors and the module is safe to disconnect. Power-On Procedure 1. Supply VDD for the control chip first. It should be higher than 10.5V (refer to the specification for VDD turn-on threshold voltage in Table 2). 2. Connect the AC voltage (90~265VAC) to start the FAN9611 evaluation board. Since FAN9611 has brownout protection, any input voltage less than the designed minimum AC line voltage triggers brownout protection. FEBFAN9611_S01U300A does not start until the AC input voltage is greater than 90VAC. 3. Change load current (0~0.75A) and check the operation 4. Verify the output voltage is regulating between 395VDC<VOUT<405VDC © 2012 Fairchild Semiconductor Corporation 7 FEBFAN9611_S01U300A • Rev. 0.0.1 AC Source PF, THD, PIN 0-265VAC DVM Voltage DVM Current Electronic Load 400V, 0-1A DVM Current DC Bias Supply 0-12V Figure 5. Recommended Test Set-Up All efficiency data shown in this document was taken using the test set up shown in Figure 5 with the output voltage being measured directly at the output bulk capacitors (not through the output connector (J2)). Power-Off Procedure 1. Make sure the electronic load is set to draw at least 100mA of constant DC current. 2. Disconnect (shut down) AC line voltage source. 3. Disconnect (shut down) 12V DC bias power supply. 4. Disconnect (shut down) DC electronic load last to ensure that the output capacitors are fully discharged before handling the evaluation module. © 2012 Fairchild Semiconductor Corporation 8 FEBFAN9611_S01U300A • Rev. 0.0.1 5. Schematic Figure 6. FEBFAN9611_S01U300A 300W Evaluation Board Schematic © 2012 Fairchild Semiconductor Corporation 9 FEBFAN9611_S01U300A • Rev. 0.0.1 6. Boost Inductor Specification 750340834 from Wurth Electronics (www.we-online.com) Core: EFD30 (Ae=69mm2) Bobbin: EFD30 Inductance : 270H Figure 7. Boost Inductor (L1, L2) in the Evaluation Board Figure 8. Wurth 750340834 Mechanical Drawing Table 3. Inductor Turns Specifications Pin Turns Wire 16 69 (3 Layers) 30xAWG#38 Litz 10 9 7 AWG#28 NBOOST Insulation Tape NAUX Insulation Tape © 2012 Fairchild Semiconductor Corporation 10 FEBFAN9611_S01U300A • Rev. 0.0.1 7. Four-Layer PCB and Assembly Images Figure 9. Layer 1 – Top Layer Figure 10. Layer 2 – Internal Layer © 2012 Fairchild Semiconductor Corporation 11 FEBFAN9611_S01U300A • Rev. 0.0.1 Figure 11. Layer 3 – Internal Layer Figure 12. Layer 4 – Bottom Layer © 2012 Fairchild Semiconductor Corporation 12 FEBFAN9611_S01U300A • Rev. 0.0.1 Figure 13. Top Assembly Figure 14. Bottom Assembly © 2012 Fairchild Semiconductor Corporation 13 FEBFAN9611_S01U300A • Rev. 0.0.1 8. Bill of Materials (BOM) Item Qty. Reference Part Number Value Description Manufacturer Package STD 1206 1 2 C1, C6 0.22µF CAP, SMD, Ceramic, 25V, X7R 2 1 C2 390nF CAP, SMD, Ceramic, 25V, X7R STD 805 3 2 C3, C13 15nF CAP, SMD, Ceramic, 25V, X7R STD 805 4 2 C4, C9 150nF Cap, 450V, 5%, Polypropylene Panasonic Thru-Hole 470nF CAP, SMD, Ceramic, 25V, X7R STD 805 Cap, 330VAC, 10%, Polypropylene EPCOS Thru-Hole ECW-F2W154JAQ 5 1 C5 6 2 C7, C11 B32914A3474 470nF 7 2 C8, C26 B43041A5157M 150µF Cap, Alum, Elect. EPCOS Thru-Hole 2.2µF CAP, SMD, Ceramic, 25V, X7R STD 1206 8 2 C10, C14 9 1 C12 B32914A3105K 1µF Cap, 330VAC, 10%, Polypropylene Epcos Thru-Hole 10 1 C15 PHE840MB6100MB05R17 0.1µF Cap, X Type, 10%, Polypropylene KEMET Thru-Hole 11 2 C16, C18 CS85-B2GA471KYNS 470pF Cap, Ceramic, 250VAC, 10%, Y5P, TDK Corporation Thru-Hole 12 1 C17 2.7nF CAP, SMD, Ceramic, 25V, X7R STD 805 13 1 C19 0.1µF CAP, SMD, Ceramic, 25V, X7R STD 805 14 1 C20 1µF CAP, SMD, Ceramic,50V, X5R STD 805 15 1 C37 1nF CAP, SMD, Ceramic, 25V, X7R STD 805 16 3 D1-3 ES3J Diode, 600V, 3A, Ultra-Fast Recovery Fairchild Semiconductor SMC 17 2 D4, D6 S1J Diode, General Purpose, 1A, 600V Fairchild Semiconductor SMA 18 1 D5 GBU6J Diode, Bridge, 6A, 1000V Fairchild Semiconductor Thru-Hole 19 3 D7-8, D10 MBR0540 Diode, Schottky,40V, 500mA Fairchild Semiconductor SOD-123 20 1 D9 MMBZ5231B 5.1V Diode, Zener, 5V, 350mW Fairchild Semiconductor SOT-23 21 1 F1 37421000410 10A Fuse, 374 Series, 5.08mm Spacing Littlefuse Radial 22 1 H1 7-345-2PP-BA Heatsink, Low Profile, T0-247 CTS Thru-Hole 23 1 J1 1-1318301-3 Header, 3 Pin, 0.312 Spacing TE Connectivity Thru-Hole 24 1 J2 1-1123724-2 Header, 2 Pin, 0.312 Spacing TYCO Thru-Hole 25 5 J3-7 3103-2-00-21-00-00-08-0 Test pin, Gold, 40mil, Mill-Max Thru-Hole 26 1 K1 G5CA-1A DC12 RELAY PWR SPST-NO 10A 12VDC PCB Omeron Electronics, Inc. Thru-Hole 27 2 L1-2 750340834/NP1138-01 280µH Inductor, Coupled Wurth Thru-Hole 28 2 L3-4 750311795 9mH Common Mode Choke, 9mH Wurth Thru-Hole MOSFET, NCH, UniFET, 500V, 11.5A, 0.18Ω Fairchild Semiconductor TO-220 29 2 Q1, Q3 FDP22N50N Continued on the following page… © 2012 Fairchild Semiconductor Corporation 14 FEBFAN9611_S01U300A • Rev. 0.0.1 Item Qty. Reference Part Number Value Description Manufacturer Package 30 2 Q2, Q4 ZXTP25020DFL Transistor, PNP, 20V, 1.5A Zetex SOT-23 31 1 Q6 2N7002 MOSFET, NCH, 60V, 300mA Philips SOT-23 32 2 R1-2 46.4kΩ RES, SMD, 1/8W STD 805 33 6 R3, R18, R23-24 R3334 665kΩ RES, SMD, 1/8W STD 805 34 3 R4, R7-8 340kΩ RES, SMD, 1/8W STD 805 35 1 R5 68.1kΩ RES, SMD, 1/8W STD 805 36 1 R6 60.4kΩ RES, SMD, 1/8W STD 805 37 1 R9 422kΩ RES, SMD, 1/8W STD 805 38 2 R10, R20 47.5Ω RES, SMD, 1/8W STD 805 39 2 R11-12 12Ω RES, SMD, 1/8W STD 805 40 2 R13-14 0.033Ω RES, SMD, 1W STD 2512 41 1 R15 33Ω Thermistor Epcos Inc. Thru-Hole 42 3 R16, R26, R40 0Ω RES, SMD, 1/2W STD 2010 43 1 R17 45.3kΩ RES, SMD, 1/8W STD 805 B57237S0330M000 44 1 R19 15.4kΩ RES, SMD, 1/8W STD 805 45 2 R21-22 10kΩ RES, SMD, 1/8W STD 805 46 1 R25 24.9kΩ RES, SMD, 1/4W STD 1206 47 2 R27-28 1.24MΩ RES, SMD, 1/8W STD 805 48 3 R29, R35-36 1.2kΩ RES, SMD, 1/8W STD 805 49 1 R30 23.7kΩ RES, SMD, 1/4W STD 1206 50 1 R31 7.68kΩ RES, SMD, 1/8W STD 805 51 1 R32 150kΩ RES, SMD, 1/4W STD 1206 52 1 R37 1kΩ RES, SMD, 1/8W STD 805 53 1 R38 0Ω RES, SMD, 1/4W STD 1206 54 1 R39 0Ω RES, SMD, 1/8W STD 805 55 2 R65-66 DNP RES, SMD, 1/10W STD 603 Fairchild Semiconductor SOIC-16 56 1 U1 FAN9611 Interleaved, Dual, BMC, PFC Controller 57 1 U2 LM393M Dual, Differential Comparator Fairchild Semiconductor SOIC-8 58 2 SC1, SC2 PMSSS 440 0050 PH SCREW MACHINE PHIL 440X1/2 SS STD Hardware 59 2 W1, W2 INT LWZ 004 WASHER LOCK INT TOOTH #4 ZINC STD Hardware 60 2 N1, N2 HNZ440 NUT HEX 4-40 ZINC PLATED STD Hardware 4 Layer, FR4, FAN9611 LOWPROFILE PWB - REV. 1.0 Fairchild Semiconductor PCB 61 1 PWB Notes: 1. DNP = Do Not Populate 2. STD = Standard Components © 2012 Fairchild Semiconductor Corporation 15 FEBFAN9611_S01U300A • Rev. 0.0.1 9. Inrush Current Limiting The evaluation board includes an inrush current limiting circuit comprised of the highlighted components shown in Figure 15. Figure 15. Inrush Current Limiting Circuit Since the inrush current limiting circuit has a negative impact on light-load efficiency and may not be required by all offline applications, the evaluation board is configured with the inrush circuit fully populated, but disabled, as shown in Figure 15. R18 and R39 are installed on the PCB; purposely electrically open. To enable and test the inrush current limiting circuit, rotate R18 and R39 to complete the proper series connection shown in the schematic. Remove R38 to allow the 33Ω NTC thermistor (R15) to limit the inrush current during startup. Input current measurements can be made by removing the R16, 0Ω jumper and installing a loop of wire connected to the holes provided within the R16 PCB pad locations. A current probe can then be connected to the wire loop. The effectiveness of the inrush current limiting function is shown below in Figure 16. © 2012 Fairchild Semiconductor Corporation 16 FEBFAN9611_S01U300A • Rev. 0.0.1 33Ω NTC AC Input Current (Inrush Enabled) AC Input Current (Inrush Disabled) AC Input Peak Current (Zoom) (Inrush Disabled) M2: AC Line Current (5A/div), CH3: AC Line Current (5A/div), Time (50ms/div) Figure 16. Full-Load Startup at 115VAC Table 4. Inrush Current Limiting Circuit Effectiveness Comparison Input Line Output Peak Line Current Peak Line Current Voltage Power (Inrush Circuit Disabled) (Inrush Circuit Enabled) % Inrush Current Reduction VIN=115VAC 300W 22.50APK 8.45APK 62.40% VIN=230VAC 300W 26.9APK 11.5APK 57.3% © 2012 Fairchild Semiconductor Corporation 17 FEBFAN9611_S01U300A • Rev. 0.0.1 10. Test Results 10.1. Startup Figure 17 and Figure 18 show the startup operation at 115VAC line voltage for no-load and full-load condition, respectively. Due to the closed-loop soft-start, almost no overshoot is observed for no-load startup and full-load startup. DRV1 COMP VOUT Line Current CH1: Gate Drive 1 Voltage (20V/div), CH2: COMP Voltage (2V/div), CH3: Output Voltage (200V/div), CH4: Line Current (5A/div), Time (100ms/div) Figure 17. No-Load Startup at 115VAC DRV1 COMP VOUT Line Current CH1: Gate Drive 1 Voltage (20V/div), CH2: COMP Voltage (2V/div), CH3: Output Voltage (200V/div), CH4: Line Current (5A/div), Time (200ms/div) Figure 18. Full-Load Startup at 115VAC © 2012 Fairchild Semiconductor Corporation 18 FEBFAN9611_S01U300A • Rev. 0.0.1 Figure 19 and Figure 20 show the startup operation at 230VAC line voltage for no-load and full-load conditions, respectively. Due to the closed-loop soft-start, almost no overshoot is observed for no-load startup and full-load startup. DRV1 COMP VOUT Line Current CH1: Gate Drive 1 Voltage (20V/div), CH2: COMP Voltage (2V/div), CH3: Output Voltage (200V/div), CH4: Line Current (10A/div), Time (100ms/div) Figure 19. No-Load Startup at 230VAC DRV1 COMP VOUT Line Current CH1: Gate Drive 1 Voltage (20V/div), CH2: COMP Voltage (2V/div), CH3: Output Voltage (200V/div), CH4: Line Current (10A/div), Time (100ms/div) Figure 20. Full-Load Startup at 230VAC © 2012 Fairchild Semiconductor Corporation 19 FEBFAN9611_S01U300A • Rev. 0.0.1 10.2. Steady-State Operation Figure 21 and Figure 22 show the two inductor currents and the sum of the two inductor currents operating at full load for 90VAC and 230VAC line voltage. The sum of the inductor currents has relatively small ripple due to the ripple cancellation of interleaving. IL2 IL1 IL1 + IL2 CH3: Inductor L2 Current (5A/div), CH4: Inductor L1 Current (5A/div), CH2: Sum of Two Inductor Currents (5A/div), Time (2ms/div, zoom to 10s/div) Figure 21. Zoom of Inductor Current Waveforms at Full-Load and 90VAC IL2 IL1 IL1 + IL2 CH3: Inductor L1 Current (2A/div), CH4: Inductor L2 Current (2A/div), CH2: Sum of Two Inductor Current (2A/div), Time (2ms/div) Figure 22. Zoom of Inductor Current Waveforms at Full-Load and 230VAC © 2012 Fairchild Semiconductor Corporation 20 FEBFAN9611_S01U300A • Rev. 0.0.1 VDS(Q3) DRV1 ZCD1 IL2 CH1: DRV1 (20V/div), CH2: VDS(Q3) (100V/div) CH3: ZCD1 (1V/div), CH4: Inductor L2 Current (5A/div) Figure 23. Zero Valley Switching at Full Load, 115VAC VDS(Q3) DRV1 ZCD1 IL2 CH1: DRV1 (20V/div), CH2: VDS(Q3) (100V/div) CH3: ZCD1 (1V/div), CH4: Inductor L2 Current (5A/div) Figure 24. Zero Valley Switching at Full Load, 230VAC © 2012 Fairchild Semiconductor Corporation 21 FEBFAN9611_S01U300A • Rev. 0.0.1 VDS(Q3) IL2 DRV1 CH1: DRV1 (20V/div), CH2: VDS(Q3) (100V/div) CH4: Inductor L2 Current (5A/div) Figure 25. Zoom of Valley Switching at Full Load, 230VAC CS1 CS2 IL2 IL1 CH1: FAN9611, Pin 16 (100mV/div), CH2: FAN9611, Pin 15 (100mV/div) CH3: Inductor L2 Current (5A/div), CH4: Inductor L1 Current (5A/div) Figure 26. Current-Sense Waveforms at Full Load, 90VAC © 2012 Fairchild Semiconductor Corporation 22 FEBFAN9611_S01U300A • Rev. 0.0.1 IL1 IL2 CH1: Inductor L1 Current (2A/div), CH2: Inductor L2 Current (2A/div) Figure 27. Inductor Current Waveforms at 360W, 85VAC, Over-Current Operation IL1 IL2 Line Current VOUT CH1: Inductor L1 Current (5A/div), CH2: Inductor L2 Current (5A/div) CH3: Output Voltage (100V/div), CH4: Line Current (5A/div), Time (20ms/div) Figure 28. MOT Power Limit, 0.5A to 1.3A Load Transient, 115VAC © 2012 Fairchild Semiconductor Corporation 23 FEBFAN9611_S01U300A • Rev. 0.0.1 10.3. Line Transient Figure 29 and Figure 30 show the line transient operation and minimal effect on output voltage due to the line feed-forward function. When the line voltage changes from 230VAC to 115VAC, about 20V (5% of nominal output voltage) voltage undershoot is observed. When the line voltage changes from 115VAC to 230VAC, about 6V (1.5% of nominal output voltage) voltage overshoot is observed. Rectified Line Voltage VOUT COMP Line Current CH1: Rectified Line Voltage (200V/div), CH2: Output Voltage (20V/div, AC), CH3: COMP Voltage (2V/div), CH4: Line Current (5A/div), Time (50ms/div) Figure 29. Line Transient Response at Full-Load Condition (230VAC 115VAC) Rectified Line Voltage VOUT COMP Line Current CH1: Rectified Line Voltage (200V/div), CH2: Output Voltage (10V/div, AC), CH3: COMP Voltage (2V/div), CH4: Line Current (5A/div), Time (50ms/div) Figure 30. Line Transient Response at Full-Load Condition (115VAC 230VAC) © 2012 Fairchild Semiconductor Corporation 24 FEBFAN9611_S01U300A • Rev. 0.0.1 10.4. Load Transient Figure 31 and Figure 32 show the load-transient operation. When the output load changes from 100% to 0%, 20V (5% of nominal output voltage) voltage overshoot is observed. When the output load changes from 0% to 100%, 34V (8.5% of nominal output voltage) voltage undershoot is observed. Rectified Line Voltage VOUT COMP Line Current CH1: Rectified Line Voltage (100V/div), CH2: Output Voltage (20V/div, AC), CH3: COMP Voltage (2V/div), CH4: Line Current (5A/div), Time (50ms/div) Figure 31. Load Transient Response at 115VAC (Full Load No Load) Rectified Line Voltage VOUT COMP Line Current CH1: Rectified Line Voltage (100V/div), CH2: Output Voltage (20V/div, AC), CH3: COMP Voltage (2V/div), CH4: Line Current (5A/div), Time (50ms/div) Figure 32. Load Transient Response at 115VAC (No Load Full Load) © 2012 Fairchild Semiconductor Corporation 25 FEBFAN9611_S01U300A • Rev. 0.0.1 Rectified Line Voltage VOUT COMP Line Current CH1: Rectified Line Voltage (100V/div), CH2: Output Voltage (20V/div, AC), CH3: COMP Voltage (5V/div), CH4: Line Current (5A/div), Time (50ms/div) Figure 33. Load Transient Response at 230VAC (Full Load No Load) Rectified Line Voltage VOUT COMP Line Current CH1: Rectified Line Voltage (100V/div), CH2: Output Voltage (20V/div, AC), CH3: COMP Voltage (5V/div), CH4: Line Current (5A/div), Time (50ms/div) Figure 34. Load Transient Response at 230VAC (No Load Full Load) © 2012 Fairchild Semiconductor Corporation 26 FEBFAN9611_S01U300A • Rev. 0.0.1 10.5. Brownout Protection Figure 35 shows the startup operation while slowly increasing the line voltage. The power supply starts up when the line voltage reaches around 90VAC. Figure 36 shows the shutdown operation while slowly decreasing the line voltage. The power supply shuts down when the line voltage reaches around 80VAC. Line Voltage DRV1 Line Current CH1: Line Voltage (100V/div), CH2: Gate Drive 1 Voltage (10V/div), CH4: Line Current (5A/div), Time (200ms/div) Figure 35. Startup Slowly Increasing the Line Voltage Line Voltage DRV1 Line Current CH1: Line Voltage (100V/div), CH2: Gate Drive 1 Voltage (10V/div), CH4: Line Current (5A/div), Time (20ms/div) Figure 36. Shutdown Slowly Decreasing the Line Voltage © 2012 Fairchild Semiconductor Corporation 27 FEBFAN9611_S01U300A • Rev. 0.0.1 10.6. Phase Management Figure 37 and Figure 38 show the phase-shedding waveforms. As observed, when the gate drive signal of Channel 2 is disabled, the duty cycle of Channel 1 gate drive signal is doubled to minimize the line current glitch and guarantee smooth transient. DRV1 DRV2 IL1 IL2 CH1: Gate Drive 1 Voltage (20V/div), CH2: Gate Drive 2 Voltage (20V/div), CH3: Inductor L1 Current (1A/div), CH4: Inductor L2 Current (1A/div), Time (5ms/div) Figure 37. Phase-Shedding Operation DRV1 DRV2 IL1 IL2 CH1: Gate Drive 1 Voltage (20V/div), CH2: Gate Drive 2 Voltage (20V/div), CH3: Inductor L1 Current (1A/div), CH4: Inductor L2 Current (1A/div), Time (5µs/div) Figure 38. Phase-Shedding Operation (Zoomed-in Timescale) © 2012 Fairchild Semiconductor Corporation 28 FEBFAN9611_S01U300A • Rev. 0.0.1 Figure 39 and Figure 40 show the phase-adding waveforms. As observed, just before the Channel 2 gate drive signal is enabled, the duty cycle of Channel 1 gate drive signal is reduced by 50% to minimize the line current glitch and guarantee smooth transient. In Figure 40, the first pulse of gate drive 2 during the phase-adding operation is skipped to ensure 180° out-of-phase interleaving operation during transient. DRV1 DRV2 IL1 IL2 CH1: Gate Drive 1 Voltage (20V/div), CH2: Gate Drive 2 Voltage (20V/div), CH3: Inductor L1 Current (1A/div), CH4: Inductor L2 Current (1A/div), Time (5ms/div) Figure 39. Phase-Adding Operation DRV1 DRV2 IL1 IL2 CH1: Gate Drive 1 Voltage (20V/div), CH2: Gate Drive 2 Voltage (20V/div), CH3: Inductor L1 Current (1A/div), CH4: Inductor L2 Current (1A/div), Time (5µs/div) Figure 40. Phase-Adding Operation (Zoomed-in Timescale) © 2012 Fairchild Semiconductor Corporation 29 FEBFAN9611_S01U300A • Rev. 0.0.1 10.7. Efficiency Figure 41 and Figure 42 show the measured efficiency of the 300W evaluation board with RMOT=60.4kΩ at input voltages of 115VAC and 230VAC. The phase management threshold on the test evaluation board is approximately 15% of the nominal output power. The threshold can be adjusted upwards to achieve a more desirable efficiency profile by increasing the MOT resistor. Figure 43 and Figure 44 show the light-load efficiency improvement that can be achieved when the threshold is adjusted to 30% by increasing the MOT resistor to 120kΩ. Since phase shedding reduces the switching loss by effectively decreasing the switching frequency at light load, greater efficiency improvement is achieved at 230VAC, where switching losses dominate. Relatively less improvement is obtained at 115VAC, since the MOSFET is turned on with zero voltage and switching losses are negligible. The efficiency measurements include the losses in the EMI filter, cable loss and power consumption of the control IC. Efficiency vs. Load Efficiency vs. Load (115VAC, 400V DC Output, RMOT=60.4KΩ, No Inrush Circuit) (230VAC, 400V DC Output, RMOT=60.4KΩ, No Inrush Circuit) 100% Efficiency (%) Efficiency (%) 100% 95% 90% 95% 90% 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 0% 10% 20% 30% Output Power (%) 50% 60% 70% 80% 90% 100% Output Power (%) Figure 41. Efficiency vs. Load (115VAC) Figure 42. Efficiency vs. Load (230VAC) Efficiency vs. Load Efficiency vs. Load (115VAC, 400V DC Output, RMOT=120KΩ, No Inrush Circuit) (230VAC, 400V DC Output, RMOT=120KΩ, No Inrush Circuit) 100% Efficiency (%) 100% Efficiency (%) 40% 95% 90% 95% 90% 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 0% Output Power (%) 20% 30% 40% 50% 60% 70% 80% 90% 100% Output Power (%) Figure 43. Efficiency vs. Load (115VAC) © 2012 Fairchild Semiconductor Corporation 10% Figure 44. Efficiency vs. Load (230VAC) 30 FEBFAN9611_S01U300A • Rev. 0.0.1 Figure 45 and Figure 46 show a direct comparison of light-load efficiency benefit gained when increasing the MOT resistor. For RMOT=120kΩ, the phase threshold is adjusted upward from 18% to approximately 30% of nominal maximum output power. It is not recommended to adjust the phase threshold near the 50% nominal maximum output power, since each individual BCM PFC channel is optimally designed to process 50% (plus 20% margin) of the total output power required by the load. Efficiency vs. Load Efficiency vs. Load (115VAC, 400V DC Output, RMOT Comparison, No Inrush Circuit) (230VAC, 400V DC Output, RMOT Compare, No Inrush Circuit) 100% Efficiency (%) Efficiency (%) 100% 95% 95% RMOT=60.4KΩ RMOT=60.4KΩ RMOT=120KΩ RMOT=120KΩ 90% 90% 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 0% Output Power (%) 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% Output Power (%) Figure 45. Efficiency vs. Load (115VAC) Figure 46. Efficiency vs. Load (230VAC) The FEBFAN9611_S01U300A evaluation board is configured with RMOT=60.4kΩ, which sets the maximum output power limit to about 360W. Because of the highly optimized, low-profile cross-section of this design; the EFD30 inductors are not rated to process more than 200W each (400W total output power). When the MOT resistor is increased to 120kΩ, the maximum allowable output power is also increased to greater than 400W. To fully protect the power stage, a simple voltage divider and PNP clamp should be applied to the FAN9611 COMP voltage (pin 7) as detailed in AN-6086, Figure 15. © 2012 Fairchild Semiconductor Corporation 31 FEBFAN9611_S01U300A • Rev. 0.0.1 10.8. Harmonic Distortion and Power Factor Figure 47 and Figure 48 compare the measured harmonic current with EN61000 Class D and Class C, respectively, at input voltages of 115VAC and 230VAC. Class D is applied to TV and PC power, while Class C is applied to lighting applications. As can be observed, both regulations are met with sufficient margin. EN61000‐3‐2, 115VAC, 300W EN61000‐3‐2, 230VAC, 300W 1.2 1.2 1 Measured Harmonic Current Class C Limit 0.8 Harmonic Current (A) Harmonic Current (A) 1 Class D Limit 0.6 Class C Limit Class D Limit 0.6 0.4 0.4 0.2 0.2 0 Measured Harmonic Current 0.8 0 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 Harmonic Number Harmonic Number Figure 47. Harmonic Current, 115VAC Figure 48. Harmonic Current, 230VAC Power Factor vs. Load Total Harmonic Distortion vs. Load (400V DC Output, 300W) 1.00 30% 0.95 25% 230Vac 20% 115Vac 0.90 230Vac THD (%) Power Factor (400V DC Output, 300W) 0.85 115Vac 15% 0.80 10% 0.75 5% 0.70 0% 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 0% Output Power (%) 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% Output Power (%) Figure 49. Measured Power Factor Figure 50. Measured Total Harmonic Distortion Figure 49 shows the measured power factor at input voltage of 115VAC and 230VAC. As observed, high power factor above 0.95 is obtained from 100% to 50% load. Figure 50 shows the total harmonic distortion at input voltages of 115VAC and 230VAC. © 2012 Fairchild Semiconductor Corporation 32 FEBFAN9611_S01U300A • Rev. 0.0.1 10.9. EMI EN55022 CISPR, Class B Att 10 dB dBµV 100 RBW 9 kHz MT 10 ms PREAMP OFF 1 MHz Att 10 dB dBµV 10 MHz 2 AV MAXH 1 MHz 10 MHz 90 90 1 PK MAXH 100 RBW 9 kHz MT 10 ms PREAMP OFF 1 PK MAXH 80 TDF 70 2 AV MAXH 80 TDF 70 EN55022Q EN55022Q 60 60 PRN EN55022A PRN EN55022A 50 50 6DB 6DB 40 40 30 30 20 20 10 10 0 0 150 kHz 30 MHz 150 kHz Figure 52. 115VAC, Neutral Figure 51. 115VAC, Line Att 10 dB dBµV 100 RBW 9 kHz MT 10 ms PREAMP OFF 1 MHz Att 10 dB dBµV 10 MHz 90 1 PK MAXH 2 AV MAXH 30 MHz 100 RBW 9 kHz MT 10 ms PREAMP OFF 1 MHz 10 MHz 90 1 PK MAXH 80 TDF 70 EN55022Q 2 AV MAXH 80 TDF 70 EN55022Q 60 60 PRN EN55022A 50 PRN EN55022A 50 6DB 6DB 40 40 30 30 20 20 10 10 0 0 150 kHz 30 MHz 150 kHz Figure 53. 230VAC, Line © 2012 Fairchild Semiconductor Corporation 30 MHz Figure 54. 230VAC, Neutral 33 FEBFAN9611_S01U300A • Rev. 0.0.1 11. References [1] [2] FAN9611 / FAN9612 — Interleaved Dual BCM PFC Controllers AN-6086 — Design Considerations for Interleaved Boundary-Conduction Mode PFC Using FAN9611 / FAN9612 12. Ordering Information Orderable Part Number Description FEBFAN9611_S01U300A FAN9611 300W Evaluation Board 13. Revision History Date Revision Description February 2012 0.0.1 Initial release WARNING AND DISCLAIMER Replace components on the Evaluation Board only with those parts shown on the parts list (or Bill of Materials) in the Users’ Guide. Contact an authorized Fairchild representative with any questions. This board is intended to be used by certified professionals, in a lab environment, following proper safety procedures. Use at your own risk. The Evaluation board (or kit) is for demonstration purposes only and neither the Board nor this User’s Guide constitute a sales contract or create any kind of warranty, whether express or implied, as to the applications or products involved. Fairchild warrantees that its products meet Fairchild’s published specifications, but does not guarantee that its products work in any specific application. Fairchild reserves the right to make changes without notice to any products described herein to improve reliability, function, or design. Either the applicable sales contract signed by Fairchild and Buyer or, if no contract exists, Fairchild’s standard Terms and Conditions on the back of Fairchild invoices, govern the terms of sale of the products described herein. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness ANTI-COUNTERFEITING POLICY Fairchild Semiconductor Corporation's Anti-Counterfeiting Policy. Fairchild's Anti-Counterfeiting Policy is also stated on our external website, www.fairchildsemi.com, under Sales Support. Counterfeiting of semiconductor parts is a growing problem in the industry. All manufacturers of semiconductor products are experiencing counterfeiting of their parts. Customers who inadvertently purchase counterfeit parts experience many problems such as loss of brand reputation, substandard performance, failed applications, and increased cost of production and manufacturing delays. Fairchild is taking strong measures to protect ourselves and our customers from the proliferation of counterfeit parts. Fairchild strongly encourages customers to purchase Fairchild parts either directly from Fairchild or from Authorized Fairchild Distributors who are listed by country on our web page cited above. Products customers buy either from Fairchild directly or from Authorized Fairchild Distributors are genuine parts, have full traceability, meet Fairchild's quality standards for handling and storage and provide access to Fairchild's full range of up-to-date technical and product information. Fairchild and our Authorized Distributors will stand behind all warranties and will appropriately address any warranty issues that may arise. Fairchild will not provide any warranty coverage or other assistance for parts bought from Unauthorized Sources. Fairchild is committed to combat this global problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors. EXPORT COMPLIANCE STATEMENT These commodities, technology, or software were exported from the United States in accordance with the Export Administration Regulations for the ultimate destination listed on the commercial invoice. Diversion contrary to U.S. law is prohibited. U.S. origin products and products made with U.S. origin technology are subject to U.S Re-export laws. In the event of re-export, the user will be responsible to ensure the appropriate U.S. export regulations are followed. © 2011 Fairchild Semiconductor Corporation 34 FEBFAN9611_S01U300A • Rev. 0.0.1