FSA9280A USB Port Multimedia Switch Featuring Automatic Select and Accessory Detection Features Signals Switch Mechanism Accessory Detection USB USB Charging Audio VBAT Programmability ESD Package Description Audio, USB, UART, USB Charging Automatic Switching with Available Interrupt Headsets (Headphone/MIC/Remote) USB Data Port (SDP) UART Serial Link USB Chargers (Car-Kit, CDP, DCP) Factory-Mode TTY Converter FS and HS 2.0 Compliant Battery Charging 1.1 Compliant (Including Optional DCD) Integrated Power FET Over-Voltage Tolerance (OVT) 28V Over-Current Protection (OCP) 1.5A Over-Voltage Protection (OVP) 6.8V Left, Right, MIC, TTY 3 to 4.4V I2 C 15kV IEC 61000-4-2 Air Gap 20-Lead UMLP (3 x 4 x 0.55mm, 0.5mm Pitch) Ordering Information The FSA9280A is a high-performance multimedia switch featuring automatic switching and accessory detection for the USB port. This switch allows sharing of a common USB port to pass audio, USB data / charging, as well as factory programmability. In addition, the FSA9280A integrates detection of accessories; such as headphones, headsets (MIC / button), car chargers, USB chargers, and UART data cables; with the ability to use a common USB connector. The FSA9280A can be programmed for manual or automatic switching of data paths based on accessory detected. FSA9280A includes an integrated 28V over-voltage and 1.5A over-current protected FET. Applications Mobile Phones & Portable Media Players Related Resources FSA9280A Evaluation Board Evaluation Board Users Guide For samples, questions or board requests; please contact [email protected] FSA9280AUMX FSA9280A Figure 1. Typical Application © 2009 Fairchild Semiconductor Corporation FSA9280A • Rev 1.1.0 www.fairchildsemi.com FSA9280A — USB Port Multimedia Switch, Featuring Automatic Select and Accessory Detection March 2013 Features ....................................................................................................................................................................................... 1 Description ................................................................................................................................................................................... 1 Applications .................................................................................................................................................................................. 1 Related Resources ....................................................................................................................................................................... 1 Table of Contents ......................................................................................................................................................................... 2 Block Diagram .............................................................................................................................................................................. 3 Pin Configuration .......................................................................................................................................................................... 3 Pin Descriptions ........................................................................................................................................................................... 4 1. Functionality .......................................................................................................................................................................... 5 1.1. Functional Overview ................................................................................................................................................... 5 2. Power-up & Reset ................................................................................................................................................................. 6 2.1. Reset .......................................................................................................................................................................... 6 2.1.1. Hardware Reset ............................................................................................................................................... 6 2.1.2. Software Reset ................................................................................................................................................ 6 2 3. I C ......................................................................................................................................................................................... 7 4. Configuration ......................................................................................................................................................................... 8 5. Detection ............................................................................................................................................................................... 8 5.1. USB Port Detection ................................................................................................................................................... 10 5.2. Audio Accessory Detection ....................................................................................................................................... 12 5.3. OCP and OVP Detection .......................................................................................................................................... 13 6. Processor Communication .................................................................................................................................................. 13 7. Switch Configuration ........................................................................................................................................................... 13 7.1. Manual Switching ...................................................................................................................................................... 14 8. Active Signal Performance .................................................................................................................................................. 15 8.1. USB Data .................................................................................................................................................................. 15 8.2. FS USB ..................................................................................................................................................................... 15 8.3. Audio ........................................................................................................................................................................ 15 9. Electrical Specifications ...................................................................................................................................................... 16 9.1. Absolute Maximum Ratings ...................................................................................................................................... 16 9.2. Recommended Operating Conditions ....................................................................................................................... 16 9.3. Switch Path DC Electrical Characteristics................................................................................................................. 16 9.4. Capacitance .............................................................................................................................................................. 18 9.5. Switch Path AC Electrical Characteristics ................................................................................................................. 18 9.6. I2C Controller DC Characteristics.............................................................................................................................. 19 9.7. I2C AC Electrical Characteristics & Register Map ..................................................................................................... 19 9.8. Factory Modes .......................................................................................................................................................... 23 9.8.1. Factory-Mode Accessory Detection ............................................................................................................... 23 10. Reference Schematic .......................................................................................................................................................... 26 11. Layout Guidelines ............................................................................................................................................................... 27 11.1. PCB Layout Guidelines for High-Speed USB Signal Integrity .................................................................................. 27 11.2. Layout for GSM/TDMA Buzz Reduction ................................................................................................................... 27 11.3. VBUS_OUT Load Timing Requirements ........................................................................................................................ 27 11.4. Systems with Multiple USB Controllers .................................................................................................................... 28 Physical Dimensions .................................................................................................................................................................. 29 © 2009 Fairchild Semiconductor Corporation FSA9280A • Rev 1.1.0 www.fairchildsemi.com 2 FSA9280A — USB Port Multimedia Switch, Featuring Automatic Select and Accessory Detection Table of Contents FSA9280A — USB Port Multimedia Switch, Featuring Automatic Select and Accessory Detection Block Diagram Phone Power VBAT FSA9280A VBUS_OUT Charger IC CHG_DET Micro USB MIC Audio Codec FS USB or UART HS USB Audio_R Audio_L - Detection OCP,OVP 3:1 MUX and Charge Pump RxD TxD DP_HOST DM_HOST VBUS_IN DM_CON DP_CON ID_CON GND Charger Detect Interrupt I2C Baseband Processor INTB I2C_SCL I2C_SDA Switch Control and I2C Slave VDDIO JIG BOOT Float Detect ADC ID Detect Figure 2. Block Diagram ID_CON DP_CON DM_CON VBUS_IN Pin Configuration 20 19 18 17 Audio_R 1 16 CHG_DET Audio_L 2 15 VBUS_OUT MIC 3 14 I2C_SCL GND Exposed DAP DP_HOST 4 13 I2C_SDA DM_HOST 5 12 INTB RxD 6 11 VBAT TxD BOOT 9 10 JIG 8 VDDIO 7 Figure 3. Pin Assignments (Top View) © 2009 Fairchild Semiconductor Corporation FSA9280A • Rev 1.1.0 www.fairchildsemi.com 3 Pin # Type Default State Description DP_HOST 4 Signal Path Open D+ signal switch path, dedicated USB port to be connected to the resident USB transceiver on the phone DM_HOST 5 Signal Path Open D- signal switch path, dedicated USB port to be connected to the resident USB transceiver on the phone Name USB Interface Audio Interface Audio_L 2 Signal Path Open Left audio channel from mobile phone audio-out CODEC Audio_R 1 Signal Path Open Right audio channel from mobile phone audio-out CODEC MIC 3 Signal Path Open Connected to the mobile phone audio CODEC MIC input pin TxD 7 Signal Path Open Transmitter (Tx) from resident UART on the mobile phone RxD 6 Signal Path Open Receiver (Rx) from resident UART on the mobile phone UART Interface Connector Interface ID_CON 20 Signal Path Open Connected to the USB connector ID pin and used for detecting accessories or button presses DP_CON 19 Signal Path Open Connected to the USB connector D+ pin; depending on the signaling mode, this pin can be switched to DP_HOST, Audio_R, or RxD pins DM_CON 18 Signal Path Open Connected to the USB connector D- pin; depending on the signaling mode, this pin can switched to DM_HOST, Audio_L, or TxD pins VBUS_IN 17 Power Path N/A Input voltage supply pin to be connected to the VBUS pin of the USB connector VBAT 11 Power N/A Input voltage supply pin to be connected to the mobile phone battery output or to an internal regulator on the phone VDDIO 9 Power N/A Baseband processor interface I/O supply pin GND Exposed Center Pad Ground N/A Ground (center ground pad of package makes electrical contact) Power Interface Charger Interface VBUS_OUT 15 Power Path N/A Output voltage supply pin to be connected to the source voltage pin on the charger IC CHG_DET 16 Open-Drain Output Hi-Z Open-drain active LOW output, used to signal the charger IC that a charger has been attached Factory Interface JIG 10 Open-Drain Output Hi-Z Output control signal driven by the FSA9280A and used by the processor for factory test modes BOOT 8 CMOS Output LOW Output control signal driven by the FSA9280A and used by the processor for factory test modes I2C_SCL 14 Input Hi-Z I2C serial clock signal to be connected to the phone-based I2C master I2C_SDA 13 Open-Drain I/O Hi-Z I2C serial data signal to be connected to the phone-based I2C master INTB 12 CMOS Output LOW Interrupt active LOW output used to prompt the phone baseband 2 processor to read the I C register bits, indicates a change in ID_CON pin status or accessory attach status I2C Interface © 2009 Fairchild Semiconductor Corporation FSA9280A • Rev 1.1.0 www.fairchildsemi.com 4 FSA9280A — USB Port Multimedia Switch, Featuring Automatic Select and Accessory Detection Pin Descriptions The FSA9280A offers a complete solution for a single 5-pin USB interface. Through built-in detection algorithms that monitor the ID and VBUS pins of the USB interface, the FSA9280A allows seamless sharing of the interface between HS USB, FS USB or UART, and audio sources. The FSA9280A also offers a complete solution for multiple types of USB chargers. The FSA9280A detects different USB charger types and has a dedicated charger IC interface to allow charging through the devices and dynamic current control by the charger IC based on the type of charger detected. Additional over-current protection (OCP) and up to 28V over-voltage tolerance (OVT) is provided. Flow Diagram Power-up & Reset I2C The detection features are capable of monitoring the ID pin of the USB interface to detect a full array of USB accessories, including audio accessories with up to 12 buttons. 1.1. Functional Overview The FSA9280A is designed for minimal software requirements for proper operation. The flow diagram below shows the basic steps of operation and contains references to more detailed information. State Datasheet Section Description Power-up & Reset Section 2 Applying power to the device and reset states of the device. I2 C Section 3 Communication with device through I2C (which can be bypassed during power-up). Configuration Section 4 Configuring the device using I2C and the internal registers (which can be bypassed during power-up). Detection Section 5 How the detection of the accessory is done including attachment and detachment. Processor Communication Section 6 How the detection of the accessory is indicated to the processor. Switch Configuration Section 7 Configuration of switches based on detection. Active Signal Section 8 Signal performance of selected configuration Configuration Accessory Plug-in Detection Processor Communication Switch Configuration Active Signals Accessory Detached © 2009 Fairchild Semiconductor Corporation FSA9280A • Rev 1.1.0 www.fairchildsemi.com 5 FSA9280A — USB Port Multimedia Switch, Featuring Automatic Select and Accessory Detection 1. Functionality The FSA9280A does not need special power sequencing for correct operation. The main power of the device is provided by either VBUS_IN or VBAT. If VBUS_IN is not present and VBAT is applied, VBAT is used to power the device. VDDIO is only used for I2C interface and interrupt processing. Table 1 summarizes the enabled features of each power state of the FSA9280A. The valid voltages levels for each power supply can be found in Section 9.2. Table 1 – Power States Summary Valid VBUS_IN Valid VBAT Valid VDDIO(1) Power State NO NO NO NO Power Down NO YES(2) NO YES NO Charging through FET Enabled Functionality Processor Communication (I2C & Interrupts) NO NO Detection NO ILLEGAL STATE Powered from VBAT NO NO YES NO YES YES Powered from VBAT NO YES YES YES NO NO Powered from VBUS_IN Yes NO YES YES YES NO Powered from VBAT YES NO YES Powered from VBUS_IN YES YES YES Powered from VBAT YES YES YES YES NO YES YES (2) YES YES Notes: 1. VDDIO is expected to be the same supply used by the baseband I/O‟s. 2. This is not a typical state: both VBAT and VDDIO are typically provided simultaneously. 2.1. Reset When the device is reset, all the registers are initialized to the default values shown in Table 7 and all switch paths are open. After reset or power up, the FSA9280A enters Standby Mode and is ready to detect accessories sensed on its VBUS_IN and / or ID_CON pins. With VDDIO valid, driving both I2C_SDA and I2C_SCL signals LOW for at least 30ms. Note: 3. I2C controllers that implement clock stretching could cause reset. In this case, GPIOs could be used for the I2C interface. 2.1.1. Hardware Reset There are three hardware reset mechanisms: Power-on reset caused by the initial rising edge of VBUS or VBAT 2.1.2. Software Reset The device can be reset through software by writing to the Reset bit in the Register (1BH). The falling edge of VDDIO. © 2009 Fairchild Semiconductor Corporation FSA9280A • Rev 1.1.0 www.fairchildsemi.com 6 FSA9280A — USB Port Multimedia Switch, Featuring Automatic Select and Accessory Detection 2. Power-up & Reset The FSA9280A integrates a fast-mode I2C slave controller compliant with the I2C specification version 2.1 requirements. The FSA9280A I2C interface runs up to 400KHz. The slave address is shown in Table 2. Status information and configuration occurs via the I2C interface. Please see Section 9.7 for more information. Table 2 – I2C Slave Address Name Size (Bits) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Slave Address 8 0 1 0 0 1 0 1 Read / Write 8bits S Slave Address Note: 8bits WR 8bits Register Address K A A Write Data Write Data K+1 A A Write Data K+2 A Write Data K+N-1 A P Single Byte write is initiated by Master with P immediately following first data byte. Figure 4. 8bits 8bits I2C Write Sequence 8bits 8bits S Slave Address WR A Register Address K A S Slave Address RD A Register address to Read specified Note: Read Data K A Read Data K+1 A Read Data K+N-1 NA P Single or multi byte read executed from current register location (Single Byte read is initiated by Master with NA immediately following first data byte) If Register is not specified Master will begin read from current register. In this case only sequence showing in Red bracket is needed I2C Read Sequence Figure 5. From Master to Slave From Slave to Master S A Start Condition Acknowledge (SDA Low) NA NOT Acknowledge (SDA High) WR Write=0 RD P Read =1 Stop Condition VBAT VDDIO SDA 30ms SCL 30ms Internal Reset Time Idle Standby Idle Standby 400µs 400µs I2C Reset Mode Timing Figure 6. © 2009 Fairchild Semiconductor Corporation FSA9280A • Rev 1.1.0 www.fairchildsemi.com 7 FSA9280A — USB Port Multimedia Switch, Featuring Automatic Select and Accessory Detection 3. I2C FSA9280A requires minimal configuration for proper detection and reporting. The following steps can be followed for full configuration. In many cases, only Step 5 needs to be implemented for proper operation. 3. 1. 5. 2. 4. Write Control register (02h) to configure different switching configurations and wait timing. Write Interrupt Mask 1 and 2 registers (05h, 06h) to mask any interrupts not required in the application. Write Timing Set 1 (08h) register to program required key-press timing and ADC-detection timing. Write Timing Set 2 (09h) register to program required Switching Wait timing and Long Key Press timing. Write Control register (02h) to clear INT Mask bit. This enables interrupts to the baseband. 5. Detection The FSA9280A detection algorithms monitor both the VBUS and ID pins of the USB interface. Based on the detection results, multiple registers are updated and the INTB pin is asserted to indicate to the baseband processor that an accessory was detected and to read the registers for the complete information. The detection algorithm allows the application to control the timing of the detection algorithm and the configuration of the internal switches. The flow diagram in Figure 7 shows the operation of the detection algorithm. FSA9280A Standby Mode Accessory Plug-in FSA9280A Detects Accessory Type NO FSA9280A Writes Device Type registers and Attach Interrupt Is Accessory detected a USB or Factory Mode YES FSA9280A autoconf igures switch paths Set INTB Pin LOW (INT MASK bit must have been cleared by µP) FSA9280A Writes Device Type registers and Attach Interrupt NO VDDIO =0V ? µP reads FSA9280A Interrupt Registers FSA9280A set INTB Pin LOW (INT MASK bit must have been cleared by µP) YES FSA9280A waits Switching Wait time µP reads FSA9280A Interrupt Registers NO FSA9280A takes no action until Wait bit is set HIGH by processor NO Detach ? Wait Bit = 1 ? YES YES FSA9280A writes Detach Interrupt Manual Switch = 1? YES NO FSA9280A sets INTB Pin LOW (INT MASK bit must have been cleared by µP) FSA9280A conf igures switches according to Manual SW 1 /2 registers FSA9280A autoconf igures switch paths Detach ? YES FSA9280A writes Detach Interrupt and clears Device Type register FSA9280A set s INTB Pin LOW (INT MASK bit must have been cleared by µP) NO Figure 7. © 2009 Fairchild Semiconductor Corporation FSA9280A • Rev 1.1.0 Detection Flow Chart www.fairchildsemi.com 8 FSA9280A — USB Port Multimedia Switch, Featuring Automatic Select and Accessory Detection 4. Configuration Table 3. determine which accessory is attached. Table 3 shows the assignment of accessories based on resistor values. ID_CON Accessory Detection Binary Value(4) ID_CON Resistance to GND Min. Typ. Max. Accessory Detected(5) 00000 GND GND GND DO NOT USE 00001 1.9k 2.0k 2.1k Audio Send/End Button 00010 2.470k 2.604k 2.730k Audio Remote S1 Button(6) 00011 3.050k 3.208k 3.370k Audio Remote S2 Button(6) 00100 3.810k 4.014k 4.210k Audio Remote S3 Button(6) 00101 4.58k 4.82k 5.06k Audio Remote S4 Button(6) 00110 5.73k 6.03k 6.33k Audio Remote S5 Button(6) 00111 7.63k 8.03k 8.43k Audio Remote S6 Button(6) 01000 9.53k 10.03k 10.53k Audio Remote S7 Button(6) 01001 11.43k 12.03k 12.63k Audio Remote S8 Button(6) 01010 13.74k 14.46k 15.18k Audio Remote S9 Button(6) 01011 16.40k 17.26k 18.12k Audio Remote S10 Button(6) 01100 19.48k 20.50k 21.53k Audio Remote S11 Button(6) 01101 22.87k 24.07k 25.27k Audio Remote S12 Button(6) 01110 27.27k 28.70k 30.14k Reserved Accessory #1 01111 32.3k 34.0k 35.7k Reserved Accessory #2 10000 38.19k 40.20k 42.21k Reserved Accessory #3 10001 47.41k 49.90k 52.40k Reserved Accessory #4 10010 61.66k 64.90k 68.15k Reserved Accessory #5 10011 76.1k 80.7k 84.1k DO NOT USE 10100 96.9k 102.0k 107.1k DO NOT USE 10101 115k 121k 127k TTY Converter 10110 143k 150k 157k UART Cable 10111 190k 200k 206k USB: See Table 4 11000 247.3k 255k 262.7k Factory Mode Boot OFF-USB 11001 292k 301k 310k Factory Mode Boot ON-USB 11010 347k 365k 383k Audio Cradle 11011 428.7k 442.0k 455.3k USB: See Table 4 11100 507.3k 523k 538.7k Factory Mode Boot OFF-UART 11101 600.4k 619k 637.6k Factory Mode Boot ON-UART 750k 1000k 1050k Audio Type 1 with Remote(8) 750k 1002k 1050k Audio Type 1 / Only Send-End(8) 20M Open 11110 11111 USB Mode, Dedicated Charger or Accessory Detach Notes: 4. The binary values are reported in the binary register (07h) with each valid accessory detection. 5. The accessory type is reported in the Device Type 1 (0Bh), Device Type 2 (0Bh), Button 1 (0Ch), and Button 2 (0Dh) registers with each valid accessory detection. 6. These resistor values are created by multiple standard resistor values in series to form the button presses on the wired remote (see Figure 12). 7. For the ID float, ID “open” is recommended; otherwise, capacitance should be minimized. 8. Audio devices with remote and audio devices with only send/end are both reported as Audio Type 1 in the Device Type 1 register (see the Audio Accessory Detection section below). Type 1 is for passive resistor audio accessories and a future Audio Type 2 is designated for active audio accessories. © 2009 Fairchild Semiconductor Corporation FSA9280A • Rev 1.1.0 www.fairchildsemi.com 9 FSA9280A — USB Port Multimedia Switch, Featuring Automatic Select and Accessory Detection The FSA9280A monitors both VBUS_IN and ID_CON to detect accessories. The ID_CON detection is a “resistive detection” that detects the resistance to GND on the ID_CON pin to INTB Asserted BB Reads INTB Configured Switch Closes FLOAT XXXXXX ID Resistance BB read and clear INTB Pin 200ms Open Switch State 10ms wait time Closed Figure 8. ID-Based Accessories, No VBUS_IN Attach Timing with Default Switching Wait Bits of 10ms 5.1. USB Port Detection The multiple types of USB 2.0 ports that the FSA9280A can detect are summarized in Table 4. These devices are unique in that VBUS must be present to detect these accessories. Table 4. ID_CON and VBUS_IN Detection for USB Devices ID_CON Resistance to GND ADC Value(9) VBUS_IN DP_CON DP_CON Min. Typ. Max. 10111 5V X X 190k 200k 206k Car Kit Type 1 Charger(11) 11011 5V X X 428.7k 442k 455.3k Car Kit Type 2 Charger(11) 11111 5V (12) (12) 20M Open Open USB Dedicated Charging Port, Travel Adapter or Dedicated Charger (DCP) 11111 5V (12) (12) 20M Open Open USB Charging Downstream Port (CDP) 5V (12) (12) 20M Open Open USB Standard Downstream Port (SDP) 11111 Accessory Detected(10) Notes: 9. The ADC values are reported in the ADC register (07h) with an each valid accessory detection. 10. The accessory type is reported in the Device Type 1 (0Bh) and Car Kit Status (0Eh) registers with an each valid accessory detection. 11. Follows the ANSI/CEA-936-A USB Car Kit specification. 12. The FSA9280A follow the Battery Charging 1.1 specification, which uses DP_CON and DM_CON to determine what USB accessory is attached (refer to the specification for details). © 2009 Fairchild Semiconductor Corporation FSA9280A • Rev 1.1.0 www.fairchildsemi.com 10 FSA9280A — USB Port Multimedia Switch, Featuring Automatic Select and Accessory Detection Accessory Attached proper connection of the DP_CON and DM_CON before starting the USB charging detection scheme. This feature allows for shorter attach times by eliminating long wait times to allow full contact of the DP_CON and DM_CON pins. Charger FET Closed INTB Asserted and registers written VBUS >4.0V VBUS Voltage XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX FLOAT FLOAT ID Resistance 170ms VBUS_OUT Switch State Closed (CDP Only) CHG_DET Pin 100ms INTB Pin DCD-20ms CHG DETECTION 150ms Figure 9. USB Dedicated Charging Port (DCP) or Charging Downstream Port (CDP) Attach Timing Charger FET Closed USB Switches Closed VBUS >4.0V VBUS_IN XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX FLOAT FLOAT ID Resistance VBUS_OUT DCD Checking 20ms Charger Detection Time 110ms Open USB Switch State Closed 130ms Figure 10. USB Standard Downstream Port Attach Timing Charger FET Closed Configured Switches Closed VBUS >4.0V VBUS Voltage FLOAT XXXXXXXX ID Resistance VBUS_OUT ID Detection Time 200ms Open Switch State CHG_DET Pin 100ms INTB Pin 200ms Figure 11. © 2009 Fairchild Semiconductor Corporation FSA9280A • Rev 1.1.0 Car Kit Type 1 and 2 Attach Timing www.fairchildsemi.com 11 FSA9280A — USB Port Multimedia Switch, Featuring Automatic Select and Accessory Detection The following figures show the attach timing of the USB accessories and the relationship between the INTB assertion and the CHG_DET assertion. FSA9280A implements the optional data contact detection (DCD) feature of the USB Battery Charging specification. The DCD detection ensures Audio accessories are detected when the ID_CON pin resistance to GND is approximately 1MΩ. Configurations for this audio accessory shown in Figure 12 and Figure 13 . Phone FSA 9280A Microphone V BUS_IN ID Detect 2 k? ID _ CON SEND / END Headset with Send/End Only 1 M? DP _ CON Right Earpiece Left Earpiece DM _ CON Figure 12. Audio Accessory with Just Send/End Button (1% or 5% Resistors) Phone FSA9280A Microphone VBUS_IN Headset with Remote ID Detect 604Ω 604Ω 2kΩ ID_ CON SEND/ END S1 S2 806Ω S3 806Ω 1.21kΩ 2kΩ S4 S6 S5 2kΩ 2kΩ S7 S8 2.43kΩ S9 2.8kΩ 3.24kΩ 3.57kΩ S10 S11 976kΩ S12 Hold DP_ CON Right Earpiece Left Earpiece DM_ CON Figure 13. Audio Accessory with Full Wired Remote Control (1% Resistors) The FSA9280A can detect and differentiate between regular key presses, long key presses, and a stuck key. The definition of the key press timing is user configurable by t0 Key Depressed, Timing starts Key tKP tKP-t0 = Key Press bits value Error Key Press tLKP writing the Timing Set 1 (08h) and Timing Set 2 (09h) registers. Timing diagrams for the key press detection are shown below in Figure 14 and Figure 15. t0 tLKP-t0 = Long Key tLKP tKP-t0 = Key Press bits value Long Key Press tKP tLKP-t0 = Long Key Press bits value Press bits value Key KP Bit Set LKP Bit Set LKR Bit Set µP read and clear µP read and clear INTB INTB µP read and clear Figure 14. INTB Released after µP read INTB Released after µP read Regular Key-Press Timing Diagram © 2009 Fairchild Semiconductor Corporation FSA9280A • Rev 1.1.0 Figure 15. INTB Released after µP read Long Key-Press Timing Diagram www.fairchildsemi.com 12 FSA9280A — USB Port Multimedia Switch, Featuring Automatic Select and Accessory Detection 5.2. Audio Accessory Detection With VBUS_IN greater than 6.8V, VBUS_IN is disconnected, protecting the FSA9280A and all application circuitry from excess voltage. This block is capable of withstanding continuous 28V in Shutdown Mode. Upon entering Shutdown Mode, the OVP_EN bit in the Interrupt 1 register is set HIGH and an interrupt is sent to the baseband. The Over-Current Protection (OCP) feature limits current through the charger FET to ≤ 1.5A. The FSA9280A automatically senses an over-current event, shuts down VBUSOUT, and reports this to the baseband by asserting OCP_EN in the Interrupt 1 register. OCP Mode is only implemented when VBUS_IN is provided by the attached accessory. Removal of an OVP or OCP condition triggers another interrupt sent to the processor clearing the OCP_EN and/or the OVP_EN bits and setting the OCP_OVP_DIS bit in the Interrupt 1 register. VBAT VDDIO Standby Mode Internal Reset 100µs INTB Mask bit INTB event INTB 6. Processor Communication TINT_MASK Switch Wait Time Typical communication steps between the processor and the FSA9280A during accessory detection are: 1. a) 2. CHG_DET asserted LOW if USB charger detected. b) Power-up Interrupt Timing Diagram VDDIO Reset Processor reads Interrupt registers to determine which event occurred. a) 3. Figure 16. INTB asserted LOW, indicating change in accessory detection. Interrupt registers read VBAT VDDIO Interrupt 1 (03h): Indicates if an attach, detach, key press, long key press, long key release, OVP / OCP event, or OVP / OCP event recovery was detected. Each bit can be masked by setting the corresponding bit in the Interrupt Mask 1 (05h) register. Standby Mode Internal Reset 100µs INTB Mask bit INTB event INTB Interrupt 2 (04h): Indicates if a reserved accessory, ADC change, stuck key, or stuck key recovery was detected. Each bit can be masked by setting the corresponding bit in the Interrupt Mask 2 (06h) register. TINT_MASK Switch Wait Time Figure 17. Interrupt registers read VDDIO Reset Interrupt Timing Diagram Processor reads Status registers to determine exact accessory detected. a) Device Type 1 (0Ah): Indicates which USB, Car Kit UART, or audio accessory was detected. b) Device Type 2 (0Bh): Indicates which factory mode was detected or if a TTY cable was detected. c) Button 1 (0Ch & ODh): Indicates which button press was detected with Audio Type 1 accessories. d) VBAT VDDIO INTB event INTB event INTB Mask bit INTB Don‟t Care (High or Low) Car Kit Status (0Eh): Indicates which type of car kit charger was detected. Figure 18. TINT_MASK INT Mask to INTB Interrupt Timing Diagram 6.1. Interrupts The baseband processor recognizes interrupt signals by observing the INTB signal, which is active LOW. Interrupts are masked upon reset or power up via the INT Mask register bit (bit 0 of Control register, address 02h in Table 7. Register Map) and INTB pin defaults LOW right after this reset or power up. After the INT Mask bit is cleared by the baseband processor, the INTB pin is driven HIGH in preparation for a future interrupt. When an interruptible event © 2009 Fairchild Semiconductor Corporation FSA9280A • Rev 1.1.0 7. Switch Configuration FSA9280A devices have two modes of operation when configuring the internal switches. The FSA9280A can autoconfigure the switches or the switches can be configured manually by the processor. Typical applications can use the Auto-Configuration Mode and do not require interaction with the baseband to configure the switches correctly. www.fairchildsemi.com 13 FSA9280A — USB Port Multimedia Switch, Featuring Automatic Select and Accessory Detection occurs, INTB transitions LOW and returns HIGH when the processor reads the Interrupt register at address 03h. Subsequent to the initial power up or reset; if the processor writes a “1” to INT Mask bit when the system is already powered up, the INTB pin stays HIGH and ignores all interrupts until the INT Mask bit is cleared. If an event happens that would ordinarily cause an interrupt when the INT Mask bit is set, the INTB pin is LOW for tINT_MASK after the INT Mask bit is cleared. 5.3. OCP and OVP Detection Auto-Configurations FSA9280A VBUS_OUT Charger IC USB: DP_CON=DP_HOST DM_CON=DM_HOST VBUS_OUT=VBUS_IN CHG_DET Micro USB MIC Audio Codec Audio_R Audio_L FS USB or UART RxD TxD HS USB DP_HOST DM_HOST 3:1 MUX Charger IC VBUS_IN DM_CON DP_CON and Charge Pump ID_CON Charger Detect GND FSA9280A VBUS_OUT Audio / Key Pad: DP_CON=Audio_R DM_CON=Audio_L MIC=VBUS_IN TTY: DP_CON=Audio_R MIC=VBUS_IN - Detection OCP,OVP CHG_DET Micro USB MIC Audio Codec FS USB or UART HS USB Audio_R Audio_L 3:1 MUX RxD TxD DP_HOST DM_HOST VBUS_IN DM_CON DP_CON and Charge Pump ID_CON Charger Detect GND FSA9280A VBUS_OUT Charger IC - Detection OCP,OVP CHG_DET Micro USB MIC (13) UART : DP_CON=RxD DM_CON=TxD Audio Codec FS USB or UART HS USB Audio_R Audio_L 3:1 MUX RxD TxD - Detection OCP,OVP DM_CON DP_CON and Charge Pump DP_HOST DM_HOST VBUS_IN ID_CON Charger Detect GND Note: 13. Use of FS USB on the UART path requires manual switching, as described in Section 11.4 — Systems with Multiple USB Controllers. 7.1. Manual Switching Manual switching is enabled by writing the following registers: Manual Switch 1 (13h): Configures the switches for DM_CON, DP_CON, and VBUS_IN. Manual Switch 2 (14h): Configures the CHG_DET, BOOT, and JIG pins. © 2009 Fairchild Semiconductor Corporation FSA9280A • Rev 1.1.0 www.fairchildsemi.com 14 FSA9280A — USB Port Multimedia Switch, Featuring Automatic Select and Accessory Detection Table 5. 8.1. USB Data Figure 19. Pass Through Eye Compliance Testing Input Signal Figure 20. USB 2.0 Eye Compliance Test Results at Output 8.2. FS USB Figure 21. FS USB Eye Compliance for UART Path 8.3. Audio Figure 22. © 2009 Fairchild Semiconductor Corporation FSA9280A • Rev 1.1.0 THD+N Plot for Audio Channels www.fairchildsemi.com 15 FSA9280A — USB Port Multimedia Switch, Featuring Automatic Select and Accessory Detection 8. Active Signal Performance 9.1. Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter VBAT/VDDIO Supply Voltage from Battery / Baseband VBUS_IN VSW IIK ICHG ISW ISWPEAK Supply Voltage from Micro-USB Connector Switch I/O Voltage Min. Max. Unit -0.5 6.0 V V -0.5 28.0 USB -1.0 VBUS+0.5 Stereo / Mono Audio Path Active -1.5 VBAT+0.5 All Other Channels -0.5 VBAT+0.5 Input Clamp Diode Current -50 Charger Detect CHG_DET Pin Current Sink Capability Switch I/O Current (Continuous) mA 30 USB 50 Audio 60 All Other Channels 50 USB 150 Peak Switch Current (Pulsed at Audio 1ms Duration, <10% Duty Cycle) Charger FET mA mA mA 150 All Other Channels TSTG V Storage Temperature Range -65 2 A 150 mA +150 C TJ Maximum Junction Temperature +150 C TL Lead Temperature (Soldering, 10 Seconds) +260 C IEC 61000-4-2 System ESD ESD Human Body Model, JEDEC JESD22-A114 Air Gap USB Connector Pins (DP_CON, DM_CON, VBUS_IN, ID_CON) to GND Contact 15.0 JIG, BOOT, INTB 3.5 All Other Pins, Including DP_CON, DM_CON,ID_CON and VBUS_IN 5.0 Charged Device Model, JEDEC JESD22-C101 All Pins 8.0 kV 2.0 9.2. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol VBAT Parameter Battery Supply Voltage (14) (15) Min. Max. Unit 3.0 4.4 V VBUSIN Supply Voltage from VBUS_IN Pin 4.0 5.5 V VDDIO Processor Supply Voltage 1.8 3.6 V USB Path Active 0 3.6 Audio Path Active -1.2 1.2 0 5.0 VSW Switch I/O Voltage All Other Pins IDCAP TA Capacitive Load on ID_CON Pin for Reliable Accessory Detection Operating Temperature -40 V 1.0 nF +85 ºC Note: 14. Fairchild does not guarantee operation below 3.0V. 15. Between 5.5 to OVP starting voltage, the charger FET is still closed so that charger IC can charge battery even with 5.9~6.0V travel adaptor. © 2009 Fairchild Semiconductor Corporation FSA9280A • Rev 1.1.0 www.fairchildsemi.com 16 FSA9280A — USB Port Multimedia Switch, Featuring Automatic Select and Accessory Detection 9. Electrical Specifications Symbol Parameter VBAT (V) Conditions TA = -40 to +85°C Min. Typ. Max. Unit Host Interface Pins (JIG, BOOT, INTB, CHG-DET) VOH Output High Voltage(16) 3.0 to 4.4 IOH=2mA VOL Output Low Voltage 3.0 to 4.4 IOL=10mA 0.7 x VDDIO V 0.4 V 10 µA 0.100 µA Switch OFF Characteristics Power-Off Leakage Current INO Switch Open Leakage Current with Device Powered 3.0 to 4.4 Short-Circuit Current(17) 3.0 to 4.4 Current Limit if ID_CON=0V IIDSHRT 0 All Data Ports Except MIC VSW=0V to 4.4V IOFF VBAT=4.4V; I/O Pins=0.3V, 4.1V, or Floating, Except MIC -0.100 0.001 5 mA USB Switch ON Path USB Analog Signal Range RONUSB 3.0 to 4.4 (18) USB Switch On Resistance 0 3.0 to 4.4 VD+/D-=0V, 0.4V, ION=8mA 3.6 V 8 10 Ω 6.8 7.2 V Charging FET ON Path VOVP RONFET IOCP Over-Voltage Protection (OVP) Threshold Voltage (17) Charging FET On Resistance VBUS_IN=4.2V-5.0V, ION=1A Over-Current Protection (OCP) Threshold Current(17) VBUS_IN=5.2V 6.2 mΩ 200 1.1 1.3 1.5 A Audio_R/Audio_L Switch ON Paths Audio Analog Signal Range RON RFLAT 3.0 to 4.4 Audio Switch On Resistance(18) Audio RON Flatness(19) -1.2 3.0 to 4.4 VL/R=-0.8V, 0.8V, ION=30mA, 3.0 to 4.4 f=0-470kHz 3.0 V 3 Ω 0.1 Ω 5 V MIC and UART Switch ON Paths Analog Signal Range(20) RON 3.0 to 4.4 MIC Path ON Resistance (17) UART Path ON Resistance 0 3.0 to 4.4 VSW=0V, 4.4V, ION=30mA 40 Ω 25 30 No Accessory Static Current During Standby Mode 10 25 µA With Accessory Static Current During Standby Mode 30 40 µA Total Current Consumption ICCSL ICCSLWA Battery Supply Standby Mode Current (No Accessory Attached) Battery Supply Standby Mode Current with Accessory Attached(21) 3.0 to 4.4 3.8 Notes: 16. Does not apply to CHG_DET or JIG pins because they are open drain. 17. Limits based on electrical characterization data. 18. On resistance is the voltage drop between the two terminals at the indicated current through the switch. 19. Flatness is defined as the difference between the maximum and minimum values of on resistance over the specified range of conditions. 20. The MIC bias applied by the baseband should not exceed 2.8V. 21. Applies to all accessories except Audio Type 1 and Factory-Mode accessories. © 2009 Fairchild Semiconductor Corporation FSA9280A • Rev 1.1.0 www.fairchildsemi.com 17 FSA9280A — USB Port Multimedia Switch, Featuring Automatic Select and Accessory Detection 9.3. Switch Path DC Electrical Characteristics All typical values are at TA=25°C unless otherwise specified. Symbol Parameter VBAT (V) CONUSB DP_CON, DM_CON On Capacitance (USB Mode) 3.8 Condition TA = -40 to +85°C Min. VBIAS=0.2V, f=1MHz Typ. Max. 8 Unit pF 9.5. Switch Path AC Electrical Characteristics All typical values are for VBAT=3.8V at TA=25ºC unless otherwise specified. Symbol Parameter OIRR PSRR THD Active Channel Crosstalk DP_CON to DM_CON Off Isolation TA = -40 to +85°C Min. Typ. Max. f=20kHz, RT=32Ω, CL=0pF -50 f=1MHz, RT=50Ω, CL=0pF -60 f=240MHz, RT=50Ω, CL=0pF -40 Audio Mode f=20kHz, RT=32Ω, CL=0pF -90 USB Mode f=1 MHz, RT=50Ω, CL=0pF -90 Power Supply Noise 300mVpp, f=217Hz -100 20Hz to 20kHz, RL=32/16Ω, Input Signal Range 2VPP 0.03 20Hz to 20kHz, RL=32/16Ω, Input Signal Range -1.2V to 1.2V 0.05 tr=tf=750ps (10-90%) at 240MHz, CL=0pF, RL=50Ω 30 Audio Mode Xtalk Condition USB Mode Power Supply Rejection Ratio, MIC on VBUS_IN Total Harmonic Distortion (Audio Path) Unit dB dB dB % tSK(P) Skew of Opposite Transitions of the Same Output (USB Mode) tI2CRST Time When I2C_SDA and I2C_SCL Both LOW to Cause a Reset See Figure 6 tINTMASK Time after INT Mask Cleared to “0“ until INTB Goes LOW to Signal the Interrupt after Interruptible Event while INT Mask Bit Set to “1” See Figure 18 10 ms tSDPDET Time from VBUS_IN Valid to VBUS_OUT Valid with Charger FET Closed and USB Switches Closed for USB Standard Downstream Port See Figure 10 130 ms tCHGOUT Time from VBUS_IN Valid to VBUS_OUT Valid with the Charger FET Closed for Both USB Charging Ports (CDP and DCP) See Figure 9 170 ms tCARKIT Time from VBUS_IN Valid to Car Kit Type 1 or Type 2 Charger Detected See Figure 11 200 ms tCHGDET Time from VBUS_OUT Valid to CHG_DET Output LOW for Both USB Charging Ports (CDP and DCP) and for Car Kit Chargers See Figure 9, Figure 11 100 ms Time from ID_CON Not Floating to INTB LOW to Signal Accessory Attached that is ID_CON Resistance-Based Only (VBUS_IN Not Valid) See Figure 8 200 ms Time from VBUS_IN Valid to JIG LOW and VBUS_OUT Valid with Charger FET Closed for Both Factory Mode Operation with VBUS_IN Present See Figure 25 200 ms Time from VBUS_IN Valid to JIG LOW for Factory Mode Operation without VBUS_IN Present See Figure 26 200 ms tIDDET tJIGVBUS © 2009 Fairchild Semiconductor Corporation FSA9280A • Rev 1.1.0 30 ps ms www.fairchildsemi.com 18 FSA9280A — USB Port Multimedia Switch, Featuring Automatic Select and Accessory Detection 9.4. Capacitance Symbol Fast Mode (400kHz) Parameter Min. Max. Units 0.3VDDIO V VIL Low-Level Input Voltage -0.5 VIH High-Level Input Voltage 0.7VDDIO VHYS Hysteresis of Schmitt Trigger Inputs VOL1 Low-Level Output Voltage at 3mA Sink Current (Open-Drain) VDDIO>2V 0.05VDDIO VDDIO<2V 0.1VDDIO VDDIO>2V 0 V V 0.4 VDDIO<2V 0.2VDDIO II2C Input Current of I2C_SDA and I2C_SCL Pins, Input Voltage 0.26V to 2.34V CI Capacitance for Each I/O Pin -10 V 10 µA 10 pF 9.7. I2C AC Electrical Characteristics & Register Map Symbol fSCL tHD;STA Fast Mode Parameter Min. Max. Unit 0 400 kHz SCL Clock Frequency Hold Time (Repeated) START Condition 0.6 µs tLOW LOW Period of SCL Clock 1.3 µs tHIGH HIGH Period of SCL Clock 0.6 µs tSU;STA Set-up Time for Repeated START Condition 0.6 µs tHD;DAT Data Hold Time tSU;DAT Data Set-up Time(22) tr tf tSU;STO 0 0.9 µs 100 (23) Rise Time of SDA and SCL Signals (23) Fall Time of SDA and SCL Signals ns 20+0.1Cb 300 20+0.1Cb 300 ns ns Set-up Time for STOP Condition 0.6 µs tBUF BUS-Free Time between STOP and START Conditions 1.3 µs tSP Pulse Width of Spikes that Must Be Suppressed by the Input Filter 0 50 ns Notes: 22. A fast-mode I2C-Bus® device can be used in a standard-mode I2C-Bus system, but the requirement tSU;DAT ≥ be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr_max + tSU;DAT = 1000 + 250 = 1250ns (according to the standard-mode I2C bus specification) before the SCL line is released. 23. Cb equals the total capacitance of one BUS line in pF. If mixed with high-speed devices, faster fall times are allowed according to the I2C specification. Figure 23. Definition of Timing for Full-Speed Mode Devices on the I2C Bus Table 6. I2C Slave Address Name Size (Bits) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Slave Address 8 0 1 0 0 1 0 1 R/W © 2009 Fairchild Semiconductor Corporation FSA9280A • Rev 1.1.0 www.fairchildsemi.com 19 FSA9280A — USB Port Multimedia Switch, Featuring Automatic Select and Accessory Detection 9.6. I2C Controller DC Characteristics Table 7. Register Map Address Register Type Reset Value 01H Device ID Read 00000000 02H Control Read / Write Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Version ID: 0xb001 Reserved: - Read XXX - Write 000 00011111 04H Interrupt 1 Interrupt 2 Read / Clear Read / Clear 00000000 00000000 Switch Open ADC Interrupt Disable Manual Switch Configuration Delay Global Interrupt Mask 0: Open All switches 0: Report interrupt when detection is complete on ID_CON 0: Automatic configuration disabled, switch configuration based on Manual Switch registers (13H, 14H) 0: After wait time expires delay configuration indefinitely until this bit is written to 1 by host 0: Does not Mask Interrupts 1: Automatic configuration is enabled 1: If wait time has expired configure the switches immediately (See figure 2(flow chart)) 1: Mask interrupts Detach Attach 1: Accessory detached 1: Accessory attached OVP & OCP OCP Event OVP Event Long Key Release Long Key Press Key Press Recovery 0: OVP and/or OCP event 0: No OCP event 0: No OVP event 0: No Interrupt not recovered 1: OVP and/or 1: Long key 1: Long key press 1: Key press OCP event 1: OCP event 1: OVP event release detected detected detected recovered Stuck Key Stuck Key ADC Change Recovery Reserved: - Read XXX 0: No Interrupt - Write 000 1: Stuck key 1: Stuck key 1: Valid ADC recovered detected detection OVP & OCP 05H 06H 07H 08H 09H Interrupt Mask 1 Read / Write OCP OVP Long Key Release Long Key Press Reserved Attach 1: Reserved accessory attached Reserved: - Read X - Write 0 Key Press Detach Attach 1: Mask – Interrupt 1 [Attach] 0: No Interrupt Mask 00000000 1: Mask – 1: Mask – 1: Mask – Interrupt 1 Interrupt 1 [OCP Interrupt 1 [OVP [OVP & OCP Event] Event] Recovery] Reserved: - Read XXX - Write 000 1: Mask – Interrupt 1 [Long Key Release] 1: Mask – Interrupt 1 [Long Key Press] 1: Mask – Interrupt 1 [Key Press] 1: Mask – Interrupt 1 [Detach] Stuck Key Recovery Stuck Key ADC Change Reserved Attach Interrupt Mask 2 Read / Write 00000000 ADC Read 00011111 Reserved: - Read XXX, - Write 000 ADC Value (See Table 8) 00000000 Key Press Time (See Table 8) ADC Detection Time (See Table 8) 00000000 Switching Wait Time (See Table 8) Long Key Press Time (See Table 8) Timing Set Read / 1 Write Timing Set Read / 2 Write Bit 0 Vendor ID (Fairchild): 000 1: Switch based on 1: ADC change detection interrupt is disabled 03H Bit 1 0: No Interrupt Mask 1: Mask – Interrupt 2 [Stuck Key Recovery] 1: Mask – Interrupt 2 [Stuck Key] 1: Mask – Interrupt 2 [ADC Change] 1: Mask – Interrupt 2 [Reserved Attach] Reserved: - Read X - Write 0 Continued on the following page… © 2009 Fairchild Semiconductor Corporation FSA9280A • Rev 1.1.0 www.fairchildsemi.com 20 Address 0AH Register Device Type 1 Type Read Reset Value 00000000 Bit 7 Reserved: - Read X - Write 0 Bit 6 Bit 5 USB Charging (DCP) USB Charging (CDP) Bit 4 Bit 3 Car Kit Charger Bit 2 UART 0: No detect 1: USB 1: USB charging dedicated 1: Car Kit charger downstream port charging port detected (CDP) detected (DCP) detected 0BH Read Reserved: - Read XX - Write 00 00000000 Button 7 0CH Button 1 Read Reserved: - Read X - Write 0 1: USB standard downstream port (SDP) detected 1: UART detected 0: No detect 1: Audio Type 1 accessory detected Factory Mode – See Table 9 0: No detect 1: TTY detected Button 6 Bit 0 Audio Type 1 USB Data (SDP) TTY Device Type 2 Bit 1 Button 5 Reserved: - Read X - Write 0 0: No detect Button 4 00000000 1: Jig: UART – Boot_OFF 1: Jig: UART – Boot_ON 1: Jig: USB – Boot_OFF 1: Jig: USB – Boot_ON Button 3 Button 2 Button 1 Send End Button 10 Button 9 Button 8 0: Not Pressed 1: Pressed Key Press Error 0DH Button 2 Read 00000000 Reserved: - Read XX - Write 00 Button 12 Button 11 0: No Key Press Error 1: Key Press Error detected (too short) 0: Not Pressed 1: Pressed Charger Type Reserved: - Read XXXXXX - Write 000000 00: No connection 01: Reserved Charger 10: Car Kit charger type 1 11: Car Kit charger type 2 0EH Car Kit Status Read 00000000 0FH Reserved N/A 00000000 Reserved: - Read XXXXXXXX, - Write 00000000 10H Reserved N/A 00000000 Reserved: - Read XXXXXXXX, - Write 00000000 11H Reserved N/A 00000000 Reserved: - Read XXXXXXXX, - Write 00000000 12H Reserved N/A 00000000 Reserved: - Read XXXXXXXX, - Write 00000000 DM_CON Connection 13H Manual Switch 1 Read / Write 14H Manual Switch 2 Read / Write 00000000 00000000 000: Open DM_CON switch 001: DM_CON connected to DM_HOST of USB port 010: DM_CON connected to Audio_L 011: DM_CON connected to TxD of UART port Reserved: - Read XXX - Write 000 DP_CON Connection VBUS Connection 000: Open DP_CON switch 001: DP_CON connected to DP_HOST of USB port 010: DP_CON connected to Audio_R 011: DP_CON connected to RxD of UART port CHG_DET BOOT JIG 0: High Impedance 0: Low 0: High Impedance 1: Low 1: High 1: Low 00: Open VBUS switch 01: VBUS_OUT connected to VBUS_IN (Host – current sourced from the phone to accessory, max. load current is 5mA) 10: VBUS_IN connected to MIC 11: VBUS_IN connected to VBUS_OUT (Standard USB – phone sinks current from attached accessory) Reserved: - Read XXX - Write 000 Continued on the following page… © 2009 Fairchild Semiconductor Corporation FSA9280A • Rev 1.1.0 www.fairchildsemi.com 21 Address Register Type Reset Value 15H Reserved N/A 00000000 Reserved: - Read XXXXXXXX, - Write 00000000 16H Reserved N/A XXXXXXX0 Reserved: - Read XXXXXXXX, - Write 00000000 17H Reserved N/A 00000000 Reserved: - Read XXXXXXXX, - Write 00000000 18H Reserved N/A 00000000 Reserved: - Read XXXXXXXX, - Write 00000000 19H Reserved N/A 00000000 Reserved: - Read XXXXXXXX, - Write 00000000 1AH Reserved N/A 00000000 Reserved: - Read XXXXXXXX, - Write 00000000 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset 1BH Reset R/W X0001000 1CH Reserved N/A XXXXX001 0: No Reset 1: Reset (Always reads 0) Reserved: - Read XXXXXXX, - Write 0000100 Reserved: - Read XXXXXXXX, - Write 00000001 VBUS_IN VALID 1DH Reserved N/A 00000000 Reserved: - Read XXXXXXXX, - Write 00000000 0: VBUS_IN Not Valid 1: VBUS_IN Valid 1EH Reserved N/A 1FH Reserved N/A XXXXXXX X XXXXXXX X 20H DCD Configuration Read/Write XXXXXX00 21H Reserved N/A XXXXXX00 © 2009 Fairchild Semiconductor Corporation FSA9280A • Rev 1.1.0 Reserved: - Read X, Write 0 Reserved: - Read XXXXXXXX, - Write 00000000 Reserved: - Read XXXXXXXX, - Write 00000000 Reserved: - Read XXXXXXXX, - Write 00000000 Enable DCD Timeout 0: DCD Timeout Not Enabled 1: DCD Timeout Enabled Reserved: Read XX, - Write 00 Reserved: - Read XXXXXXXX, - Write 00000000 www.fairchildsemi.com 22 Setting Value(24) ADC Detection Time Key Press Time 0000 50ms 100ms 300ms 10ms 0001 100ms 200ms 400ms 30ms 0010 150ms 300ms 500ms 50ms 0011 200ms 400ms 600ms 70ms 0100 300ms 500ms 700ms 90ms 0101 400ms 600ms 800ms 110ms 0110 500ms 700ms 900ms 130ms 0111 600ms 800ms 1000ms 150ms 1000 700ms 900ms 1100ms 170ms 1001 800ms 1000ms 1200ms 190ms 1010 900ms 1300ms 210ms 1011 1000ms 1400ms 1100 Long Key Press Time Switching Wait Time 1500ms 1101-1111 Note: 24. Each of the four registers can have unique register setting values. JIG output signals when a factory-mode accessory is plugged in and BOOT output signals the baseband processor to boot up, allowing tests to be conducted with and without the baseband processor powered up. As soon as the factory-mode cable is removed, the FSA9280A returns to a standard accessory flow that requires a device detach between accessory type configurations changes (except Audio Type 1 accessory described in the Audio Accessory Detection section above). The typical key sensing for Audio Type 1 accessories for wired remote is not active for factory-mode test. 9.8. Factory Modes The FSA9280A has four dedicated Factory Modes that allow efficient factory testing of a platform. Factory Modes are initiated with the attachment of special test hardware, called a “JIG box” used for factory testing. FSA9280A automatically configures switch paths to any factory-mode accessories when VDDIO is present, without detaching and attaching the micro-USB cable. Since the processor may not be awake when a factory-mode accessory is detected, I2C read acknowledge is not required, nor does the FSA9280A employ a switching wait timer found in the Timing Set 2 register for the initial switch configuration. A change of resistor on the ID_CON pin dynamically switches between factory modes and auto-configures the appropriate switch paths without detaching and attaching the cable. 9.8.1. Factory-Mode Accessory Detection The different factory-mode accessories with the associated resistor values (1% standard resistors) on the ID_CON pin, the JIG and BOOT logic states, and switch configurations are listed in Table 9. Table 9. Factory Mode Auto-Configuration Table (1% Resistors on ID_CON Pin) Configuration Type Factory Mode 0 Jig: UART Factory Mode 1 Jig: USB Audio Type 1 (25) VBUS_IN DP_CON DM_CON ID_CON BOOT JIG CHG_DET Boot_On Chg FET Open(25) RxD TxD 619kΩ HIGH LOW Hi-Z Boot_Off Chg FET Open(25) RxD TxD 523kΩ LOW LOW Hi-Z Boot_On Chg FET Closed DP_Host DM_Host 301kΩ HIGH LOW Hi-Z Boot_Off Chg FET Closed DP_Host DM_Host 255kΩ LOW LOW Hi-Z Full Remote (26) Audio_R Audio_L 1000kΩ LOW LOW Hi-Z Send/End Remote (26) Audio_R Audio_L 1002kΩ LOW LOW Hi-Z © 2009 Fairchild Semiconductor Corporation FSA9280A • Rev 1.1.0 www.fairchildsemi.com 23 FSA9280A — USB Port Multimedia Switch, Featuring Automatic Select and Accessory Detection Table 8 – Timing for Timing Set 1 & 2 Registers Standby FSA9280A Detects JIG Attachment FSA9280A Writes Device Register and Asserts JIG LOW NO VDDIO HIGH? YES INTB Asserted and Switch Paths AutoConfigured per Table 9 µP Reads Interrupt Registers FSA9280A Enters Standby YES NO YES ID Float >70ms NO Exit Factory Mode Accessory Flow NO ID Change? YES Rid=Factory Mode or Audio Type 1 Value Figure 24. © 2009 Fairchild Semiconductor Corporation FSA9280A • Rev 1.1.0 Factory Mode Flow www.fairchildsemi.com 24 FSA9280A — USB Port Multimedia Switch, Featuring Automatic Select and Accessory Detection Notes: 25. The charger FET closes for factory-mode BOOT ON-UART or factory-mode BOOT OFF-UART if VBUS_IN is valid only during the time when the cable is first plugged in or a new ID_CON resistor is detected. 26. Audio-type device configuration is entered as part of the factory-mode flow shown in Figure 24 where the ID_CON pin is not monitored for key presses and JIG remains LOW until the factory jig box is detached from the phone. MIC is not connected in this audio type case. Figure 24 provides the attach flow diagram for the JIG box accessory. If any of the factory modes is first entered and JIG=LOW; then and only then, can the ID_CON resistor (1MΩ) dynamically switch to Audio Type 1 accessory without a cable detach. For the latter case, factory-mode Audio Type 1 accessory autoconfigures the switches such that: Audio_L = DM_CON. 27. MIC is left unconnected. 28. The typical key sensing for Audio Type 1 accessories for wired remote is not active for this factory-mode test. VBUS_OUT ID Resistance FLOAT XXXXXXXX JIG Pin ID detection time 200ms BB wake-up time VDDIO BOOT Pin Open Switch State Closed Figure 25. ID Resistance FACTORY Box Attach Timing (VBUS_IN Valid) FLOAT XXXXXX JIG Pin ID detection time 200ms BB wake- up time VDDIO BOOT Pin Open Switch State Closed Figure 26. © 2009 Fairchild Semiconductor Corporation FSA9280A • Rev 1.1.0 FACTORY Box Attach Timing without VBUS_IN www.fairchildsemi.com 25 FSA9280A — USB Port Multimedia Switch, Featuring Automatic Select and Accessory Detection VBUS >4.0V VBUS_IN VBAT VBUS_OUT 1µF 1µF Battery VBAT PMIC VDDIO 100k VDDIO VBUS_IN 1.2~ 10k 1.2~ 10K TVS VBR ≤ 32V RON ≤ 1.4Ω 1µF SDA SCL INTB SDA SCL GPIO DP_CON 1pF TVS D+ D+ D- AP or DBaseband DM_CON 1pF TVS ID_CON TxD GPIO 1pF TVS TxD RxD RxD Optional (leave open if not used) 1.8 ~ 3.6V 1µF JIG JIG_ON 2.2 2.2 Micro USB Connector 2.2 GND BOOT MIC bias VDDIO Audio CODEC MIC Audio_R Audio_L Figure 27. © 2009 Fairchild Semiconductor Corporation FSA9280A • Rev 1.1.0 10k CHG_DET Optional (leave open if not used) Baseband or Charger IC Reference Schematic www.fairchildsemi.com 26 FSA9280A — USB Port Multimedia Switch, Featuring Automatic Select and Accessory Detection 10. Reference Schematic 11.1. PCB Layout Guidelines for High-Speed USB Signal Integrity 1. Place FSA9280A as close to the USB controller as possible. Shorter traces mean less loss, less chance of picking up stray noise, and may radiate less EMI. a) Keep the distance between the USB controller and the device less than one inch (< 1in). b) For best results, this distance should be <18mm. This keeps it less than one quarter (¼) of the transmission electrical length. 2. Use an impedance calculator to ensure 90Ω differential impedance for DP_COM/DM_CON lines. 3. Select the best transmission line for the application. a) 4. 11.2. Layout for GSM/TDMA Buzz Reduction There are two possible mechanisms for TDMA/GSM noise to negatively impact the FSA9280A device‟s performance. The first is the result of large current draw by the phone transmitter during active signaling when the transmitter is at full or almost full power. With the phone transmitter dumping large amounts of current in the phone GND plane; it is possible for there to be temporary voltage excursions in the GND plane if not properly designed. This noise can be coupled back up through the GND plane into the FSA9280A device and, although the FSA9280A has very good isolation; if the GND noise amplitude is large enough, it can result in noise coupling to the VBUS_IN/MIC pin. The second path for GSM noise is through electromagnetic coupling onto the signal lines themselves. In most cases, the noise introduced as a result of this noise is on the VBAT and/or GND supply rails. Following are recommendations for PCB board design that help address these two sources of TDMA/GSM noise. For example, for a densely populated board, select an edge-coupled differential stripline. Minimize the use of vias and keep HS USB lines on same plane in the stack. 1. Provide a wide, low-impedance GND return path to both the FSA9280A and to the power amplifier that sources the phone transmit block. Try to avoid routing schemes that generally force the use of at least two vias: one on each end to get the signal to and from the surface. 2. Provide separate GND connections to PCB GND plane for each device. Do not share GND return paths between devices. 5. Cross lines, only if necessary, orthogonally to avoid noise coupling (traces running in parallel couple). 3. 6. If possible, separate HS USB lines with GND to improve isolation. Add as large a decoupling capacitor as possible (1µF) between the VBAT pin and GND to shunt any power supply noise away from the FSA9280A. Also add decoupling capacitance at the PA (see the reference application schematic in Figure 27 for recommended decoupling capacitor values). 4. Add 33pF shunt capacitors on any PCB nodes with the potential to collect radiated energy from the phone transmitter. At a minimum, add these 33pF capacitors to the MIC pin (see Figure 27). 5. Add a series RBAT resistor prior to the decoupling capacitor on the VBAT pin to attenuate noise prior to reaching the FSA9280A. a) Vias are an interruption in the impedance of the transmission line and should be avoided. b) a) Routing GND, power, or components close to the transmission lines can create impedance discontinuities. 7. Match transmission line pairs as much as possible to improve skew performance. 8. Avoid sharp bends in PCB traces; a chamfer or rounding is generally preferred. 9. Place decoupling for power pins as close to the device as possible. a) Use low-ESR capacitors for decoupling if possible. b) A tuned PI filter should be used to negate the effects of switching power supplies and other noise sources if needed. © 2009 Fairchild Semiconductor Corporation FSA9280A • Rev 1.1.0 11.3. VBUS_OUT Load Timing Requirements The FSA9280A includes over-current protection (OCP) used to protect the FSA9280A and any downstream devices from a high-current event. In addition, the FSA9280A has an inrush-limiting feature that helps protect against high-current transient currents during initial charger FET closure. For these two reasons, it is recommended that the system designer delay current draw >250mA from the FSA9280A VBUS_OUT pin until at least 10ms after VBUS_OUT is valid. Failure to observe this timing requirement could result in false OCP triggering and, in some cases, could result in the FSA9280A staying in OCP Mode until the load is removed and re-attached. www.fairchildsemi.com 27 FSA9280A — USB Port Multimedia Switch, Featuring Automatic Select and Accessory Detection 11. Layout Guidelines Many phone platforms have separate full-speed and highspeed controllers; however, the FSA9280A only has one designated USB switch path. The FSA9280A high-speed USB path is only designed to allow one HS USB controller to be multiplexed on to the USB connector. To allow for multiple USB controllers on the USB port, it may be tempting to use one of Fairchild‟s existing USB switches to multiplex the HS and FS controllers onto the shared HS USB switch path of the FSA9280A, as illustrated in Figure 28. It is NOT recommended that the USB signals be multiplexed at the input the FSA9280A DP_Host or DM_Host pins for the following reasons: MAP or V/P High Speed USB Standard USB switches like the FSUSB42 are also passive and cannot improve a USB signal. They result in a slight degradation of the HS USB signal as well. When placed in series, as shown in Figure 28, the cumulative effect of the two series passive USB switches impacts the HS eye performance and could result in failure of the HS eye mask test per the USB 2.0 specification. When factoring in the additional routing required for the two switches in series and the additional signal path discontinuities introduced, the likelihood of eye degradation is increased. High Speed USB Full Speed USB DM_Host TxD FSA9280A DM_Con ID Figure 29. RECOMMENDED Configuration for Systems with High-Speed, Full-Speed, and UART In every case where the FS USB path is not routed through the dedicated USB path of the FSA9280A, the phone designers must place the FSA9280A into manual mode to configure the switch path properly. On initial attachment of a USB accessory, the FSA9280A detects and auto-configures for USB, resulting in the DP_Con and DM_Con pins being connected to the DP_Host and DM_Host pins, respectively. In this configuration, the HS USB controller is automatically connected and no further action is needed by the baseband to send and receive data from the HS controller. For the application shown in Figure 29, the FSA9280A must be changed to manual mode to enable FS USB through the UART TxD and RxD switch paths. After initial USB detection and attach signaled by the FSA9280A, do the following: DM_Con 1. Write the hex value „1A‟ to the Control register (02h) (see Table 7. Register Map). This enables Manual Switch Mode and the FSA9280A automatically opens all switch paths, breaking the HS USB signal path and forcing the USB host to re-enumerate when the FS device is configured. 2. To configure the FSA9280A switch paths such that the FS device is connected through the UART switch path, write the hex value „6Ch‟ into the Manual Switch register (13h) >125µs later to ensure enumeration. This connects the RxD and TxD to DP_CON and DM_CON, respectively. 3. When FS USB data communication is complete, disable manual switch mode by writing „1E‟ back in to the Control register (02h). 4. Configure the FSUSB42 input select back to the UART source to allow UART communication. ID NOT RECOMMENDED — Multiplexing High-Speed and Full-Speed USB onto the DP_Host, DM_Host For the reasons outlined above, it is recommend that only the HS USB controller be connected to the FSA9280A DP_Host and DM_Host pins. The following solutions are recommended for those applications that require both a HS and FS USB controller. The FSA9280A must be used for all of these solutions since it has the available UART switch path. The HS USB signal is highly sensitive and should only be routed through the specially designed HS USB signal path of the FSA9280A. Conversely, the FS USB signal operates at much slower data rates, which makes it much more resilient to signal path discontinuities. FS USB only © 2009 Fairchild Semiconductor Corporation FSA9280A • Rev 1.1.0 Txd RxD Txd GND D- Figure 28. FSA9280A DP_Con Rxd Rxd Connector D+ D+ D- UART DP_Con DP_Host Connector GND Vbus FSUSB42 (DPDT USB 2.0 Switch) DM_HOST FSUSB42 D+ D- DP_HOST D- Vbus Baseband Full Speed USB The FSA9280A employs a passive USB switch path. It does not buffer, amplify, or enhance the USB signal in any way. The FSA9280A is designed to have minimal impact on the HS USB eye performance; however, there is some limited reduction in signal amplitude and edge rate resulting from the inherent resistance and capacitance of the USB switch within the FSA9280A. D+ www.fairchildsemi.com 28 FSA9280A — USB Port Multimedia Switch, Featuring Automatic Select and Accessory Detection operates at 12Mbps and has a full 3.6V swing, which makes it much less sensitive to capacitive loading. Compared to HS USB, FS USB has a large voltage swing, which makes it less sensitive to switch on resistance. Therefore, the FS USB signal can be alternately routed through the UART signal path. Figure 29 provides an alternative application diagram. 11.4. Systems with Multiple USB Controllers 0.10 C 3.00 2X A 2.80 B 1.70 PIN1 IDENT 3.80 4.00 2.70 0.60 20X 0.10 C 2X TOP VIEW 0.55 MAX 0.30 20X A 0.10 C 0.08 C 0.50 RECOMMENDED LAND PATTERN (0.15) 0.05 0.00 C SIDE VIEW SEATING PLANE NOTES: 1.70 1.60 A. PACKAGE CONFORMS TO JEDEC MO-220 EXCEPT WHERE NOTED. 10 7 B. DIMENSIONS ARE IN MILLIMETERS. 6 11 C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. D. DRAWING FILENAME: MKT-UMLP20Arev1. 2.70 2.60 E. LAND PATTERN RECOMMENDATION IS BASED ON FSC DESIGN ONLY 0.25 20X 0.15 16 1 PIN 1 IDENT 20 17 0.10 0.05 C A B C 0.45 20X 0.35 0.50 BOTTOM VIEW Figure 30. 20-Lead Ultrathin Molded Leadless Package (UMLP), 3 x 4 x 0.55mm, 0.5mm Pitch Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/packaging/3x4UMLP20_TNR.pdf. Part Number Operating Temperature Range Top Mark Package FSA9280AUMX -40 to +85°C 9280A 20-Lead Ultrathin Molded Leadless Package (UMLP), 3 x 4 x 0.55mm, 0.5 Pitch © 2009 Fairchild Semiconductor Corporation FSA9280A • Rev 1.1.0 www.fairchildsemi.com 29 FSA9280A — USB Port Multimedia Switch, Featuring Automatic Select and Accessory Detection Physical Dimensions FSA9280A — USB Port Multimedia Switch, Featuring Automatic Select and Accessory Detection 30 www.fairchildsemi.com © 2009 Fairchild Semiconductor Corporation FSA9280A • Rev 1.1.0