TSU6712 SCDS321 – MAY 2011 www.ti.com SP4T SWITCH WITH IMPEDANCE DETECTION MICRO-USB SWITCH TO SUPPORT USB, UART, AUDIO, AND VIDEO Check for Samples: TSU6712 FEATURES 1 • Detection is Compatible to CEA-936A (4-Wire Protocol, UART Interface) USB Path Supports USB 2.0 High Speed Support Control Signals (USB, UART JIG) Used in Manufacturing (JIG, BOOT) Interrupt for Attach and Detach Accessory Compatible Accessories – USB Cable, UART Cable, TV Out Cable – Mono, Stereo Headset – Remote Controller for DMB – Car Kit – CEA-936A – Charging + TV Out – Charging + Stereo Headset ESD Performance Tested Per JESD 22 – 1500-V Human-Body Model (A114-B, Class II) – 1000-V Charged-Device Model (C101) ESD Performance DP/DM/ID/VBUS to GND – ±6-kV Contact Discharge (IEC 61000-4-2) Surge Protection on VBUS, DP and DM USB Connector Pins. • • • • • • • 1 2 3 4 5 A INTB VDDIO ISET OUT VBUS B D+ SDA S_L MIC DM C D- SCL V_L S_R DP D VBAT IDBP V_R VIDEO ID E RxD TxD BOOT JIG GND DESCRIPTION The TSU6712 is a multiple SP4T switch with impedance detection. The switch features impedance detection, which supports the detection of various accessories that are attached through DP and DM. The detection is based on the impedance values of the accessories as defined in Table 1. The TSU6712 is fully controlled using I2C and enables USB data, stereo and mono audio, video, microphone, and UART data to use a common connector port. APPLICATIONS • • • • • RVC PACKAGE (TOP VIEW) Cell Phones & Smart Phones Tablet PCs Digital Cameras & Camcorders GPS Navigation Systems Micro USB interface with USB/UART/Audio/Video Power for this device is supplied through VBAT of the system or through VBUS when attached. The switch can be controlled through I2C. JIG and BOOT pins are used when a USB, UART JIG cable is used to test during development and manufacturing. Table 1. ORDERING INFORMATION (1) TA –40°C to 85°C (1) (2) (3) PACKAGE (2) WCSP 0.4-mm pitch – YFP ORDERABLE PART NUMBER Tape and reel TSU6712YFPRB TOP-SIDE MARKING 56N (3) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. Last 3 letters of the top-side marking. The top-side marking is 6 letters. First 3 letters indicate manufacturing date and lot number. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated TSU6712 SCDS321 – MAY 2011 www.ti.com APPLICATION BLOCK DIAGRAM VDDIO Xlators Switches OUT SDA Sw. Chg. Pump D+ D- SCL Clock Sources Load Switch Sense & Ctrl. State Machine I2C Interface & Registers INTB JIG BOOT IDBP V_L ISET VIDEO Carkit & Sw. Ctrl. S_L S_R Buffers and/or Comparators MIC VBUS DP DM Carkit Interface ID TxD RxD Charger Detection Sources and Comp’s. Accessory ID Detection ADC Supervisor And Pwr. Sel. VBAT VPOWER (all ckts) Reset AVSS 2 Copyright © 2011, Texas Instruments Incorporated TSU6712 SCDS321 – MAY 2011 www.ti.com TERMINAL FUNCTIONS TERMINAL Ball NO. NAME I/O DESCRIPTION D1 VBAT – 3.0 – 4.4V Battery supply voltage A2 VDDIO – 1.8 ~ 3.3V Logic Supply A5 VBUS I USB connector VBUS A4 OUT O Phone charger output E5 GND – Ground B1 D+ I/O USB data + C1 D- I/O USB data - D2 IDBP I/O USB ID data E1 RxD I/O UART receive data E2 TxD I/O UART transmit data D3 V_R I/O TV-out right sound C3 V_L I/O TV-out left sound D4 VIDEO I/O TV-out encoded video B4 MIC I/O Microphone signal C4 S_R I/O Stereo headset right sound B3 S_L I/O Mono or stereo headset left sound C2 SCL I I2C clock B2 SDA I/O I2C data C5 DP I/O Common I/O port B5 DM I/O Common I/O port D5 ID I/O Common I/O port A1 INTB O Processor interrupt signal when peripheral is plugged/unplugged. Push-pull output A3 ISET O Fast-mode charger output. Open-drain output E4 JIG O GPIO factory output. Open-drain output E3 BOOT O GPIO factory output. Push-pull output Copyright © 2011, Texas Instruments Incorporated 3 TSU6712 SCDS321 – MAY 2011 ABSOLUTE MAXIMUM RATINGS (1) www.ti.com (2) over operating free-air temperature range (unless otherwise noted) MIN MAX VBUS Supply voltage from USB connector –0.5 28 VBAT Supply voltage from battery -0.5 6 VDDIO Logic supply voltage -0.5 4.6 VAUDIO VMICIO VVIDEOI Switch I/O voltage range Audio Switch -1.5 VBAT+0.5 Mic Switch -0.5 VBAT+0.5 Video Switch O VUSBIO VLOGIC_ USB Switch -1 VBAT+0.5 UNIT V V V -0.5 VBAT+0.5 Voltage applied to logic output -0.5 VBAT+0.5 V IBUS Peak input current on VBUS pin 2 A IOUT Peak output current on OUT pin 2 A IK Analog port diode current -50 50 mA ISW-DC ON-state continuous switch current -60 60 ISW- ON-state peak switch current -150 150 mA -50 mA 50 mA 100 mA 150 °C O PEAK IIK Digital logic input clamp current VL < 0 ILOGIC_O Continuous current through logic output IGND Continuous current through GND Tstg Storage temperature range (1) (2) -50 –65 Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum. THERMAL IMPEDANCE RATINGS UNIT θJA 4 Package thermal impedance YFP package 98.8 °C/W Copyright © 2011, Texas Instruments Incorporated TSU6712 SCDS321 – MAY 2011 www.ti.com DIGITAL SIGNALS – I2C INTERFACE AND GPIO over operating free-air temperature range (unless otherwise noted) TEST CONDITIONS MIN MAX UNIT VDDIO Logic and I/O supply voltage 1.65 3.6 V VIH High-level input voltage VDDIO × 0.7 VDDIO V VIL Low-level input voltage 0 VDDIO × 0.3 V VOH High-level output voltage IOH = -3 mA VOL Low-level output voltage IOL = 3 mA fSCL SCL frequency VDDIO × 0.7 V 0 0.4 V 400 kHz UART BUFFER over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT 1.15 VDDIO V From Phone Transmitter to Accessory VIH High-level input voltage (TxD) VDDIO = 2.8 V VIL Low-level input voltage (TxD) VDDIO = 2.8 V VOH High-level output voltage (DP, DM) IOH = –4 mA , VBAT = 3.0 V VOL Low-level output voltage (DP, DM) IOL = 4 mA , VBAT = 3.0 V 0 0.49 V 2.4 VBAT V 0 0.55 V From Accessory to Phone Receiver VIH High-level input voltage (DP, DM) VBAT = 3.0 V 2.0 VBAT V VIL Low-level input voltage (DP, DM) VBAT = 3.0 V 0 0.8 V VOH High-level output voltage (RxD) IOH = –4 mA , VDDIO = 2.8 V 1.16 VDDIO V VOL Low-level output voltage (RxD) IOL = 4 mA , VDDIO = 2.8 V 0 0.33 V MIN MAX UNIT JIG AND ISET FAST-MODE CHARGER OUTPUT (OPEN-DRAIN OUTPUT) over operating free-air temperature range (unless otherwise noted) PARAMETER VOL Low-level output voltage TEST CONDITIONS IOL = 10 mA, VBAT = 3.0 V 0.5 V INTB AND BOOT (PUSH-PULL OUTPUT) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VOH High-level output voltage IOH = –4 mA , VDDIO = 2.8 V VOL Low-level output voltage IOL = 4 mA , VDDIO = 2.8 V Copyright © 2011, Texas Instruments Incorporated MIN MAX UNIT 2.2 VDDIO V 0 0.33 V 5 TSU6712 SCDS321 – MAY 2011 www.ti.com OVP ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT In Undervoltage lockout, input power detected threshold rising VUVLO+ VBUS increasing from 0V to 5V, No load on OUT pin 2.65 2.8 3 V Undervoltage lockout, input power detected threshold falling VUVLO– VBUS decreasing from 5V to 0V, No load on OUT pin 2.25 2.44 2.7 V Δ of VUVLO+ and VUVLO– 150 260 550 mV 120 200 mΩ Hysteresis on UVLO VHYS-UVLO Input to Output Characteristics VBUS switch resistance RDS-VBUSSWITCH VBUS = 5 V, IOUT = 100 mA Turn-ON time tON RL = 36 Ω, CL = 400 pF 16 ms Turn-OFF time tOFF RL = 36 Ω, CL = 400 pF 50 μs VOVP VBUS increasing from 6 V to 8 V 6.8 VBUS decreasing from 8 V to 6 V 25 Input Overvoltage Protection (OVP) Input overvoltage protection threshold VBUS Maximum OV delay VBUS tPD(OVP) Hysteresis on OVP VBUS VHYS-UVLO Recovery time from input overvoltage condition VBUS tON(OVP) Time measured from VBUS 8 V ≥ 6 V, 1-μs fall-time 7 7.2 V 0.25 1 µs 100 300 mV 8 ms TOTAL SWITCH CURRENT CONSUMPTION over operating free-air temperature range (unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT VBAT Standby Current Consumption IBAT(Standby) VBUS = 0 V 30 µA VBAT Operating Current Consumption IBAT(Operating) VBUS = 0 V 150 µA VBUS Operating Current Consumption IVBUS 600 µA 6 No load on OUT pin, VBUS = 5 V 150 Copyright © 2011, Texas Instruments Incorporated TSU6712 SCDS321 – MAY 2011 www.ti.com AUDIO SWITCH ELECTRICAL CHARACTERISTICS (1) VBAT = 3 V to 4.4 V, VDDIO = 2.8 V, TA = –40°C to 85°C (unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Analog Switch Analog signal range –0.8 VAUDIO 0.8 V 2 5.5 Ω VI = 0.8 V, II = –20mA, VBAT = 3.0 V 0.05 0.5 Ω rON(flat) VI = ±0.8 V, IO = –20 mA, VBAT = 3.0 V 0.05 0.2 Ω VI or VO OFF leakage current IIO(OFF) (VI = 0 V, VO = 0.8 V) or (VI = 0.8 V, VO = –0.8 V), VBAT = 4.4 V, Switch OFF 200 500 nA VO ON leakage current IIO(ON) VI = OPEN, VO = –0.8 V or 0.8 V, VBAT = 4.4 V, Switch ON 10 300 nA ON-state resistance S_L or S_R , DM or DP rON ON-state resistance match between channels S_L or S_R , DM or DP ΔrON ON-state resistance flatness S_L or S_R , DM or DP VI = ±0.8 V, IO = –20 mA, VBAT = 3.F0 V Dynamic Turn-ON time From receipt of I2C stop bit tON VI or VO = VBAT, RL = 50 Ω, CL = 35 pF 120 µs Turn-OFF time From receipt of I2C stop bit tOFF VI or VO = VBAT, RL = 50 Ω, CL = 35 pF 4.5 µs VI OFF capacitance CI(OFF) DC bias = 0 V or 1.6 V, f = 10 MHz, Switch OFF 5.5 pF VO OFF capacitance CO(OFF) DC bias = 0 V or 1.6 V, f = 10 MHz, Switch OFF 10 pF VI, VO ON capacitance CI(ON), CO(ON) DC bias = 0 V or 1.6 V f = 10 MHz, Switch ON 13 pF BW RL = 50 Ω, Switch ON 450 MHz OFF Isolation OISO f = 20 kHz, RL = 50 Ω, Switch OFF –100 dB Crosstalk XTALK f = 20 kHz, RL = 50 Ω –85 dB THD RL = 16 Ω, CL = 20 pF, f = 20 Hz to 20 kHz, 1.6-Vpp output 0.05 % Bandwidth Total harmonic distortion (1) VI is equal to the asserted voltage on S_R and S_L pins. VO is equal to the asserted voltage on DP and DM pins. II is equal to the current on the S_R and S_L pins. IO is equal to the current on the DP and DM pins. Copyright © 2011, Texas Instruments Incorporated 7 TSU6712 SCDS321 – MAY 2011 www.ti.com MIC SWITCH ELECTRICAL CHARACTERISTICS (1) VBAT = 3 V to 4.4 V, VDDIO = 2.8 V, TA = –40°C to 85°C (unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Analog Switch Analog signal range ON-state resistance VMICIO MIC, VBUS rON 0 VI = 2.3 V, IO = –2 mA, VBAT = 3 V 2.3 V 40 70 Ω 5 500 nA VI or VO OFF leakage current IIO(OFF) VI = 0.3 V, VO = 2.3 V or VI = 2.3 V, VO = 0.3 V, VBAT = 4.4 V, Switch OFF MIC pulldown resistance RPD (ON) VI = OPEN, VO = 1.35 V, VBAT = 4.4 V, Switch ON 1.5 kΩ Dynamic Turn-ON time From receipt of I2C ACK bit tON VI or VO = VBAT, RL = 50 Ω, CL = 35 pF 120 µs Turn-OFF time From receipt of I2C ACK bit tOFF VI or VO = VBAT, RL = 50 Ω, CL = 35 pF 11 µs VI OFF capacitance CI(OFF) DC bias = 0 V or 3.6 V, f = 10 MHz, Switch OFF 140 pF VO OFF capacitance CO(OFF) DC bias = 0 V or 3.6 V, f = 10 MHz, Switch OFF 10.5 pF VI, VO ON capacitance CI(ON), CO(ON) DC bias = 0 V or 3.6 V, f = 10 MHz, Switch ON 140 pF Bandwidth BW RL = 50 Ω, Switch ON 40 MHz OFF Isolation OISO f = 20 kHz, RL = 50 Ω, Switch OFF –95 dB Crosstalk XTALK f = 20 kHz, RL = 50 Ω, to audio output –85 dB THD RL = 600 Ω, CL = 20 pF, f = 20 Hz–20 kHz , Vin=0.1 Vpp centered at VBAT/2 0.46 Total harmonic distortion (1) 8 0.65 % VI is equal to the asserted voltage on VBUS pin. VO is equal to the asserted voltage on MIC pin. II is equal to the current on the VBUS pin. IO is equal to the current on the MIC pin. Copyright © 2011, Texas Instruments Incorporated TSU6712 SCDS321 – MAY 2011 www.ti.com VIDEO SWITCH ELECTRICAL CHARACTERISTICS (1) VBAT = 3.0 V to 4.4 V, VDDIO = 2.8 V, TA = –40°C to 85°C (unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Analog Switch Analog signal range –0.5 VVIDEOIO ON-state resistance V_L, V_R, or VIDEO DM, DP, or ID ON-state resistance match between channels V_L, V_R DM, DP ΔrON ON-state resistance flatness V_L, V_R DM, DP 2 V VI = 0.5 V to 2 V, IO = –20 mA, VBAT = 3.0 V 12 18 Ω VI = 1.0 V, II = –2.0 mA, VBAT = 3.0 V 0.5 2 Ω rON(flat) VI = 0.5 V to 2.0 V, IO = –20 mA, VBAT = 3.0 V 0.5 2 Ω VI or VO OFF leakage current IIO(OFF) VI = 0.3 V, VO = 2.0 V or VI = 2 V, VO = 0.3 V, VBAT = 4.4 V, Switch OFF 60 360 nA VO ON leakage current IIO(ON) VI = OPEN, VO = 0.3 V or 2.0 V, VBAT = 4.4 V, Switch ON 60 360 nA rON Dynamic Turn-ON time From receipt of I2C ACK bit tON VI or VO = VBAT, RL = 50 Ω, CL = 35 pF 70 µs Turn-OFF time From receipt of I2C ACK bit tOFF VI or VO = VBAT, RL = 50 Ω, CL = 35 pF 26 µs VI OFF capacitance CI(OFF) DC bias = 0 V or 3.6 V, f = 10 MHz, Switch OFF 3 pF VO OFF capacitance CO(OFF) DC bias = 0 V or 3.6 V, f = 10 MHz, Switch OFF 10 pF VI, VO ON capacitance CI(ON), CO(ON) DC bias = 0 V or 3.6 V, f = 10 MHz, Switch ON 12 pF BW RL = 50 Ω, Switch ON 450 MHz OFF Isolation OISO f = 10 MHz, RL(VIDEO) = 50 Ω, Switch OFF –58 dB Crosstalk XTALK f = 10 MHz, RL(VIDEO) = 50 Ω, Switch ON –60 dB THD RL = 600 Ω, CL = 20 pF, f = 20 Hz~20 kHz , 2.3Vpp output 0.05 % Bandwidth Total harmonic distortion (1) V_L or V_R VO is equal to the asserted voltage on DP, DM, and ID pins. VI is equal to the asserted voltage on D+, D–, and IDBP pins. IO is equal to the current on the DP, DM, and ID pins. II is equal to the current on the D+, D–, and IDBP pins. Copyright © 2011, Texas Instruments Incorporated 9 TSU6712 SCDS321 – MAY 2011 www.ti.com USB SWITCH ELECTRICAL CHARACTERISTICS (1) VBAT = 3 V to 4.4 V, VDDIO = 2.8 V, TA = –40°C to 85°C (unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT VBAT V 8 15 Ω VI = 0.4 V, IO = –2 mA, VBAT = 3 V 0.5 1 Ω Analog Switch Analog signal range VUSBIO 0 ON-state resistance D–, D+, or IDBP DM, DP, or ID ON-state resistance match between channels D–, D+ DM, DP ΔrON ON-state resistance flatness D–, D+ DM, DP rON(flat) VI = 0 V to 3.6 V, IO = –2 mA, VBAT = 3 V 0.5 1 Ω VI or VO OFF leakage current IIO(OFF) VI = 0.3 V, VO = 2.7 V or VI = 2.7 V, VO = 0.3 V, VBAT = 4.4 V, Switch OFF 45 360 nA VO ON leakage current IIO(ON) VI = OPEN, VO = 0.3 V or 2.7 V, VBAT = 4.4 V, Switch ON 50 360 nA rON VI = 0 V to 3.6 V, IO = –2 mA, VBAT = 3 V Dynamic Turn-ON time From receipt of I2C ACK bit tON VI or VO = VBAT, RL = 50 Ω, CL = 35 pF 95 µs Turn-OFF time From receipt of I2C ACK bit tOFF VI or VO = VBAT, RL = 50 Ω, CL = 35 pF 25 µs VI OFF capacitance CI(OFF) DC bias = 0 V or 3.6 V, f = 10 MHz, Switch OFF 3 pF VO OFF capacitance CO(OFF) DC bias = 0 V or 3.6 V, f = 10 MHz, Switch OFF 10 pF VI, VO ON capacitance CI(ON), CO(ON) DC bias = 0 V or 3.6 V, f = 10 MHz, Switch ON 11 pF Bandwidth BW RL = 50 Ω, Switch ON 510 MHz OFF Isolation OISO f = 240 MHz, RL = 50 Ω, Switch OFF –24 dB Crosstalk XTALK f = 240 MHz, RL = 50 Ω –40 dB (1) 10 VO is equal to the asserted voltage on DP, DM, and ID pins. VI is equal to the asserted voltage on D+, D–, and IDBP pins. IO is equal to the current on the DP, DM, and ID pins. II is equal to the current on the D+, D–, and IDBP pins. Copyright © 2011, Texas Instruments Incorporated TSU6712 SCDS321 – MAY 2011 www.ti.com GENERAL OPERATION The TSU6712 will automatically detect accessories plugged into the phone via the mini USB 5 pin connector. The type of accessory detected will be stored in I2C registers within the TSU6712 for retrieval by the host. The TSU6712 has a network of switches that can be automatically opened and closed base on the accessory detection. See Table 1 for details of which switches are open during each mode of operation. For flexibility, the TSU6712 also offers a manual switching mode allowing the host processor to decide which switches should be opened and closed and execute the settings through the I2C interface. Standby Mode Standby mode is the default mode upon power up and occurs when no accessory has been detected. During this mode, the VBUS and ID lines are continually monitored through comparators to determine when an accessory is inserted. Power consumption is minimal during standby mode. Accessory ID Detection If VBUS is high and the attachment is not a carkit or charger, then determine the impedance on the ID pin. If VBUS is low and an accessory is attached, then use an ADC for impedance sensing on the ID pin to identify which accessory is attached and/or what kind of remote control key button is pushed. Impedance Buckets for Each Accessory and Remote Control Key Button In order to implement ID detection, each accessory and remote control key button of audio accessory should contain below ID impedance resistor value which is 1% tolerance accuracy. OVP OPERATION The device continuously monitors the input voltage and the input current as described in detail in the following sections. Input Overvoltage Protection When the input voltage rises above VOVP, the internal VBUS switch is turned off, removing power from the circuit. The response is very rapid, with the FET switch turning off in less than 1 µs. The OVP_EN interrupt bit is set high when an overvoltage condition is detected. When the input voltage returns below VOVP – VHYS-OVP and remains above VUVLO, the VBUS FET switch is turned on again after a deglitch time of tON(OVP). The deglitch time ensures that the input supply has stabilized before turning the switch on. When the OVP condition is cleared, the OVP_OCP_DIS interrupt bit is set high. OVP Glitch Immunity When VBUS is near the OVP threshold, noise on VBUS cause spurious OVP triggering. To avoid this, OVP glitch immunity allows noise on the VBUS line to be rejected. The glitch protection circuitry integrates the glitch over time allowing the OVP circuitry to trigger faster for larger voltage excursions above the OVP threshold and slower for shorter excursions. The protection circuitry has a maximum OV delay of 1 µs Copyright © 2011, Texas Instruments Incorporated 11 TSU6712 SCDS321 – MAY 2011 www.ti.com AV Cable Detection Once an A/V cable is attached with 365 kΩ ID resistance and/or 75 Ω load resistance, the ID voltage will drop below the internal comparator reference level of the TSU6712 and the ADC block of the TSU6712 will determine the ID line impedance value. The ID detect signal that is sent to the logic control block will be set equal to an A/V cable accessory. With the video driver in the phone enabled, detection block of the TSU6712 will sense that the 75ohm load resistance at the end of the A/V cable is still attached since the video sync pulse will always be present. Power-On Reset When power (from 0 V) is applied to VBAT, an internal power-on reset holds the TSU6712 in a reset condition until VBAT has reached VPOR. At that point, the reset condition is released, and the TSU6712 registers and I2C state machine initialize to their default states. After the initial power-up phase, VBAT must be lowered to below 0.2 V and then back up to the operating voltage (VDDIO) for a power-reset cycle. Software Reset The TSU6712 has software reset feature. Hold low both SCL and SDA more than 30ms will reset digital logic of the TSU6712. After resetting, INTB will keep low until INT_Mask bit of Control register (0x02) is cleared. Key Press Identification Key Key Press Timing Long Key Press Timing INTB Key Press Interrupt Long Key Press Interrupt Long Key Release Interrupt (A) (B) (C) A. Key press B. Released key press → Set KP Interrupt → Set error bit in Button register → INTB pulled low C. I2C read of INT register → Clear KP interrupt → INTB goes back high Figure 1. Short Key Press 12 Copyright © 2011, Texas Instruments Incorporated TSU6712 SCDS321 – MAY 2011 www.ti.com Key Key Press Timing Long Key Press Timing INTB Key Press Interrupt Long Key Press Interrupt Long Key Release Interrupt (A) (B) (C) A. Key press B. Released key press → Set KP Interrupt → Set Key (S/E, 1–12) bit in Button register → INTB pullled low C. I2C read of INT register → Clear KP interrupt → INTB goes back high Figure 2. Normal Key Press Key Key Press Timing Long Key Press Timing INTB Key Press Interrupt Long Key Press Interrupt Long Key Release Interrupt (A) (B) (C) (D) (E) A. Key press B. Long key press timing reached → Set LKP interrupt bit → Set Key (S/E, 1–12) bit in Button register → INTB pullled low C. I2C read of INT register → Clear LKP interrupt bit → INTB goes back high D. Released key press → Set LKR Interrupt bit → INTB pullled low E. I2C read of INT register → Clear LKR interrupt bit→ INTB goes back high Figure 3. Long Key Press Copyright © 2011, Texas Instruments Incorporated 13 TSU6712 SCDS321 – MAY 2011 www.ti.com Key Key Press Timing Long Key Press Timing INTB Key Press Interrupt Stuck Key Press Interrupt Stuck Key Release Interrupt (A) (B) (C) (D) (E) A. Key press detected when accessory attached B. Long key press timing reached → Set SK interrupt bit → Set Key (S/E, 1–12) bit in Button register → INTB pullled low C. I2C read of INT register → Clear SK interrupt bit → INTB goes back high D. Released key press detected when accessory ID resistor is 1 MΩ → Set SKR Interrupt bit → INTB pullled low E. I2C read of INT register → Clear SKR interrupt bit→ INTB goes back high Figure 4. Stuck Key Press RSend_End Send_End R1 S1 R2 S2 R3 S3 R4 S4 R5 S5 R6 S6 R7 S7 R8 S8 R9 S9 R10 S10 R11 S11 R12 S12 RID Hold Figure 5. Audio / Remote Controller Accessory 14 Copyright © 2011, Texas Instruments Incorporated TSU6712 SCDS321 – MAY 2011 www.ti.com Table 2. Accessory Detection Scheme 1% ID Resistor Tolerance (Resistor Values and Part Numbers) ACCCESSORY ID RESISTOR VALUE ON ACCESSORY DETECTED IMPEDANCE ON TSU6712 ADC VALUE OTG – – 00000 Send_End Button 2K 2K 00001 Stereo Headset with RC S1 Button 0.604K 2.604K 00010 Stereo Headset with RC S2 Button 0.604K 3.208K 00011 Stereo Headset with RC S3 Button 0.806K 4.014K 00100 Stereo Headset with RC S4 Button 0.806K 4.82K 00101 Stereo Headset with RC S5 Button 1.21K 6.03K 00110 Stereo Headset with RC S6 Button 2K 8.03K 00111 Stereo Headset with RC S7 Button 2K 10.03K 01000 Stereo Headset with RC S8 Button 2K 12.03K 01001 Stereo Headset with RC S9 Button 2.43K 14.46K 01010 Stereo Headset with RC S10 Button 2.8K 17.26K 01011 Stereo Headset with RC S11 Button 3.24K 20.5K 01100 Stereo Headset with RC S12 Button 3.57K 24.07K 01101 Audio Device Type 3 28.7K 28.7K 01110 Reserved Accessory #2 34K 34K 01111 Reserved Accessory #4 49.9K 49.9K 10001 Reserved Accessory #5 64.9K 64.9K 10010 Audio Device Type 2 56.2K 80.27K 10011 Phone Powered Device 102K 102K 10100 TTY Converter 121K 121K 10101 UART Cable 150K 150K 10110 Type 1 Charger 200K 200K 10111 Factory Mode Cable –Boot Off USB 255K 255K 11000 Factory Mode Cable –Boot On USB 301K 301K 11001 Audio/Video Cable 365K 365K 11010 Type 2 Charger 442K 442K 11011 Factory Mode Cable – Boot Off UART 523K 523K 11100 Factory Mode Cable – Boot On UART 619K 619K 11101 Stereo Headset with Remote Controller 976K 1000.07K 11110 Mono/Stereo Headset 1000K 1002K 11110 No Device – – 11111 Carkit Interface of TSU6712 TSU6712 is designed to support Carkit interface, which is defined in the CEA-936A Carkit Specification. But, in the Carkit mode, TSU6712 would be compliant with 4-wire Carkit protocol defined in the CEA-936A Carkit Specification and UART data interface. In case of UART data interface in the Carkit mode, TSU6712 opens the signal path and allows the UART transceiver in the phone to communicate with Carkit. To support data during audio (DDA) mode, TSU6712 integrates UART driver and audio amplifier to generate DDA signal. UART and audio signaling follow the protocol defined in the CEA-936A Carkit Specification. Copyright © 2011, Texas Instruments Incorporated 15 TSU6712 SCDS321 – MAY 2011 Phone www.ti.com USB Mode UART Mode Mono Mode Stereo Mode VBUS VBUS VBUS VBUS Carkit or Car Stereo (CEA-936-A) VBUS Phone Processor 5 V Regulators SW D– D– TxD SPKR SPKR_L D– USB Controller D+ D+ RxD MIC SPKR_R D+ UART Audio Codec TxD RxD SHUD SHLD CMR CMR MIC GND GND GND GND USB Cable 12 V Spkr Drvr GND Audio L Audio_L Spkr Drvr SHLD STS DM_CON CTL USB Carkit Amplifier SPKR_L SPKR_R UART Tx Driver TxD Carkit State Machine CTL Carkit Comparator Car Stereo Processor INTERFACE ARCHITECTURE Five different signaling Modes: • UART • Audio mono • Audio stereo • Data during audio (DDA) - mono • Data during audio (DDA) - stereo Main sub-blocks • UART Tx driver • UART Rx driver • Carkit comparator • Audio input amplifier (MIC) • Two audio output amplifiers Mic In Audio_R DP_CON Audio_R UART Rx Driver RxD CARKIT INTERFACE ACHITECTURE Figure 6. Carkit Interface Architecture Carkit Status Register Bit Descriptions I2C Carkit Status Register Three Carkit mode bits –'000' = Open all paths for Carkit except Load switch –'001' = UART mode –'010' = Mono mode When the phone receives an interrupt from the Carkit, as described in 7.3.4 of CEA-936-A, the Mode bits will automatically switch to ‘001’ –'011' = Stereo mode When the phone receives an interrupt from the Carkit, as described in 7.3.6 of CEA-936-A, the Mode bits will automatically switch to ‘001’ –'100' = DDA Mono mode –'101' = DDA Stereo mode When the phone receives an interrupt from the Carkit, as described in 7.3.7 of CEA-936-A, the Mode bits will automatically switch to ‘100’ 16 UART_TRAFFI C – When high, allows UART data traffic if Carkit Mode set to ‘001’, ‘100’. DISC_Request – When high, causes jump to Standby state Copyright © 2011, Texas Instruments Incorporated TSU6712 SCDS321 – MAY 2011 www.ti.com All bits are cleared by reading the Carkit Interrupt register PH_INIT This bit is set on the rising edge of the state machine clock signal causes the transition to the ph_init state. It tells the host that a charger was not detected and that we will now test for a USB device or a Carkit. PH_UART This bit is set high on the rising edge of the state machine clock that causes transition to this state regardless of the previous state -(13), (17), (21), (25), or (28). If the transition is because the host wrote '000' to the Carkit Mode bits, the state transition still waits for the state machine clock. Thus, though the host has told the Carkit to go to the ph_uart state, the state transition has not happened until the host sees the PH_UART interrupt. When one of the three Carkit interrupts occur, as in 19, 23, or 30 on the State Flow Chart, this automatically resets the Carkit Mode bits of '000' for 19 and 23 or '011' for 30. Then on the next rising edge of the state machine clock, the state transition occurs. PH_AUD_STER O PH_DDA_mono These bits are set high on the rising edge of the state clock that causes the PH_Aud_Steere transition from the ph_uart state to any of the four ph_aud states. o PH_Aud_Mono PH_DISC Set high when phone enters Standby state. A typical use for this state is when the user would like to have a private call and suspend Carkit operation. CR_UART Set high when DP pulled below VCR_PLS_NEG (0.3 V) for time of TCR_PLS_NEG (200 to 600nS) while in ph_uart state. Used to indicate to phone that button on Carkit has been pushed when UART traffic has not been enabled.(7.3.2) CR_MONO Set high when DP pulled below VCR_PLS_NEG (0.3 V) for time of TCR_PLS_NEG (200 to 600nS) PH_AUD Mono state. Used to indicate to phone that button on Carkit has been pus when DDA is disabled. (7.3.4) CR_STEREO Set high when DP pulled below VCR_PLS_NEG (0.3 V) for time of TCR_PLS_NEG (200 to 600nS) while in ph_aud -Stereo state. Used to indicate to phone that button on Carkit has been pushed when DDA is disabled. (7.3.6) CR_DDA_Stere o (CEA 7.3.7) Set high by a low pulse of at least 30mS on DP while in the ph_aud ¬Stereo/DDA state (28) (DDA from phone to Carkit enabled, but DDA from Carkit to phone not enabled). This low pulse also resets the Carkit Mode bits to '011'. Then, on the next 1KHz clock transition, jumps to the ph_aud -Mono/DDA state (25) to enable DDA from Carkit to phone. This will not set the PH_UART interrupt. Copyright © 2011, Texas Instruments Incorporated 17 TSU6712 SCDS321 – MAY 2011 www.ti.com TSU6712 Carkit Interface Data Mode UART Tx TxD DM_CON Audio L Audio_L Carkit State Machine MIC Carkit Comparator Mic In Audio_R DP_CON Audio_R RxD UART Rx TxD on TSU6712 connects phone UART transceiver to Carkit through DM line. RxD on TSU6712 connects phone UART transceiver to Carkit through DP line. TSU6712 cannot detect a Carkit interrupt with the CR_INT_REQ command after UART traffic is enabled – this is handled by the phone UART transceiver. Figure 7. TSU6712 Carkit Interface – UART Mode 18 Copyright © 2011, Texas Instruments Incorporated TSU6712 SCDS321 – MAY 2011 www.ti.com Audio Mode (Mono) UART Tx TxD DM_CON Audio L Audio_L Carkit State Machine MIC Carkit Comparator Mic In Audio_R DP_CON Audio_R UART Rx RxD S_L amplifier drives the phone audio codec signal to the Carkit left speaker through DM line. S_R amplifier is turned off. MIC input amplifier drives the Carkit microphone signal on DP line back to the audio codec. TSU6712 cannot issue a GET_STATUS command to the Carkit after a Carkit Mono to UART transition has been detected – this is handled by the phone UART transceiver. Figure 8. TSU6712 Carkit Interface – Audio Mono Mode Copyright © 2011, Texas Instruments Incorporated 19 TSU6712 SCDS321 – MAY 2011 www.ti.com Audio Mode (Stereo) UART Tx TxD DM_CON Audio L Audio_L Carkit State Machine MIC Carkit Comparator Mic In Audio_R DP_CON Audio_R UART Rx RxD S_L amplifier drives the phone audio codec signal to the Carkit left speaker through DM line. S_R amplifier drives the phone audio codec signal to the Carkit right speaker through DP line. MIC input amplifier is turned off. TSU6712 cannot issue a GET_STATUS command to the Carkit after a Carkit Stereo to UART transition has been detected – this is handled by the phone UART transceiver. Figure 9. TSU6712 Carkit Interface – Audio Stereo Mode 20 Copyright © 2011, Texas Instruments Incorporated TSU6712 SCDS321 – MAY 2011 www.ti.com DDA Mode (Phone to Carkit) UART Tx TxD DM_CON Audio L Audio_L Carkit State Machine MIC Carkit Comparator Mic In Audio_R DP_CON Audio_R RxD UART Rx MIC input amplifier is enabled for Mono mode and S_R amplifier is enabled for Stereo mode to connect the phone audio codec and Carkit through the DP line. S_L amplifier is enabled to connect the phone audio codec and Carkit through the DP line while there is no data activity on the UART TXD pin. After detecting a data transition on TXD, the Carkit state machine will disable the S_L amplifier and then enable the UART TXD output driver in order to send a positive data pulse followed by a negative data pulse on the DM line. After the data pulses have been sent, the UART TXD output driver will be disabled and then the S_L amplifier will be turned back on . Figure 10. TSU6712 Carkit Interface – DDA Mode (Phone to Carkit) Copyright © 2011, Texas Instruments Incorporated 21 TSU6712 SCDS321 – MAY 2011 www.ti.com DDA Mode (Carkit to Phone) UART Tx DM_CON TxD Audio L Audio_L Carkit State Machine MIC Carkit Comparator Mic In Audio_R DP_CON Audio_R RxD UART Rx The Car Kit can only send data during audio if it is operating in the Mono mode. S_L amplifier is enabled to connect the phone audio codec and Car Kit through the DM line. MIC input amplifier is enabled for Mono mode and S_R amplifier is disabled to connect the phone audio codec and Car Kit through the DP line. Car Kit comparator will detect when a negative pulse is sent to the phone from the Car Kit. After the Car Kit comparator detects a negative pulse, TSU6712 will toggle an internal flip-flop in order to recover the RXD signal that will be driven out to the RXD line by the UART RXD driver. Figure 11. TSU6712 Car Kit Interface – DDA Mode (Car Kit to Phone) 22 Copyright © 2011, Texas Instruments Incorporated TSU6712 SCDS321 – MAY 2011 www.ti.com Standard I2C Interface Details The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be connected to a positive supply via a pullup resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. I2C communication with this device is initiated by the master sending a START condition, a high-to-low transition on the SDA input/output while the SCL input is high (see Figure 12). After the start condition, the device address byte is sent, MSB first, including the data direction bit (R/W). This device does not respond to the general call address. After receiving the valid address byte, this device responds with an ACK, a low on the SDA input/output during the high of the ACK-related clock pulse. SDA SCL S P Stop Condition Start Condition Figure 12. Definition of START and STOP Conditions The data byte follows the address ACK. The R/W bit is kept low for transfer from the master to the slave. The data byte is followed by an ACK sent from this device. Data are output only if complete bytes are received and acknowledged. The output data is valid at time (tpv) after the low-to-high transition of SCL, during the clock cycle for the ACK. On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control commands (START or STOP) (see Figure 13). SDA SCL Data Line Change Figure 13. Bit Transfer A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the master (see Figure 12). The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the receiver can send an ACK bit. A slave receiver that is addressed must generate an ACK after the reception of each byte. The device that acknowledges has to pull down the SDA line during the ACK clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (see Figure 14). Setup and hold times must be taken into account. Copyright © 2011, Texas Instruments Incorporated 23 TSU6712 SCDS321 – MAY 2011 www.ti.com Data Output by Transmitter NACK Data Output by Receiver ACK SCL From Master 1 2 8 9 S Clock Pulse for Acknowledgment Start Condition Figure 14. Acknowledgment on I2C Bus Writes Data is transmitted to the TSU6712 by sending the device slave address and setting the LSB to a logic 0 (see Figure 15 for device address). The command byte is sent after the address and determines which register receives the data that follows the command byte. The next byte is written to the specified register on the rising edge of the ACK clock pulse. SCL 1 2 3 4 5 6 7 8 9 Slave Address Command Byte MSB SDA S Data to Register LSB 0 1 0 0 0 1 Start Condition 1 0 R/W A 0 0 0 0 0 0 Data 1 1/0 A ACK From Slave ACK From Slave A P ACK From Slave Figure 15. Write to Register Reads The bus master first must send the TSU6712 slave address with the LSB set to a logic 0. The command byte is sent after the address and determines which register is accessed. After a restart, the device slave address is sent again but, this time, the LSB is set to a logic 1. Data from the register defined by the command byte then is sent by the TSU6712. Data is clocked into the SDA output shift register on the rising edge of the ACK clock pulse. See Figure 16. ACK From Slave Slave Address MSB S 0 ACK From Slave NACK From ACK From Slave Data from Register Master Slave Address LSB 1 0 0 1 0 1 0 R/W A Command Byte A S 0 1 0 0 1 0 At this moment, master-transmitter becomes master-receiver, and slave-receiver becomes slave transmitter 1 1 A R/W Data NA P First byte Figure 16. Read From Register 24 Copyright © 2011, Texas Instruments Incorporated TSU6712 SCDS321 – MAY 2011 www.ti.com Clear INT Registers Upon Read The TSU6712 I2C logic core is set to clear all INT bits in a register after that register is read by the host. When the acknowledge is received from the Master after the INT register has been read, the contents of the register is reset to the default state. I2C Timing SCL Slave Address SDA ST 0 1 0 0 Start 1 0 Sub Address 1 0 A 0 0 0 0 0 0 Date Byte 1 0 A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A SP ACK From Slave W/R Register Address (Control Reg) ACK From Slave Auto-Inc. Date Byte ACK From Slave Data to Control Register Data to Control Register ACK Stop From Slave Figure 17. Repeated Data Write to a Single Register Slave Address SDA ST 0 1 0 0 Start 1 0 Sub Address 1 0 A 1 0 0 0 1 0 Date Byte 0 0 Date Byte A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A ACK Data to Timing Set 1 From Register Slave W/R Register Address (Timing Set 1 Reg) ACK From Slave Auto-Inc. ACK From Slave Data to Timing Set 2 Register ACK From Slave Figure 18. Burst Data Write to Multiple Registers Slave Address SDA ST 0 1 0 0 1 0 Sub Address 1 0 A 0 0 0 0 0 0 Slave Address 1 1 Register Address W/R (Interrupt 1 Reg) ACK From Slave Auto-Inc. Start A RS 0 1 0 1 0 1 1 A D7 D6 D5 D4 D3 D2 D1 D0 Data from Interrupt 1 Reg. W/R ACK From Slave ACK Re-Start From Slave Date Byte Date Byte continued 0 Date Byte A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 NA SP Data from Interrupt 1 Reg. ACK From Master Data from Interrupt 1 Reg. Stop No ACK From Master (Message Ends) ACK From Master Figure 19. Repeated Data Read from a Single Register – Combined Mode SCL Slave Address SDA ST 0 Start 1 0 0 1 0 Sub Address 1 0 A 1 0 0 0 0 0 Slave Address 1 1 Register Address W/R (Interrupt 1 Reg) ACK From Slave Auto-Inc. A RS 0 0 0 ACK Re-Start From Slave Date Byte continued 1 1 0 Date Byte 1 1 A D7 D6 D5 D4 D3 D2 D1 D0 W/R ACK From Slave Data from Interrupt 1 Reg. Date Byte A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 NA SP Data from Interrupt 2 Reg. ACK From Master ACK From Master Data from Int Mask 1 Reg. Stop No ACK From Master (Message Ends) Figure 20. Burst Data Read from Multiple Registers – Combined Mode Copyright © 2011, Texas Instruments Incorporated 25 TSU6712 SCDS321 – MAY 2011 www.ti.com Slave Address SDA ST 0 1 0 0 Start 1 0 Sub Address 1 0 A 0 0 0 0 0 Slave Address 0 1 W/R Register Address (Interrupt 1 Reg) ACK From Slave Auto-Inc. 1 A SP ST 0 1 ACK Start From Stop Slave 0 0 1 0 Date Byte 1 1 A D7 D6 D5 D4 D3 D2 D1 D0 W/R ACK From Slave Data from Interrupt 1 Reg. Continued Date Byte Date Byte A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 NA SP continued Data from Interrupt 1 Reg. ACK From Master Data from Interrupt 1 Reg. Stop No ACK From Master (Message Ends) ACK From Master Figure 21. Repeated Data Read from a Single Register – Split Mode SCL Slave Address SDA ST 0 Start 1 0 0 1 0 Sub Address 1 0 A 1 0 0 0 0 0 Slave Address 1 1 A SP ST 0 W/R Register Address ACK Start (Interrupt 1 Reg) From Stop ACK From Slave Slave Auto-Inc. 1 0 1 0 1 1 A D7 D6 D5 D4 D3 D2 D1 D0 W/R ACK From Slave Data from Interrupt 1 Reg. Continued Date Byte Date Byte continued 0 Date Byte A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 NA SP Data from Interrupt 2 Reg. ACK From Master Data from Int Mask 1 Reg. ACK From Master Stop No ACK From Master (Message Ends) Figure 22. Burst Data Read from Multiple Registers – Split Mode 26 A. SDA is pulled low on ACK from slave or ACK from master. B. Register writes always require sub-address write before first data byte. C. Repeated data writes to a single register continue indefinitely until stop or restart. D. Repeated data reads from a single register continue indefinitely until no ACK from master. E. Burst data writes start at the specified register address, then advance to the next register address, even to the read-only registers. For these registers, data write appears to occur, though no data are changed by the writes. After register 14h is written, writing resumes to register 01h and continues until stop or restart. F. Burst data reads start at the specified register address, then advance to the next register address. Once register 14h is read, reading resumes from register 01h and continues until No ACK from master. Copyright © 2011, Texas Instruments Incorporated TSU6712 SCDS321 – MAY 2011 www.ti.com I2C Register Map (1) (2) (3) ADDR REGISTER TYPE RESET VALUE 01h Device ID R N/A 02h Control R/W xxx11111 03h Interrupt 1 R 00000000 (1) (2) (3) 04h Interrupt 2 R x0000000 05h Interrupt Mask 1 R/W 00000000 06h Interrupt Mask 2 R/W x0000000 BIT 7 BIT 6 BIT 5 BIT4 BIT 3 BIT 2 Version ID OVP_OCP_DIS OVP_OCP_DIS BIT1 Switch Open Raw Data Manual S/W Wait INT Mask OVP_EN LKR LKP KP Detach Attach OTP_EN CONNECT Stuck_Key_R CV Stuck_Key ADC_Change Reserved _Attach A/V_Charging OCP_EN OVP_EN LKR LKP KP Detach Attach OTP_EN CONNECT Stuck_Key _RCV Stuck_Key ADC_Change Reserved _Attach A/V_Charging OCP_EN 07h ADC R xxx11111 08h Timing Set 1 R/W 00000000 Key Press Device Wake Up 09h Timing Set 2 R/W 00000000 Switching Wait Long Key Press 0Ah Device Type 1 0Bh Device Type 2 R x0000000 Audio Type3 0Ch Button 1 R 00000000 7 6 5 4 0Dh Button 2 R x0000000 Unknown Error 12 0Eh CarKit Status R/W x0000000 DISC_Re quest UART_Traffi c 0Fh CarKit Int 1 R 00000000 PH_Disc PH_DDA_St ereo 10h Carkit Int 2 R xxxx0000 11h Carkit Int Mask 1 R/W 00000000 12h Carkit Int Mask 2 R/W xxxx0000 13h Manual S/W 1 R/W 00000000 14h Manual S/W 2 R/W xxx00000 R 00000000 BIT0 Vendor ID ADC Value USB OTG CR_UART CR_UART Dedicated CHG A/V PH_Disc USB Charger TTY PH_DDA_St ereo Car Kit UART USB Audio Type2 Audio Type1 PPD JIG_UART _OFF JIG_UART _ON JIG_USB _OFF JIG_USB_ON 3 2 1 Send_End 11 10 9 8 Mode PH_DDA_Mo no PH_DDA_Mo no D– Switching Type PH_Aud_Ster eo PH_Aud_Mon o PH_UART PH_Init CR_Error CR_DDA_Ste reo CR_Stereo CR_Mono PH_Aud_Ster eo PH_Aud_Mon o PH_UART PH_Init CR_Error CR_DDA_Ste reo CR_Stereo CR_Mono D+ Switching Charger DET BOOT_SW VBUS Switching JIG-ON ID Switching Do not use blank register bits. Write "0" to the blank register bits. Values read from the blank register bits are not defined and invalid. Table 3. Slave Address NAME SIZE(BITS) Slave address 8 Copyright © 2011, Texas Instruments Incorporated DESCRIPTION BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 1 0 0 1 0 1 R/W 27 TSU6712 SCDS321 – MAY 2011 www.ti.com Device ID Address: 01h Reset Value: N/A Type: Read BIT NO. NAME SIZE (BITS) 0-2 Version ID 4 A unique number for vendor 010b for Texas Instruments 4-7 Vendor ID 5 A unique number for chip version 01010b for TSU6712 DESCRIPTION Control Address: 02h Reset Value: xxx11111 Type: 28 Read/Write BIT NO. NAME SIZE (BITS) 0 INT Mask 1 0: Unmask interrupt 1: Mask interrupt 1 Wait 1 0: Wait until host re-sets this bit(WAIT bit) high 1: Wait until Switching timer is expired defined in Timing Set 1 2 Manual S/W 1 0: Manual Switching 1: Automatic Switching 3 RAW Data 1 0: Report the status changes on ID to Host 1: Don't report the status changes on ID 4 Switch Open 1 0: Open all Switches (Including load switch) 1: Automatic Switching by accessory status 5-7 Unused 3 DESCRIPTION Copyright © 2011, Texas Instruments Incorporated TSU6712 SCDS321 – MAY 2011 www.ti.com Interrupt 1 Address: 03h Reset Value: 00000000 Type: Read and Clear NAME SIZE (BITS) 0 Attach 1 1: Accessory is attached 1 Detach 1 1: Accessory is detached 2 KP 1 1: Key press 3 LKP 1 1: Long key press 4 LKR 1 1: Long key release 5 OVP_EN 1 1: OVP enabled 6 OCP_EN 1 1: OCP enabled 7 OVP_OCP_DIS 1 1: OVP_OCP disabled BIT NO. DESCRIPTION Interrupt 2 Address: 04h Reset Value: x0000000 Type: Read and Clear NAME SIZE (BITS) 0 A/V_Charging 1 1: Charger detected when A/V cable is attached 1 Reserved_Attach 1 1: Reserved Device is attached 2 ADC_Change 1 1: ADC value is changed when RAW data is enabled 3 Stuck_Key 1 1: Stuck Key is detected 4 Stuck_Key_RCV 1 1: Stuck Key is recovered 5 Connect 1 1: Switch is connected(closed) 6 OTP_EN 1 1: Over Temperature Protection enabled 7 Unused 1 BIT NO. Copyright © 2011, Texas Instruments Incorporated DESCRIPTION 29 TSU6712 SCDS321 – MAY 2011 www.ti.com Interrupt Mask 1 Address: 05h Reset Value: 00000000 Type: 30 Read and Clear BIT NO. NAME SIZE (BITS) 0 Attach 1 0: Unmask Attach Interrupt 1: Mask Attach Interrupt 1 Detach 1 1: Mask Detach Interrupt 0: Unmask Key press Interrupt 2 KP 1 0: Unmask Key press Interrupt 1: Mask Key press Interrupt 3 LKP 1 0: Unmask Long key press Interrupt 1: Mask Long key press Interrupt 4 LKR 1 0: Unmask Long key release Interrupt 1: Mask Long key release Interrupt 5 OVP_EN 1 0: Unmask OVP_EN Interrupt 1: Mask OVP_EN Interrupt 6 OCP_EN 1 0: Unmask OCP_EN Interrupt 1: Mask OCP_EN Interrupt 7 OVP_OCP_DIS 1 0: Unmask OVP_OCP_DIS Interrupt 1: Mask OVP_OCP_DIS Interrupt DESCRIPTION Copyright © 2011, Texas Instruments Incorporated TSU6712 SCDS321 – MAY 2011 www.ti.com Interrupt Mask 2 Address: 06h Reset Value: x0000000 Type: Read and Clear BIT NO. NAME SIZE (BITS) 0 A/V_Charging 1 0: Unmask A/V_Charging Interrupt 1: Mask A/V_Charging Interrupt 1 Reserved_Attach 1 0: Unmask Reserved_Attach Interrupt 1: Mask Reserved_Attach Interrupt 2 ADC_Change 1 0: Unmask ADC_Change Interrrupt 1: Mask ADC_Change Interrrupt 3 Stuck_Key 1 0: Unmask Stuck_Key Interrupt 1: Mask Stuck_Key Interrupt 4 Stuck_Key_RCV 1 0: Unmask Stuck_Key_RCV Interrupt 1: Mask Stuck_Key_RCV Interrupt 5 Connect 1 0: Unmask Connect Interrupt 1: Mask Connect Interrupt t 6 OTP_EN 1 0: Unmask OTP_EN Interrupt 1: Mask OTP_EN Interrupt 7 Unused 1 BIT NO. NAME SIZE (BITS) 0-4 ADC value 5 5-7 N/A 3 DESCRIPTION ADC Value Address: 07h Reset Value: xxx11111 Type: Read Copyright © 2011, Texas Instruments Incorporated DESCRIPTION ADC value read from ID 31 TSU6712 SCDS321 – MAY 2011 www.ti.com Timing Set 1 Address: 08h Reset Value: 00000000 Type: Read/Write BIT NO. NAME SIZE (BITS) 0-3 Device wake up 4 Device wake up duration 4-7 Key press 4 Normal key press duration DESCRIPTION Timing Set 2 Address: 09h Reset Value: 00000000 Type: Read/Write BIT NO. NAME SIZE (BITS) 0-3 Long key press 4 Long key press duration 4-7 Switching wait 4 Waiting duration before switching DESCRIPTION Table 4. Time Table SETTING VALUE DEVICE WAKE UP KEY PRESS LONG KEY PRESS SWITCHING WAIT (1) 0000 50 ms 100 ms 300 ms 10 ms 0001 100 ms 200 ms 400 ms 30 ms 0010 150 ms 300 ms 500 ms 50 ms 0011 200 ms 400 ms 600 ms 70 ms 0100 300 ms 500 ms 700 ms 90 ms 0101 400 ms 600 ms 800 ms 110 ms 0110 500 ms 700 ms 900 ms 130 ms 0111 600 ms 800 ms 1000 ms 150 ms 1000 700 ms 900 ms 1100 ms 170 ms 1001 800 ms 1000 ms 1200 ms 190 ms 1010 900 ms – 1300 ms 210 ms 1011 1000 ms – 1400 ms – 1100 – – 1500 ms – 1101 – – – – 1110 – – – – 1111 – – – – (1) 32 Switching wait time does not apply to Car Kit. Copyright © 2011, Texas Instruments Incorporated TSU6712 SCDS321 – MAY 2011 www.ti.com Device Type 1 Address: 0Ah Reset Value: 00000000 Type: Read BIT NO. NAME SIZE (BITS) 0 Audio type 1 1 Audio device type 1 1 Audio type 2 1 Audio device type 2 2 USB 1 USB host 3 UART 1 UART 4 Car Kit 1 Car Kit 5 CDP 1 Charging Downstream Port (USB Host Hub Charger) 6 DCP 1 Dedicated Charging Charger 7 USB OTG 1 USB on-the-go device NAME SIZE (BITS) 0 JIG_USB_ON 1 Factory mode cable 1 JIG_USB_OFF 1 Factory mode cable 2 JIG_UART_ON 1 Factory mode cable 3 JIG_UART_OFF 1 Factory mode cable 4 PPD 1 Phone-powered device 5 TTY 1 TTY converter 6 A/V 1 A/V cable 7 Unused 1 DESCRIPTION Device Type 2 Address: 0Bh Reset Value: x0000000 Type: Read BIT NO. Copyright © 2011, Texas Instruments Incorporated DESCRIPTION 33 TSU6712 SCDS321 – MAY 2011 www.ti.com Button 1 Address: 0Ch Reset Value: 00000000 Type: Read and Clear BIT NO. NAME SIZE (BITS) 0 Send_End 1 Send_End key is pressed 1 1 1 Number 1 key is pressed 2 2 1 Number 2 key is pressed 3 3 1 Number 3 key is pressed 4 4 1 Number 4 key is pressed 5 5 1 Number 5 key is pressed 6 6 1 Number 6 key is pressed 7 7 1 Number 7 key is pressed DESCRIPTION Button 2 Address: 0Dh Reset Value: x0000000 Type: 34 Read and Clear BIT NO. NAME SIZE (BITS) 0 8 1 Number 8 key is pressed 1 9 1 Number 9 key is pressed 2 10 1 Number 10 key is pressed 3 11 1 Number 11 key is pressed 4 12 1 Number 12 key is pressed 5 Error 1 Error key is pressed 6 Unknown 1 Unknown key is pressed 7 Unused DESCRIPTION Copyright © 2011, Texas Instruments Incorporated TSU6712 SCDS321 – MAY 2011 www.ti.com Carkit Status Address: 0Eh Reset Value: x0000000 Type: Read and write BIT NO. 0-1 (1) NAME Type SIZE (BITS) DESCRIPTION 2 Detected Carkit type 00: No connection 01: Carkit 10: Carkit charger type 1 11: Carkit charger type 2 2-4 Mode 3 Carkit mode change 000: Open all path for carkit except load switch (1) 001: UART (1) 010: Carkit audio mono 011: Carkit audio stereo 100: DDA mono (1) 101: DDA stereo (1) 5 UART_Traffic 1 000: UART is disabled 001: UART is enabled 6 Disc_Request 1 000: Carkit is disconnected 001: Carkit is connected 7 Unused 1 Audio type 2 uses mode 000, 001, 100, and 101 of carkit status register to change device mode. Copyright © 2011, Texas Instruments Incorporated 35 TSU6712 SCDS321 – MAY 2011 www.ti.com Carkit Interrupt 1 Address: 0Fh Reset Value: 0000000 Type: Read and Clear NAME SIZE (BITS) 0 Ph_Init 1 1: Switching IC is in initial stage 1 Ph_UART 1 1: Switching IC is in UART stage 2 Ph_Aud_Mono 1 1: Switching IC is in mono audio stage 3 Ph_Aud_Stereo 1 1: Switching IC is in stereo audio stage 4 Ph_DDA_Mono 1 1: Switching IC is in DDA mono audio stage 5 Ph_DDA_Stereo 1 1: Switching IC is in DDA stereo audio stage 6 Ph_Disc 1 1: Switching IC is in disconnection stage 7 CR_UART 1 1: Carkit generates interrupt BIT NO. DESCRIPTION PH_INIT – Set high when TSU6712 enters ph_init state. PH_UART – Set high when TSU6712 enters ph_uart state. PH_DISC – Set high when TSU6712 enters Standby state. CR_UART – Set high when DP pulled below VCR_PLS_NEG for time of TCR_PLS_NEG while in ph_uart_4w state. Used to indicate to TSU6712 that button on Carkit has been pushed when UART traffic has not been enabled. Carkit Interrupt 2 Address: 10h Reset Value: xxxx000 Type: Read and Clear NAME SIZE (BITS) 0 CR_Mono 1 1: Carkit generates interrupt 1 CR_Stereo 1 1: Carkit generates interrupt 2 CR_DDA_Stereo 1 1: Carkit generates interrupt 3 CR_ERROR 1 1: Incomplete Carkit connection sequence 4–7 Unused 4 BIT NO. 36 DESCRIPTION CR_MONO Set high when DP pulled below VCR_PLS_NEG for time of TCR_PLS_NEG while in – ph_aud_4w state and STEREO_MODE = 0. Used to indicate to TSU6712 that button on Carkit has been pushed when DDA is low. CR_STEREO Set high when DP pulled below VCR_PLS_NEG for time of TCR_PLS_NEG while in – ph_aud_4w state and STEREO_MODE = 1. Used to indicate to TSU6712 that button on Carkit has been pushed when DDA is low. Copyright © 2011, Texas Instruments Incorporated TSU6712 SCDS321 – MAY 2011 www.ti.com Carkit Interrupt Mask 1 Address: 0Eh Reset Value: x0000000 Type: Read and write BIT NO. NAME SIZE (BITS) 0 PH_Init 1 0: Unmask PH_Init Interrupt 1: Mask PH_Init interrupt 1 PH_UART 1 0: Unmask PH_UART interrupt 1: Mask PH_UART interrupt 2 PH_Aud_Mono 1 0: Unmask PH_Aud_Mono interrupt 1: Mask PH_Aud_Mono interrupt 3 PH_Aud_Stereo 1 0: Unmask PH_Aud_Stereo interrupt 1: Mask PH_Aud_Stereot interrupt 4 PH_DDA_Mono 1 0: Unmask PH_DDA_Mono interrupt 1: Mask PH_DDA_Mono interrupt 5 PH_DDA_Stereo 1 0: Unmask PH_DDA_Stereo interrupt 1: Mask PH_DDA_Stereo interrupt 6 PH_Disc 1 0: Unmask PH_Disc interrupt 1: Mask PH_Disc interrupt 7 CR_UART 1 0: Unmask CR_UART interrupt 1: Mask CR_UART interrupt DESCRIPTION Carkit Interrupt Mask 2 Address: 12h Reset Value: xxxx0000 Type: Read and write BIT NO. NAME SIZE (BITS) 0 CR_Mono 1 0: Unmask CR_Mono interrupt 1: Mask CR_Mono interrupt 1 CR_Stereo 1 0: Unmask CR_Stereo interrupt 1: Mask CR_Stereo interrupt 2 CR_DDA_Stereo 1 0: Unmask CR_DDA_Stereo interrupt 1: Mask CR_DDA_Stereo interrupt 3 CR_Error 1 1: Incomplete Carkit connection sequence 4–7 Unused 4 Copyright © 2011, Texas Instruments Incorporated DESCRIPTION 37 TSU6712 SCDS321 – MAY 2011 www.ti.com Manual S/W 1 Address: 13h Reset Value: 00000000 Type: Read and write BIT NO. NAME SIZE (BITS) 0-1 VBUS Switching 2 00: Open all switch 01: VBUS is connected to OUT (charger) 10: VBUS is connected to MIC 3 000: Open all switch 001: D+ is connected to D+ of USB port 010: D+ is connected to S_R 011: D+ is connected to RxD of UART 100-111: Reserved 3 000: Open all switch 001: D– is connected to D– of USB port 010: D– is connected to S_L 011: D– is connected to TxD of UART 100-111: Reserved 2-4 5-7 D+ Switching D– Switching DESCRIPTION Manual S/W 2 Address: 14h Reset Value: xxx00000 Type: 38 Read and write SIZE (BITS) BIT NO. NAME DESCRIPTION 0-1 N/A 2 JIG 1 0: Low 1: High 3 BOOT 1 0: Low 1: High 4 ISET 1 0: High Impedance 1: GND 5-7 N/A Copyright © 2011, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 26-May-2011 PACKAGING INFORMATION Orderable Device TSU6712YFPRB Status (1) PREVIEW Package Type Package Drawing DSBGA YFP Pins Package Qty 25 3000 Eco Plan TBD (2) Lead/ Ball Finish Call TI MSL Peak Temp (3) Samples (Requires Login) Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 25-May-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device TSU6712YFPRB Package Package Pins Type Drawing SPQ DSBGA 3000 YFP 25 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 178.0 9.2 Pack Materials-Page 1 2.19 B0 (mm) K0 (mm) P1 (mm) 2.19 0.62 4.0 W Pin1 (mm) Quadrant 8.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 25-May-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TSU6712YFPRB DSBGA YFP 25 3000 220.0 220.0 35.0 Pack Materials-Page 2 D: Max = 2.09 mm, Min = 2.03 mm E: Max = 2.09 mm, Min = 2.03 mm IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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