FAN54015 - Fairchild Semiconductor

FAN54015
USB-Compliant Single-Cell Li-Ion Switching Charger with
USB-OTG Boost Regulator
Features
Description

Fully Integrated, High-Efficiency Charger for Single-Cell
Li-Ion and Li-Polymer Battery Packs


Faster Charging than Linear
The FAN54015 combines a highly integrated switch-mode
charger, to minimize single-cell Lithium-ion (Li-ion) charging
time from a USB power source, and a boost regulator to
power a USB peripheral from the battery.






5% Input Current Regulation Accuracy
Charge Voltage Accuracy:
0.5% at 25°C
1% from 0 to 125°C
5% Charge Current Regulation Accuracy
20 V Absolute Maximum Input Voltage
6 V Maximum Input Operating Voltage
1.45 A Maximum Charge Rate
Programmable through High-Speed I2C Interface
(3.4 Mb/s) with Fast Mode Plus Compatibility
– Input Current
–
–
–
Fast-Charge / Termination Current
Charger Voltage
Termination Enable

3 MHz Synchronous Buck PWM Controller with Wide
Duty Cycle Range






Small Footprint 1 H External Inductor

Safety Timer with Reset Control
1.8 V Regulated Output from VBUS for Auxiliary Circuits
Dynamic Input Voltage Control
Low Reverse Leakage to Prevent Battery Drain to VBUS
5 V, 500 mA Boost Mode for USB OTG for 3.0 V to
4.5 V Battery Input
Available in a 1.96 x 1.87 mm, 20-bump, 0.4 mm Pitch
WLCSP Package
Applications



Cell Phones, Smart Phones, PDAs
Tablet, Portable Media Players
The charging parameters and operating modes are
programmable through an I2C Interface that operates up to
3.4 Mbps. The charger and boost regulator circuits switch at
3 MHz to minimize the size of external passive components.
The FAN54015 provides battery charging in three phases:
conditioning, constant current and constant voltage.
To ensure USB compliance and minimize charging time, the
input current limit can be changed through the I2C by the
host processor. Charge termination is determined by a
programmable minimum current level. A safety timer with
reset control provides a safety backup for the I2C host.
Charge status is reported to the host through the I2C port.
The integrated circuit (IC) automatically restarts the charge
cycle when the battery falls below an internal threshold. If the
input source is removed, the IC enters a high-impedance
mode, preventing leakage from the battery to the input.
Charge current is reduced when the die temperature reaches
120°C, protecting the device and PCB from damage.
The FAN54015 can operate as a boost regulator on
command from the system. The boost regulator includes a
soft-start that limits inrush current from the battery and uses
the same external components used for charging the battery.
L1
SW
VBUS
CBUS
1H
1F
COUT
0.1F
PGND
PMID
CMID
CSIN
4.7F
SDA
SCL
RSENSE
FAN54015
68m
VBAT
DISABLE
OTG/USB#
STAT
VREG
CREG
+ Battery
CBAT
SYSTEM
LOAD
10F
1F
Gaming Device, Digital Cameras
Figure 1. Typical Application
All trademarks are the property of their respective owners.
© 2012 Fairchild Semiconductor Corporation
FAN54015 • Rev. 1.0.2
www.fairchildsemi.com
FAN54015 — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
October 2013
Part Number
Temperature
Range
Package
-40 to 85°C
20-Bump, Wafer-Level Chip-Scale Package (WLCSP),
0.4 mm Pitch, Estimated Size: 1.96 x 1.87 mm
FAN54015UCX
FAN54015BUCX(1)
Packing
Method
PN Bits:
IC_INFO[4:2]
Tape and
Reel
101
Note:
1. FAN54015BUCX includes backside lamination.
Table 1. Feature Summary
Part Number
Slave Address
Automatic
Charge
Special
Charger(2)
Safety
Limits
Battery Absent
Behavior
E2 Pin
VREG
(E3 Pin)
FAN54015UCX
1101010
Yes
Yes
Yes
ON
DISABLE
1.8 V
Note:
2. A “special charger” is a current-limited charger that is not a USB compliant source.
Block Diagram
VREG
1.8V / PMID REG
CREG
PMID
1F
PMID
Q1
Q3
CMID
Q1A
VBUS
CBUS
CHARGE
PUMP
1F
4.7F
Q1B
SW
VBUS
OVP
PWM
MODULATOR
I_IN
CONTROL
Q2
L1
1H
COUT
RSENSE
0.1F
DAC
VCC
PGND
VREF
CSIN
+
Battery
VBAT
SDA
SCL
DISABLE
OTG/USB#
PMID
I2C
INTERFACE
STAT
30mA
CBAT
SYSTEM
LOAD
OSC
LOGIC
AND
CONTROL
PMID
Greater than VBAT
Less than VBAT
Q1A
ON
OFF
Q1B
OFF
ON
Figure 2. IC and System Block Diagram
Table 2. Recommended External Components
Component
Description
Vendor
1 H ±20%, 1.6 A, DCR=55 m, 2520
Murata: LQM2HPN1R0
1 H ±30%, 1.4 A, DCR=85 m, 2016
Murata: LQM2MPN1R0
CBAT
10 F, 20%, 6.3 V, X5R, 0603
CMID
CBUS
L1
Parameter
Typ. Unit
L
1.0
H
Murata: GRM188R60J106M
TDK: C1608X5R0J106M
C
10
F
4.7 F, 10%, 6.3 V, X5R, 0603
Murata: GRM188R60J475K
TDK: C1608X5R0J475K
C(3)
4.7
F
1.0 F, 10%, 25 V, X5R, 0603
Murata GRM188R61E105K
TDK:C1608X5R1E105M
C
1.0
F
Note:
3. A 6.3 V rating is sufficient for CMID because PMID is protected from over-voltage surges on VBUS by Q3 (Figure 2).
© 2012 Fairchild Semiconductor Corporation
FAN54015 • Rev. 1.0.2
www.fairchildsemi.com
2
FAN54015 — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Ordering Information
A1
A2
A3
A4
A4
A3
A2
A1
B1
B2
B3
B4
B4
B3
B2
B1
C1
C2
C3
C4
C4
C3
C2
C1
D1
D2
D3
D4
D4
D3
D2
D1
E1
E2
E3
E4
E4
E3
E2
E1
Top View
Bottom View
Figure 3. WLCSP-20 Pin Assignments
Pin Definitions
Pin #
Name
Description
A1, A2
VBUS
Charger Input Voltage and USB-OTG output voltage. Bypass with a 1 F capacitor to PGND.
A3
NC
No Connect. No external connection is made between this pin and the IC’s internal circuitry.
A4
SCL
I2C Interface Serial Clock. This pin should not be left floating.
B1-B3
PMID
Power Input Voltage. Power input to the charger regulator, bypass point for the input current sense,
and high-voltage input switch. Bypass with a minimum of 4.7 F, 6.3 V capacitor to PGND.
B4
SDA
I2C Interface Serial Data. This pin should not be left floating.
C1-C3
SW
Switching Node. Connect to output inductor.
C4
STAT
Status. Open-drain output indicating charge status. The IC pulls this pin LOW when charging.
D1-D3
PGND
Power Ground. Power return for gate drive and power transistors. The connection from this pin to the
bottom of CMID should be as short as possible.
D4
OTG
On-The-Go. Enables boost regulator in conjunction with OTG_EN and OTG_PL bits (see Table 16). On
VBUS Power-On Reset (POR), this pin sets the input current limit for t15MIN charging.
E1
CSIN
Current-Sense Input. Connect to the sense resistor in series with the battery. The IC uses this node to
sense current into the battery. Bypass this pin with a 0.1 F capacitor to PGND.
E2
DISABLE
E3
VREG
Regulator Output. Connect to a 1 F capacitor to PGND. This pin can supply up to 2mA of DC load
current. The output voltage is PMID, which is limited to 1.8 V.
E4
VBAT
Battery Voltage. Connect to the positive (+) terminal of the battery pack. Bypass with a 0.1 F
capacitor to PGND if the battery is connected through long leads.
Charge Disable. If this pin is HIGH, charging is disabled. When LOW, charging is controlled by the
I2C registers. When this pin is HIGH, the 15-minute timer is reset. This pin does not affect the
32-second timer.
© 2012 Fairchild Semiconductor Corporation
FAN54015 • Rev. 1.0.2
www.fairchildsemi.com
3
FAN54015 — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Pin Configuration
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above
the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended
exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum
ratings are stress ratings only.
Symbol
Parameter
VBUS
VBUS Voltage
VSTAT
STAT Voltage
VI
VO
Min.
Continuous
–1.4
Pulsed, 100 ms Maximum Non-Repetitive
–2.0
–0.3
PMID Voltage
Max.
Unit
20.0
V
16.0
V
7.0
V
SW, CSIN, VBAT, DISABLE Voltage
–0.3
7.0
Voltage on Other Pins
–0.3
6.5(4)
V
4
V/s
dVBUS
dt
Maximum VBUS Slope above 5.5 V when Boost or Charger are Active
ESD
Electrostatic Discharge
Protection Level
TJ
Junction Temperature
–40
+150
°C
TSTG
Storage Temperature
–65
+150
°C
+260
°C
TL
Human Body Model per JESD22-A114
2000
Charged Device Model per JESD22-C101
500
Lead Soldering Temperature, 10 Seconds
V
Note:
4. Lesser of 6.5 V or VI + 0.3 V.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating
conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend
exceeding them or designing to absolute maximum ratings.
Symbol
VBUS
VBAT(MAX)

dVBUS
dt
Parameter
Min.
Supply Voltage
4
Maximum Battery Voltage when Boost enabled
Negative VBUS Slew Rate during VBUS Short Circuit,
CMID < 4.7 F (see VBUS Short While Charging)
Max.
Unit
6
V
4.5
V
TA < 60°C
4
TA > 60°C
2
V/s
TA
Ambient Temperature
–30
+85
°C
TJ
Junction Temperature (see Thermal Regulation and Protection section)
–30
+120
°C
Thermal Properties
Junction-to-ambient thermal resistance is a function of application and board layout. This data is measured with four-layer
2s2p boards in accordance to JEDEC standard JESD51. Special attention must be paid not to exceed junction temperature
TJ(max) at a given ambient temperature TA. For measured data, see Table 11.
Symbol Parameter
Typical
Unit
JA
Junction-to-Ambient Thermal Resistance
60
°C/W
JB
Junction-to-PCB Thermal Resistance
20
°C/W
© 2012 Fairchild Semiconductor Corporation
FAN54015 • Rev. 1.0.2
www.fairchildsemi.com
4
FAN54015 — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Absolute Maximum Ratings
Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for TJ and TA;
VBUS=5.0 V; HZ_MODE; OPA_MODE=0; (Charge Mode); SCL, SDA, OTG=0 or 1.8 V; and typical values are for TJ=25°C.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
Power Supplies
IVBUS
VBUS Current
ILKG
VBAT to VBUS Leakage Current
IBAT
Battery Discharge Current in HighImpedance Mode
VBUS > VBUS(min), PWM Switching
10
mA
VBUS > VBUS(min); PWM Enabled,
Not Switching (Battery OVP
Condition); I_IN Setting=100 mA
2.5
mA
0°C < TJ < 85°C, HZ_MODE=1
VBAT < VLOWV, 32S Mode
63
90
A
0°C < TJ < 85°C, HZ_MODE=1,
VBAT=4.2 V, VBUS=0 V
0.2
5.0
A
0°C < TJ < 85°C, HZ_MODE=1,
VBAT=4.2 V
20
DISABLE=1, 0°C < TJ < 85°C,
VBAT=4.2 V
10
A
Charger Voltage Regulation
Charge Voltage Range
VOREG
Charge Voltage Accuracy
3.5
4.4
–0.5%
+0.5%
TJ=0 to 125°C
–1%
+1%
VLOWV < VBAT < VOREG, RSENSE=68 m
550
1450
mA
20 mV ≤ VIREG ≤ 40 mV
92
97
102
%
VIREG > 40 mV
94
97
100
%
TA=25°C
V
Charging Current Regulation
Output Charge Current Range
IOCHRG
Charge Current Accuracy Across
RSENSE
Weak Battery Detection
VLOWV
Weak Battery Threshold Range
3.4
3.7
V
Weak Battery Threshold Accuracy
–5
+5
%
Weak Battery Deglitch Time
Rising Voltage
30
ms
Logic Levels: DISABLE, SDA, SCL, OTG
VIH
High-Level Input Voltage
VIL
Low-Level Input Voltage
IIN
Input Bias Current
1.05
Input Tied to GND or VIN
V
0.01
0.4
V
1.00
A
mA
Charge Termination Detection
Termination Current Range
I(TERM)
Termination Current Accuracy
Termination Current Deglitch Time
VBAT > VOREG – VRCH, RSENSE=68 m
50
400
[VCSIN – VBAT ] from 3 mV to 20 mV
–25
+25
[VCSIN – VBAT ] from 20 mV to 40 mV
–5
+5
2 mV Overdrive
30
%
ms
1.8V Linear Regulator
VREG
1.8V Regulator Output
IREG from 0 to 2 mA
1.7
1.8
1.9
V
Input Power Source Detection
VIN(MIN)1
VBUS Input Voltage Rising
To Initiate and Pass VBUS Validation
4.29
4.42
V
VIN(MIN)2
Minimum VBUS During Charge
During Charging
3.71
3.94
V
tVBUS_VALID
VBUS Validation Time
30
ms
Continued on the following page…
© 2012 Fairchild Semiconductor Corporation
FAN54015 • Rev. 1.0.2
www.fairchildsemi.com
5
FAN54015 — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Electrical Specifications
Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for TJ and TA;
VBUS=5.0 V; HZ_MODE; OPA_MODE=0; (Charge Mode); SCL, SDA, OTG=0 or 1.8 V; and typical values are for TJ=25°C.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
+3
%
Special Charger (VBUS)
VSP
–3
Special Charger Setpoint Accuracy
Input Current Limit
IINLIM
Input Current Limit Threshold
IIN Set to 100 mA
88
93
98
IIN Set to 500 mA
450
475
500
mA
VREF Bias Generator
VREF
Bias Regulator Voltage
VBUS > VIN(MIN) or VBAT > VBAT(MIN)
6.5
Short-Circuit Current Limit
20
V
mA
Battery Recharge Threshold
Recharge Threshold
Below V(OREG)
Deglitch Time
VBAT Falling Below VRCH Threshold
VSTAT(OL)
STAT Output Low
ISTAT=10 mA
ISTAT(OH)
STAT High Leakage Current
VSTAT=5 V
VRCH
100
120
150
130
mV
ms
STAT Output
0.4
V
1
A
Battery Detection
IDETECT
Battery Detection Current before
Charge Done (Sink Current)(5)
tDETECT
Battery Detection Time
Begins after Termination Detected
and VBAT < VOREG –VRCH
–0.80
mA
262
ms
Sleep Comparator
VSLP
tSLP_EXIT
Sleep-Mode Entry Threshold,
VBUS – VBAT
2.3 V < VBAT < VOREG, VBUS Falling
Deglitch Time for VBUS Rising
Above VBAT by VSLP
Rising Voltage
30
IIN(LIMIT)=500 mA
0
0.04
0.10
V
ms
Power Switches (see Figure 2)
Q3 On Resistance (VBUS to PMID)
RDS(ON)
180
250
Q1 On Resistance (PMID to SW)
130
225
Q2 On Resistance (SW to GND)
150
225
mΩ
Charger PWM Modulator
fSW
Oscillator Frequency
DMAX
Maximum Duty Cycle
DMIN
Minimum Duty Cycle
ISYNC
Synchronous to Non-Synchronous
Current Cut-Off Threshold(6)
2.7
Low-Side MOSFET (Q2) Cycle-byCycle Current Limit
3.0
3.3
MHz
100
%
0
%
140
mA
Boost Mode Operation (OPA_MODE=1, HZ_MODE=0)
VBOOST
Boost Output Voltage at VBUS
IBAT(BOOST)
Boost Mode Quiescent Current
ILIMPK(BST)
Q2 Peak Current Limit
UVLOBST
Minimum Battery Voltage for Boost
Operation
2.5 V < VBAT < 4.5 V, ILOAD from 0 to
200 mA
4.80
5.07
5.17
3.0 V < VBAT < 4.5 V, ILOAD from 0 to
500 mA
4.77
5.07
5.17
140
300
A
1590
1908
mA
V
PFM Mode, VBAT=3.6 V, IOUT=0
1272
While Boost Active
2.42
To Start Boost Regulator
2.58
2.70
V
Continued on the following page…
© 2012 Fairchild Semiconductor Corporation
FAN54015 • Rev. 1.0.2
www.fairchildsemi.com
6
FAN54015 — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Electrical Specifications
Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for TJ and TA;
VBUS=5.0 V; HZ_MODE; OPA_MODE=0; (Charge Mode); SCL, SDA, OTG=0 or 1.8 V; and typical values are for TJ=25°C.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
VBUS Load Resistance
RVBUS
VBUS to PGND Resistance
Normal Operation
1500
k
Charger Validation
100

Protection and Timers
VBUSOVP
ILIMPK(CHG)
VSHORT
ISHORT
TSHUTDWN
VBUS Over-Voltage Shutdown
VBUS Rising
Hysteresis
VBUS Falling
100
mV
Q1 Cycle-by-Cycle Peak Current
Limit
Charge Mode
2.3
A
Battery Short-Circuit Threshold
VBAT Rising
Hysteresis
VBAT Falling
Linear Charging Current
VBAT < VSHORT
Thermal Shutdown Threshold
Hysteresis
(7)
(7)
TCF
Thermal Regulation Threshold(7)
tINT
Detection Interval
t32S
32-Second Timer(8)
6.09
1.95
6.29
2.00
6.49
2.05
100
20
30
V
V
mV
40
mA
TJ Rising
145
TJ Falling
10
Charge Current Reduction Begins
120
°C
2.1
s
°C
Charger Enabled
20.5
25.2
28.0
Charger Disabled
18.0
25.2
34.0
13.5
15.0
min
25
%
t15MIN
15-Minute Timer
15-Minute Mode
12.0
∆tLF
Low-Frequency Timer Accuracy
Charger Inactive
–25
s
Notes:
5. Negative current is current flowing from the battery to VBUS (discharging the battery).
6. Q2 always turns on for 60 ns, then turns off if current is below ISYNC.
7. Guaranteed by design; not tested in production.
8. This tolerance (%) applies to all timers on the IC, including soft-start and deglitching timers.
© 2012 Fairchild Semiconductor Corporation
FAN54015 • Rev. 1.0.2
www.fairchildsemi.com
7
FAN54015 — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Electrical Specifications
Guaranteed by design.
Symbol
Parameter
Conditions
Min.
Typ.
Standard Mode
fSCL
tBUF
SCL Clock Frequency
Bus-Free Time between STOP
and START Conditions
tHD;STA
tLOW
SCL LOW Period
Fast Mode
400
High-Speed Mode, CB < 100 pF
3400
High-Speed Mode, CB < 400 pF
1700
Standard Mode
4.7
Fast Mode
1.3
tSU;STA
tSU;DAT
SCL HIGH Period
Repeated START Setup Time
Data Setup Time
tRCL
tFCL
tRDA
tRCL1
Data Hold Time
SCL Rise Time
SCL Fall Time
SDA Rise Time
Rise Time of SCL after a
Repeated START Condition
and after ACK Bit
s
s
Fast Mode
600
ns
High-Speed Mode
160
ns
Standard Mode
4.7
s
Fast Mode
1.3
s
High-Speed Mode, CB < 100 pF
160
ns
High-Speed Mode, CB < 400 pF
320
ns
4
s
Fast Mode
600
ns
High-Speed Mode, CB < 100 pF
60
ns
High-Speed Mode, CB < 400 pF
120
ns
Standard Mode
4.7
s
Fast Mode
600
ns
High-Speed Mode
160
ns
Standard Mode
250
Fast Mode
100
High-Speed Mode
tHD;DAT
kHz
4
Standard Mode
tHIGH
Unit
100
Standard Mode
START or Repeated START
Hold Time
Max.
ns
10
Standard Mode
0
3.45
s
Fast Mode
0
900
ns
High-Speed Mode, CB < 100 pF
0
70
ns
ns
High-Speed Mode, CB < 400 pF
0
150
Standard Mode
20+0.1CB
1000
Fast Mode
20+0.1CB
300
High-Speed Mode, CB < 100 pF
10
80
High-Speed Mode, CB < 400 pF
20
160
Standard Mode
20+0.1CB
300
Fast Mode
20+0.1CB
300
High-Speed Mode, CB < 100 pF
10
40
High-Speed Mode, CB < 400 pF
20
80
Standard Mode
20+0.1CB
1000
Fast Mode
20+0.1CB
300
High-Speed Mode, CB < 100 pF
10
80
High-Speed Mode, CB < 400 pF
20
160
ns
ns
ns
Continued on the following page…
© 2012 Fairchild Semiconductor Corporation
FAN54015 • Rev. 1.0.2
www.fairchildsemi.com
8
FAN54015 — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
I2C Timing Specifications
Guaranteed by design.
Symbol
Parameter
tFDA
Conditions
SDA Fall Time
tSU;STO
Stop Condition Setup Time
CB
Min.
Typ.
Max.
Standard Mode
20+0.1CB
300
Fast Mode
Unit
20+0.1CB
300
High-Speed Mode, CB < 100 pF
10
80
High-Speed Mode, CB < 400 pF
20
160
Standard Mode
4
s
Fast Mode
600
ns
High-Speed Mode
160
Capacitive Load for SDA, SCL
ns
ns
400
pF
Timing Diagrams
tF
tSU;STA
tBUF
SDA
tR
TSU;DAT
tHD;STO
tHIGH
SCL
tLOW
tHD;STA
tHD;DAT
tHD;STA
REPEATED
START
START
STOP
START
Figure 4. I2C Interface Timing for Fast and Slow Modes
tFDA
tRDA
REPEATED
START
tSU;DAT
STOP
SDAH
tSU;STA
tRCL1
tFCL
tRCL
tSU;STO
tHIGH
SCLH
tLOW
tHD;STA
tHD;DAT
REPEATED
START
note A
= MCS Current Source Pull-up
= RP Resistor Pull-up
Note A: First rising edge of SCLH after Repeated Start and after each ACK bit.
Figure 5. I2C Interface Timing for High-Speed Mode
© 2012 Fairchild Semiconductor Corporation
FAN54015 • Rev. 1.0.2
www.fairchildsemi.com
9
FAN54015 — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
I2C Timing Specifications
180
900
160
800
140
700
Battery Charge Current (mA)
Battery Charge Current (mA)
Unless otherwise specified, circuit of Figure 1, VOREG=4.2 V, VBUS=5.0 V, and TA=25°C.
120
100
80
60
40
5.5VBUS
600
500
400
300
200
5.0VBUS
20
5.5VBUS
5.0VBUS
100
4.5VBUS
4.5VBUS
-
2.5
3
3.5
4
4.5
2.5
3
Battery Voltage, VBAT (V)
3.5
4
4.5
Battery Voltage, VBAT (V)
Figure 6. Battery Charge Current vs. VBUS with
IINLIM=100 mA
Figure 7. Battery Charge Current vs. VBUS with
IINLIM=500 mA
94%
97%
4.20VBAT, 4.5VBUS
4.20VBAT, 5.0VBUS
3.54VBAT, 5.0VBUS
94%
92%
Efficiency
Efficiency
3.54VBAT, 4.5VBUS
91%
88%
85%
90%
88%
86%
4.5VBUS
5.0VBUS
5.5VBUS
82%
100
84%
300
500
700
900
1100
1300
1500
2.5
Battery Charge Current (mA)
2.9
3.1
3.3
3.5
3.7
3.9
4.1
4.3
Battery Voltage, VBAT (V)
Figure 8. Charger Efficiency, No IINLIM, IOCHARGE=1450 mA
Figure 9. Charger Efficiency vs. VBUS, IINLIM=500 mA
Figure 10. Auto-Charge Startup at VBUS Plug-in,
IINLIM=100 mA, OTG=1, VBAT=3.4 V
© 2012 Fairchild Semiconductor Corporation
FAN54015 • Rev. 1.0.2
2.7
Figure 11. Auto-Charge Startup at VBUS Plug-in,
IINLIM=500 mA, OTG=1, VBAT=3.4 V
www.fairchildsemi.com
10
FAN54015 — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Charge Mode Typical Characteristics
Unless otherwise specified, circuit of Figure 1, VOREG=4.2 V, VBUS=5.0 V, and TA=25°C.
Figure 12. AutoCharge Startup with 300mA Limited
Charger / Adaptor, IINLIM=500 mA, OTG=1, VBAT=3.4 V
Figure 13. Charger Startup with HZ_MODE Bit Reset,
IINLIM=500 mA, IOCHARGE=1050 mA, OREG=4.2 V, VBAT=3.6 V
Figure 14. Battery Removal / Insertion During Charging,
VBAT=3.9 V, IOCHARGE=1050 mA, No IINLIM, TE=0
Figure 15. Battery Removal / Insertion During Charging,
VBAT=3.9 V, IOCHARGE=1050 mA, No IINLIM, TE=1
© 2012 Fairchild Semiconductor Corporation
FAN54015 • Rev. 1.0.2
www.fairchildsemi.com
11
FAN54015 — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Charge Mode Typical Characteristics
Unless otherwise specified, circuit of Figure 1, VOREG=4.2 V, VBUS=5.0 V, and TA=25°C.
1.82
200
-30C
+25C
1.80
VREG (V)
High-Z Mode Current (A)
1.81
150
+85C
100
1.79
-10C, 5.0VBUS
50
1.78
+25C, 5.0VBUS
+85C, 5.0VBUS
0
1.77
4.0
4.5
5.0
5.5
6.0
0
Input Voltage, VBUS (V)
1
2
3
4
5
1.8V Regulator Load Current (mA)
Figure 16. VBUS Current in High-Impedance Mode
with Battery Open
Figure 17. VREG 1.8 V Output Regulation
Figure 18. No Battery, VBUS at Power Up
© 2012 Fairchild Semiconductor Corporation
FAN54015 • Rev. 1.0.2
www.fairchildsemi.com
12
FAN54015 — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Charge Mode Typical Characteristics
100
100
95
95
90
90
Efficiency (%)
Efficiency (%)
Unless otherwise specified, using circuit of Figure 1, VBAT=3.6 V, TA=25°C.
85
3.0 VBAT
80
85
-10C, 3.6VBAT
80
+25C, 3.6VBAT
3.6 VBAT
+85C, 3.6VBAT
4.2 VBAT
75
75
0
100
200
300
400
0
500
100
200
300
400
500
VBUS Load Current (mA)
VBUS Load Current (mA)
Figure 19. Efficiency vs. VBAT
Figure 20. Efficiency Over Temperature
5.10
5.10
3.0 VBAT
-10C, 3.6VBAT
3.6 VBAT
5.05
+25C, 3.6VBAT
5.05
4.2 VBAT
+85C, 3.6VBAT
5.00
VBUS (V)
VBUS (V)
5.00
4.95
4.95
4.90
4.90
4.85
4.85
4.80
4.80
0
100
200
300
400
500
0
100
VBUS Load Current (mA)
200
300
400
500
VBUS Load Current (mA)
Figure 21. Output Regulation vs. VBAT
Figure 22. Output Regulation Over Temperature
250
20
-30C
Quiescent Current (µA)
High-Z Mode Current (µA)
+25C
200
+85C
150
100
15
10
-30C
5
+25C
+85C
50
0
2
2.5
3
3.5
4
4.5
5
2
Battery Voltage, VBAT (V)
3
3.5
4
4.5
5
Battery Voltage, VBAT (V)
Figure 23. Quiescent Current
© 2012 Fairchild Semiconductor Corporation
FAN54015 • Rev. 1.0.2
2.5
Figure 24. High-Impedance Mode Battery Current
www.fairchildsemi.com
13
FAN54015 — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Boost Mode Typical Characteristics
Unless otherwise specified, using circuit of Figure 1, VBAT=3.6 V, TA=25°C.
Figure 25. Boost PWM Waveform
Figure 26. Boost PFM Waveform
30
30
2.7 VBAT
-30C, 3.6VBAT
3.6 VBAT
25
+25C, 3.6VBAT
25
4.2 VBAT
+85C, 3.6VBAT
VBUS Ripple (mVpp)
VBUS Ripple (mVpp)
4.5 VBAT
20
15
10
5
20
15
10
5
0
0
0
100
200
300
400
500
0
VBUS Load Current (mA)
200
300
400
500
VBUS Load Current (mA)
Figure 27. Output Ripple vs. VBAT
© 2012 Fairchild Semiconductor Corporation
FAN54015 • Rev. 1.0.2
100
Figure 28. Output Ripple vs. Temperature
www.fairchildsemi.com
14
FAN54015 — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Boost Mode Typical Characteristics
Unless otherwise specified, using circuit of Figure 1, VBAT=3.6 V, TA=25°C.
VBUS
IL
IBAT
Figure 29. Startup, 3.6 VBAT, 44  Load, Additional 10 µF,
X5R Across VBUS
Figure 30. VBUS Fault Response, 3.6 VBAT
Figure 31. Load Transient, 5-155-5 mA, tR=tF=100 ns
Figure 32. Load Transient, 5-255-5 mA, tR=tF=100 ns
© 2012 Fairchild Semiconductor Corporation
FAN54015 • Rev. 1.0.2
www.fairchildsemi.com
15
FAN54015 — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Boost Mode Typical Characteristics
When charging batteries with a current-limited input source,
such as USB, a switching charger’s high efficiency over a
wide range of output voltages minimizes charging time.
The FAN54015 is designed to work with a current-limited
input source at VBUS. During the current regulation phase
of charging, IINLIM or the programmed charging current
limits the amount of current available to charge the battery
and power the system. The effect of I INLIM on ICHARGE can be
seen in Figure 34.
FAN54015 combines a highly integrated synchronous buck
regulator for charging with a synchronous boost regulator,
which can supply 5 V to USB On-The-Go (OTG) peripherals.
The regulator employs synchronous rectification for both the
charger and boost regulators to maintain high efficiency over
a wide range of battery voltages and charge states.
VOREG
VOREG
ICHARGE
VB
The FAN54015 has three operating modes:
1.
Charge Mode:
Charges a single-cell Li-ion or Li-polymer battery.
2.
Boost Mode:
Provides 5 V power to USB-OTG with an integrated
synchronous rectification boost regulator using the
battery as input.
3.
AT
ITERM
VSHORT
VSHORT
ISHORT
ISHORT
High-Impedance Mode:
Both the boost and charging circuits are OFF in this
mode. Current flow from VBUS to the battery or from the
battery to VBUS is blocked in this mode. This mode
consumes very little current from VBUS or the battery.
PRECHARGE
CONSTANT CURRENT
(CC)
CONSTANT
VOLTAGE (CV)
Figure 33. Charge Curve, ICHARGE Not Limited by IINLIM
Note: Default settings are denoted by bold typeface.
VOREG
Charge Mode
In Charge Mode, FAN54015 employs four regulation loops:
1.
Input Current: Limits the amount of current drawn from
VBUS. This current is sensed internally and can be
programmed through the I2C interface.
2.
Charging Current: Limits the maximum charging current.
This current is sensed using an external RSENSE resistor.
3.
T
V BA
Temperature: If the IC’s junction temperature reaches
120°C, charge current is reduced until the IC’s
temperature stabilizes at 120°C.
5.
An additional loop limits the amount of drop on VBUS to
a programmable voltage (VSP) to accommodate “special
chargers” that limit current to a lower current than might
be available from a “normal” USB wall charger.
ISHORT
PRECHARGE
CURRENT REGULATION
VOLTAGE
REGULATION
Figure 34. Charge Curve, IINLIM Limits ICHARGE
Assuming that VOREG is programmed to the cell’s fully
charged “float” voltage, the current that the battery accepts
with the PWM regulator limiting its output (sensed at VBAT)
to VOREG declines, and the charger enters the voltage
regulation phase of charging. When the current declines to
the programmed ITERM value, the charge cycle is complete.
Charge current termination can be disabled by resetting the
TE bit (REG1[3]).
Battery Charging Curve
The charger output or “float” voltage can be programmed by
the OREG bits from 3.5 V to 4.44 V in 2 0mV increments, as
shown in Table 3.
If the battery voltage is below VSHORT, a linear current source
pre-charges the battery until VBAT reaches VSHORT. The PWM
charging circuit is then started and the battery is charged
with a constant current if sufficient input power is available.
The current slew rate is limited to prevent overshoot.
© 2012 Fairchild Semiconductor Corporation
FAN54015 • Rev. 1.0.2
HA R
GE
ITERM
VSHORT
Charge Voltage: The regulator is restricted from
exceeding this voltage. As the internal battery voltage
rises, the battery’s internal impedance and RSENSE work
in conjunction with the charge voltage regulation to
decrease the amount of current flowing to the battery.
Battery charging is completed when the voltage across
RSENSE drops below the ITERM threshold.
4.
IC
www.fairchildsemi.com
16
FAN54015 — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Circuit Description / Overview
A new charge cycle begins when one of the following occurs:

The battery voltage falls below VOREG - VRCH
Decimal Hex VOREG

VBUS Power on Reset (POR) clears and the battery
voltage is below the weak battery threshold (VLOWV).

2
CE or HZ_MODE is reset through I C write to
CONTROL1 (R1) register.
Decimal Hex VOREG
0
00
3.50
32
20
4.14
1
01
3.52
33
21
4.16
2
02
3.54
34
22
4.18
3
03
3.56
35
23
4.20
Charge Current Limit (IOCHARGE)
4
04
3.58
36
24
4.22
5
05
3.60
37
25
4.24
Table 5. IOCHARGE (REG4 [6:4]) Current as Function
of IOCHARGE Bits and RSENSE Resistor Values
6
06
3.62
38
26
4.26
7
07
3.64
39
27
4.28
8
08
3.66
40
28
4.30
9
09
3.68
41
29
10
0A
3.70
42
2A
VRSENSE IOCHARGE (mA)
(mV) 68 m 100 m
DEC
BIN
HEX
4.32
0
000
00
37.4
550
374
4.34
1
001
01
44.2
650
442
010
02
51.0
750
510
11
0B
3.72
43
2B
4.36
2
12
0C
3.74
44
2C
4.38
3
011
03
57.8
850
578
13
0D
3.76
45
2D
4.40
4
100
04
71.4
1050
714
14
0E
3.78
46
2E
4.42
5
101
05
78.2
1150
782
110
06
91.8
1350
918
111
07
98.6
1450
986
15
0F
3.80
47
2F
4.44
6
16
10
3.82
48
30
4.44
7
17
11
3.84
49
31
4.44
18
12
3.86
50
32
4.44
Termination Current Limit
19
13
3.88
51
33
4.44
20
14
3.90
52
34
4.44
Current charge termination is enabled when TE (REG1[3])=1.
Typical termination current values are given in Table 6.
21
15
3.92
53
35
4.44
22
16
3.94
54
36
4.44
23
17
3.96
55
37
4.44
24
18
3.98
56
38
4.44
25
19
4.00
57
39
4.44
26
1A
4.02
58
3A
4.44
27
1B
4.04
59
3B
4.44
28
1C
4.06
60
3C
4.44
29
1D
4.08
61
3D
4.44
30
1E
4.10
62
3E
4.44
Table 6. ITERM Current as Function of ITERM Bits
(REG4[2:0]) and RSENSE Resistor Values
The following charging parameters can be programmed by
the host through I2C:
Table 4. Programmable Charging Parameters
Parameter
Name
Register
Output Voltage Regulation
VOREG
REG2[7:2]
Battery Charging Current Limit
IOCHRG
REG4[6:4]
Input Current Limit
IINLIM
REG1[7:6]
Charge Termination Limit
ITERM
REG4[2:0]
Weak Battery Voltage
VLOWV
REG1[5:4]
© 2012 Fairchild Semiconductor Corporation
FAN54015 • Rev. 1.0.2
ITERM
VRSENSE (mV)
0
3.3
1
2
ITERM (mA)
68 m
100 m
49
33
6.6
97
66
9.9
146
99
3
13.2
194
132
4
16.5
243
165
5
19.8
291
198
6
23.1
340
231
7
26.4
388
264
When the charge current falls below ITERM, PWM charging
stops and the STAT bits change to READY (00) for about
500 ms while the IC determines whether the battery and
charging source are still connected. STAT then changes to
CHARGE DONE (10), provided the battery and charger are
still connected.
www.fairchildsemi.com
17
FAN54015 — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Table 3. OREG Bits (OREG[7:2]) vs. Charger VOUT
(VOREG) Float Voltage
USB-Friendly Boot Sequence
The IC uses a current-mode PWM controller to regulate the
output voltage and battery charge currents. The synchronous
rectifier (Q2) has a current limit that which off the FET when
the current is negative by more than 140mA peak. This
prevents current flow from the battery.
At VBUS POR, when the battery voltage is above the weak
battery threshold (VLOWV), the IC operates in accordance with
its I2C register settings. If VBAT < VLOWV, the IC sets all
registers to their default values and enables the charger
using an input current limit controlled by the OTG pin
(100mA if OTG is LOW and 500 mA if OTG is HIGH). This
feature can revive a battery whose voltage is too low to
ensure reliable host operation. Charging continues in the
absence of host communication even after the battery has
reached VOREG, whose default value is 3.54 V, and the
charger remains active until t15MIN times out. Once the host
processor begins writing to the IC, charging parameters are
set by the host, which must continually reset the t32S timer to
continue charging using the programmed charging
parameters. If t32S.times out, the register defaults are loaded,
the FAULT bits are set to 110, STAT is pulsed HIGH, and
charging continues with default charge parameters.
Safety Timer
Section references Figure 39.
At the beginning of charging, the IC starts a 15-minute timer
(t15MIN ). When this times out, charging is terminated. Writing
to any register through I2C stops and resets the t15MIN timer,
which in turn starts a 32-second timer (t32S). Setting the
TMR_RST bit (REG0[7]) resets the t32S timer. If the t32S timer
times out; charging is terminated, the registers are set to
their default values, and charging resumes using the default
values with the t15MIN timer running.
Normal charging is controlled by the host with the t32S timer
running to ensure that the host is alive. Charging with the
t15MIN timer running is used for charging that is unattended by
the host. If the t15MIN timer expires; the IC turns off the
charger, sets the CE bit, and indicates a timer fault (110) on
the FAULT bits (REG0[2:0]). This sequence prevents
overcharge if the host fails to reset the t32S timer.
Input Current Limiting
To minimize charging time without overloading VBUS current
limitations, the IC’s input current limit can be programmed by
the IINLIM bits (REG1[7:6]).
Table 7. Input Current Limit
VBUS POR / Non-Compliant Charger Rejection
When the IC detects that VBUS has risen above VIN(MIN)1
(4.4 V), the IC applies a 100  load from VBUS to GND. To
clear the VBUS POR (Power-On-Reset) and begin charging,
VBUS must remain above VIN(MIN)1 and below VBUSOVP for
tVBUS_VALID (30 ms) before the IC initiates charging. The
VBUS validation sequence always occurs before charging is
initiated or re-initiated (for example, after a VBUS OVP fault
or a VRCH recharge initiation).
IINLIM REG1[7:6]
Input Current Limit
00
100 mA
01
500 mA
10
800 mA
11
No limit
The OTG pin establishes the input current limit when t15MIN is
running.
tVBUS_VALID ensures that unfiltered 50 / 60 Hz chargers and
other non-compliant chargers are rejected.
© 2012 Fairchild Semiconductor Corporation
FAN54015 • Rev. 1.0.2
www.fairchildsemi.com
18
FAN54015 — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
PWM Controller in Charge Mode
FAN54015 — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Flow Charts
VBUS POR
YES
CE or
HZ, CE#
DISABLE Pin
set?
YES
VBAT > VLOWV
HZ State
NO
NO
Charge
Configuration
State
NO
NO
T15Min Timer?
CE or
HZ, CE#
DISABLE Pin
set?
YES
NO
T32Sec
Armed?
YES
YES
CE or
HZ, CE#
DISABLE Pin
set?
YES
NO
HZ State
T32Sec
Armed?
YES
NO
Charge State
Reset all registers
Start T15MIN
Figure 35. Charger VBUS POR
© 2012 Fairchild Semiconductor Corporation
FAN54015 • Rev. 1.0.2
www.fairchildsemi.com
19
CHARGE STATE
Disable Charging
NO
Indicate
VBUS Fault
VBAT < VSHORT
Enable ISHORT ,
Reset Safety reg
YES
VBUS OK?
NO
Indicate Charging
NO
YES
PWM Charging
VBUS OK?
T15MIN
Timeout?
YES
Indicate Charging
NO
YES
Disable Charging
T15MIN
Timeout?
Indicate
VBUS Fault
Indicate timer fault
YES
Set CE
Charge
Configuration
State
NO
NO
HIGHZ mode
NO
IOUT < ITERM
Termination enabled
VBAT > VOREG–VRCH
VBAT < VOREG–VRCH
Indicate Charge
Complete
YES
Reset Safety reg
Delay tINT
NO
YES
Battery Removed
Stop Charging
VBAT < VOREG–VRCH
Enable IDET for TDETECT
YES
Reset charge
parameters
Figure 36. Charge Mode
© 2012 Fairchild Semiconductor Corporation
FAN54015 • Rev. 1.0.2
www.fairchildsemi.com
20
FAN54015 — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Flow Charts (Continued)
FAN54015 — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Flow Charts (Continued)
Charge
Configuration
State
T32Sec
ARMED AND
CE = 0?
CE#
YES
Charge State
NO
Has T15Min
CE = 0
and CE#
NO
START T15Min
YES
VBAT < VOREG
for 262ms?
NO
YES
Figure 37. Charge Configuration
HZ State
DISABLE
PIN
HIGH
Reset T15min
if running
LOW
Stop T32Sec
RUN
T32Sec
NO
HZ or CE#
CE set?
HIGH
YES
VBAT > VLOWV?
YES
NO
DISABLE
PIN
LOW
Charge State
Figure 38. HZ-State
© 2012 Fairchild Semiconductor Corporation
FAN54015 • Rev. 1.0.2
www.fairchildsemi.com
21
Charge Start
Start T15MIN
Reset Registers
YES
T32SEC
NO
Expired?
Start T32SEC
Stop T15MIN
T15MIN
Active?
YES
YES
NO
I2C Write
received?
NO
Timer Fault :
Set CE
CE
T15MIN
Expired?
NO
Continue
Charging
YES
Figure 39. Timer Flow Chart
© 2012 Fairchild Semiconductor Corporation
FAN54015 • Rev. 1.0.2
www.fairchildsemi.com
22
FAN54015 — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Flow Charts (Continued)
The FAN54015 has additional functionality to limit input
current in case a current-limited “special charger” is
supplying VBUS. These slowly increase the charging current
until either:

ISAFE (REG6[6:4])
DEC
IINLIM or IOCHARGE is reached
or

VBUS=VSP.
BIN
HEX
VRSENSE (mV)
ISAFE (mA)
68 m 100 m
0
000
00
37.4
550
374
1
001
01
44.2
650
442
If VBUS collapses to VSP when the current is ramping up, the
FAN54015 charge with an input current that keeps
VBUS=VSP. When the VSP control loop is limiting the charge
current, the SP bit (REG5[4]) is set.
2
010
02
51.0
750
510
3
011
03
57.8
850
578
4
100
04
71.4
1050
714
Table 8. VSP as Function of SP Bits (REG5[2:0])
5
101
05
78.2
1150
782
6
110
06
91.8
1350
918
7
111
07
98.6
1450
986
SP (REG5[2:0])
DEC
BIN
HEX
VSP
0
000
00
4.213
1
001
01
4.293
2
010
02
4.373
3
011
03
4.453
4
100
04
4.533
5
101
05
4.613
6
110
06
4.693
7
111
07
4.773
Table 10. VSAFE (VOREG Limit) as Function of VSAFE
Bits (REG6[3:0])
VSAFE (REG6[3:0])
Safety Settings
DEC
BIN
HEX
Max. OREG
(REG2[7:2])
VOREG
Max.
0
0000
00
100011
4.20
1
0001
01
100100
4.22
2
0010
02
100101
4.24
3
0011
03
100110
4.26
4
0100
04
100111
4.28
FAN54015 contain a SAFETY register (REG6) that prevents
the values in OREG (REG2[7:2]) and IOCHARGE
(REG4[6:4]) from exceeding the values of the VSAFE and
ISAFE values.
5
0101
05
101000
4.30
6
0110
06
101001
4.32
7
0111
07
101010
4.34
After VBAT exceeds VSHORT, the SAFETY register is loaded
with its default value and may be written only before any
other register is written. The entire desired Safety register
value should be written twice to ensure the register bits are
set. After writing to any other register, the SAFETY register
is locked until VBAT falls below VSHORT.
8
1000
08
101011
4.36
9
1001
09
101100
4.38
10
1010
0A
101101
4.40
11
1011
0B
101110
4.42
12
1100
0C
101111
4.44
13
1101
0D
110000
4.44
14
1110
0E
110001
4.44
15
1111
0F
110010
4.44
The ISAFE (REG6[6:4]) and VSAFE (REG6[3:0]) registers
establish values that limit the maximum values of IOCHARGE
and VOREG used by the control logic. If the host attempts to
write a value higher than VSAFE or ISAFE to OREG or
IOCHARGE, respectively; the VSAFE, ISAFE value appears
as the OREG, IOCHARGE register value, respectively.
Thermal Regulation and Protection
When the IC’s junction temperature reaches T CF (about
120°C), the charger reduces its output current to 550 mA to
prevent overheating. If the temperature increases beyond
TSHUTDOWN; charging is suspended, the FAULT bits are set
to 101, and STAT is pulsed HIGH. In Suspend Mode, all
timers stop and the state of the IC’s logic is preserved.
Charging resumes at programmed current after the die
cools to about 120°C.
© 2012 Fairchild Semiconductor Corporation
FAN54015 • Rev. 1.0.2
www.fairchildsemi.com
23
FAN54015 — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Table 9. ISAFE (IOCHARGE Limit) as Function of ISAFE
Bits (REG6[6:4])
Special Charger
Battery Detection During Charging
The IC can detect the presence, absence, or removal of a
battery if the termination bit (TE) is set. During normal
charging, once VBAT is close to VOREG and the termination
charge current is detected, the IC terminates charging and
sets the STAT bits to 10. It then turns on a discharge current,
IDETECT, for tDETECT. If VBAT is still above VOREG – VRCH, the
battery is present and the IC sets the FAULT bits to 000. If
VBAT is below VOREG – VRCH, the battery is absent and the IC:
1. Sets the registers to their default values.
2. Sets the FAULT bits to 111.
3. Resumes charging with default values after tINT.
Table 11. Evaluation Board Measured JA
Power (W)
JA
0.504
54°C/W
0.844
50°C/W
1.506
46°C/W
Battery Short-Circuit Protection
If the battery voltage is below the short-circuit threshold
(VSHORT); a linear current source, ISHORT, supplies VBAT until
VBAT > VSHORT.
Charge Mode Input Supply Protection
Sleep Mode
When VBUS falls below VBAT + VSLP, and VBUS is above
VIN(MIN), the IC enters Sleep Mode to prevent the battery from
draining into VBUS. During Sleep Mode, reverse current is
disabled by body switching Q1.
System Operation with No Battery
The FAN54015 continues charging after VBUS POR with the
default parameters, regulating the VBAT line to 3.54 V until
the host processor issues commands or the 15-minute timer
expires. In this way, the FAN54015 can start the system
without a battery.
The FAN54015 soft-start function can interfere with the
system supply with battery absent. The soft-start activates
whenever VOREG, IINLIM, or IOCHARGE are set from a lower to
higher value. During soft-start, the IIN limit drops to 100 mA
for about 1ms unless IINLIM is set to 11 (no limit). This could
cause the system processor to fail to start. To avoid this
behavior, use the following sequence.
1. Set the OTG pin HIGH. When VBUS is plugged in, IINLIM
is set to 500 mA until the system processor powers up
and can set parameters through I2C.
2. Program the Safety Register.
3. Set IINLIM to 11 (no limit).
4. Set OREG to the desired value (typically 4.18).
5. Reset the IO_LEVEL bit, then set IOCHARGE.
6. Set IINLIM to 500mA if a USB source is connected.
Input Supply Low-Voltage Detection
The IC continuously monitors VBUS during charging. If VBUS
falls below VIN(MIN), the IC:
1. Terminates charging
2. Pulses the STAT pin, sets the STAT bits to 11, and sets
the FAULT bits to 011.
If VBUS recovers above the VIN(MIN) rising threshold after time
tINT (about two seconds), the charging process is repeated.
This function prevents the USB power bus from collapsing or
oscillating when the IC is connected to a suspended USB
port or a low-current-capable OTG device.
Input Over-Voltage Detection
When the VBUS exceeds VBUSOVP, the IC:
1. Turns off Q3
2. Suspends charging
3. Sets the FAULT bits to 001, sets the STAT bits to 11,
and pulses the STAT pin.
When VBUS falls about 150 mV below VBUSOVP, the fault is
cleared and charging resumes after VBUS is revalidated (see
VBUS POR / Non-Compliant Charger Rejection).
During the initial system startup, while the charger IC is
being programmed, the system current is limited to 500mA
for 1ms during steps 4 and 5. This is the value of the softstart ICHARGE current used when IINLIM is set to No Limit.
VBUS Short While Charging
If VBUS is shorted with a very low impedance while the IC is
charging with IINLIMIT=100 mA, the IC may not meet
datasheet specifications until power is removed. To trigger
this condition, VBUS must be driven from 5 V to GND with a
high slew rate. Achieving this slew rate requires a 0  short
to the USB cable less than 10cm from the connector.
If the system is powered up without a battery present, the
CV bit should be set. When a battery is inserted, the CV bit
is cleared.
Charger Status / Fault Status
The STAT pin indicates the operating condition of the IC and
provides a fault indicator for interrupt driven systems.
Charge Mode Battery Detection & Protection
VBAT Over-Voltage Protection
The OREG voltage regulation loop prevents VBAT from
overshooting the OREG voltage by more than 50 mV when
the battery is removed. When the PWM charger runs with no
battery, the TE bit is not set and a battery is inserted that is
charged to a voltage higher than VOREG; PWM pulses stop. If
no further pulses occur for 30 ms, the IC sets the FAULT bits
to 100, sets the STAT bits to 11, and pulses the STAT pin.
© 2012 Fairchild Semiconductor Corporation
FAN54015 • Rev. 1.0.2
Table 12. STAT Pin Function
EN_STAT
Charge State
STAT Pin
0
X
OPEN
X
Normal Conditions
OPEN
1
Charging
LOW
X
Fault (Charging or Boost)
128s Pulse,
then OPEN
www.fairchildsemi.com
24
FAN54015 — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Additional JA data points, measured using the FAN54015
evaluation board, are given in Table 11 (measured with
TA=25°C). Note that as power dissipation increases, the
effective JA decreases due to the larger difference between
the die temperature and ambient.
Table 15. Operation Mode Control
HZ_MODE OPA_MODE FAULT Operation Mode
Table 13. Fault Status Bits During Charge Mode
Fault Bit
Fault Description
B2
B1
B0
0
0
0
Normal (No Fault)
0
0
1
VBUS OVP
0
1
0
Sleep Mode
0
1
1
Poor Input Source
1
0
0
Battery OVP
1
0
1
Thermal Shutdown
1
1
0
Timer Fault
1
1
1
No Battery
0
0
0
Charge
0
X
1
Charge Configure
0
1
0
Boost
1
X
X
High Impedance
The IC resets the OPA_MODE bit whenever the boost is
deactivated, whether due to a fault or being disabled by
setting the HZ_MODE bit.
Boost Mode
Boost Mode can be enabled if the IC is in 32-Second Mode
with the OTG pin and OPA_MODE bits as indicated in Table
16. The OTG pin ACTIVE state is 1 if OTG_PL=1 and 0
when OTG_PL=0.
If boost is active using the OTG pin, Boost Mode is initiated
even if the HZ_MODE=1. The HZ_MODE bit overrides the
OPA_MODE bit.
Charge Mode Control Bits
Setting either HZ_MODE or CE through I2C disables the
charger and puts the IC into High-Impedance Mode and
resets t32S. If VBAT < VLOWV while in High-Impedance Mode,
t32S begins running and, when it overflows, all registers
(except SAFETY) reset, which enables t15MIN charging on
versions with the 15-minute timer.
Table 16. Enabling Boost
When t15MIN overflows, the IC sets the CE bit and the IC
enters High-Impedance Mode. If CE was set by t15MIN
overflow, a new charge cycle can only be initiated through
I2C or VBUS POR.
Setting the RESET bit clears all registers. If HZ_MODE or
CE bits were set when the RESET bit is set, these bits are
also cleared, but the t32S timer is not started, and the IC
remains in High-Impedance Mode.
DISABLE Pin
CE
HZ_MODE
ENABLE
0
0
0
DISABLE
X
1
X
DISABLE
X
X
1
DISABLE
1
X
X
OTG
Pin
HZ_
MODE
OPA_
MODE
BOOST
1
ACTIVE
X
X
Enabled
X
X
0
1
Enabled
X
ACTIVE
X
0
Disabled
0
X
1
X
Disabled
1
ACTIVE
1
1
Disabled
0
ACTIVE
0
0
Disabled
To remain in Boost Mode, the TMR_RST must be set by the
host before the t32S timer times out. If t32S times out in Boost
Mode; the IC resets all registers, pulses the STAT pin, sets
the FAULT bits to 110, and resets the BOOST bit. VBUS
POR or reading R0 clears the fault condition.
Table 14. DISABLE Pin and CE Bit Functionality
Charging
OTG_EN
Boost PWM Control
Raising the DISABLE pin stops t32S from advancing, but
does not reset it. If the DISABLE pin is raised during t15MIN
charging, the t15MIN timer is reset.
The IC uses a minimum on-time and computed minimum offtime to regulate VBUS. The regulator achieves excellent
transient response by employing current-mode modulation.
This technique causes the regulator to exhibit a load line.
During PWM Mode, the output voltage drops slightly as the
input current rises. With a constant VBAT, this appears as a
constant output resistance.
Operational Mode Control
OPA_MODE (REG1[0]) and the HZ_MODE (REG1[1]) bits in
conjunction with the FAULT state define the operational
mode of the charger.
The “droop” caused by the output resistance when a load is
applied allows the regulator to respond smoothly to load
transients with no undershoot from the load line. This can be
seen in Figure 31 and Figure 40.
© 2012 Fairchild Semiconductor Corporation
FAN54015 • Rev. 1.0.2
www.fairchildsemi.com
25
FAN54015 — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
The FAULT bits (R0[2:0]) indicate the type of fault in Charge
Mode (see Table 13).
When PMID > VBAT – 400 mV, the boost regulator begins
switching with a reduced peak current limit of about 50% of
its normal current limit. The output slews up until VBUS is
within 5% of its setpoint; at which time, the regulation loop is
closed and the current limit is set to 100%.
Output Resistance (mW)
325
300
275
If the output fails to achieve 95% of its setpoint (VBST) within
128 s, the current limit is increased to 100%. If the output
fails to achieve 95% of its setpoint after this second 384s
period, a fault state is initiated.
250
225
BST State
200
2.0
2.5
3.0
3.5
4.0
4.5
5.0
This is the normal operating mode of the regulator. The
regulator uses a minimum tOFF-minimum tON modulation
Battery Voltage, VBAT (V)
Figure 40. Output Resistance (ROUT)
scheme. The minimum tOFF is proportional to
keeps the regulator’s switching frequency reasonably
constant in CCM. tON(MIN) is proportional to VBAT and is a
higher value if the inductor current reached 0 before tOFF(MIN)
in the prior cycle.
VBUS as a function of ILOAD can be computed when the
regulator is in PWM Mode (continuous conduction) as:
VOUT  5.07  ROUT  ILOAD
EQ. 1
To ensure the VBUS does not pump significantly above the
regulation point, the boost switch remains off as long as
FB > VREF.
At VBAT=3.3 V, and ILOAD=200 mA, VBUS would drop to:
VOUT  5.07  0.26  0.2  5.018V
EQ. 1A
Boost Faults
At VBAT=2.7 V, and ILOAD=200 mA, VBUS would drop to:
VOUT  5.07  0.327  0.2  5.005V
If a BOOST fault occurs:
1. The STAT pin pulses.
2. OPA_MODE bit is reset.
3. The power stage is in High-Impedance Mode.
4. The FAULT bits (REG0[2:0]) are set per Table 18.
EQ. 1B
PFM Mode
If VBUS > VREFBOOST (nominally 5.07 V) when the minimum
off-time has ended, the regulator enters PFM Mode. Boost
pulses are inhibited until VBUS < VREFBOOST. The minimum
on-time is increased to enable the output to pump up
sufficiently with each PFM boost pulse. Therefore the
regulator behaves like a constant on-time regulator, with the
bottom of its output voltage ripple at 5.07 V in PFM Mode.
Restart After Boost Faults
If boost was enabled with the OPA_MODE bit and
OTG_EN=0, Boost Mode can only be enabled through
subsequent I2C commands since OPA_MODE is reset on
boost faults. If OTG_EN=1 and the OTG pin is still ACTIVE
(see Table 16), the boost restarts after a 5.2 ms delay, as
shown in Figure 41. If the fault condition persists, restart is
attempted every 5ms until the fault clears or an I2C
command disables the boost.
Table 17. Boost PWM Operating States
Mode
Description
Invoked When
LIN
Linear Startup
VBAT > VBUS
SS
Boost Soft-Start
VBUS < VBST
Boost Operating Mode
VBAT > UVLOBST and
SS Completed
BST
VIN , which
VOUT
Table 18. Fault Bits During Boost Mode
Fault Bit
B2 B1 B0
Fault Description
Startup
0
0
0
Normal (no fault)
When the boost regulator is shut down, current flow is
prevented from VBAT to VBUS, as well as reverse flow from
VBUS to VBAT.
0
0
1
VBUS > VBUSOVP
LIN State
0
1
0
VBUS fails to achieve the voltage required to
advance to the next state during soft-start
or sustained (>50 s) current limit during the
BST state.
0
1
1
VBAT < UVLOBST
1
0
0
N/A: This code does not appear.
1
0
1
Thermal shutdown
1
1
0
Timer fault; all registers reset.
1
1
1
N/A: This code does not appear.
When EN rises, if VBAT > UVLOBST, the regulator first
attempts to bring PMID within 400 mV of VBAT using an
internal 450 mA current source from VBAT (LIN State). If
PMID has not achieved VBAT – 400 mV after 560 s, a
FAULT state is initiated.
© 2012 Fairchild Semiconductor Corporation
FAN54015 • Rev. 1.0.2
www.fairchildsemi.com
26
FAN54015 — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
SS State
350
560
5200
450mA
BATTERY
CURRENT
0
Monitor Register (Reg10H)
64
BOOST
ENABLED
Additional status monitoring bits enable the host processor
to have more visibility into the status of the IC. The monitor
bits are real-time status indicators and are not internally
debounced or otherwise time qualified.
Figure 41. Boost Response Attempting to Start into VBUS
Short Circuit (Times in s)
VREG Pin
The state of the MONITOR register bits listed in HighImpedance Mode is only valid when VBUS is valid.
The 1.8 V regulated output on this pin can be disabled
through I2C by setting the DIS_VREG bit (REG5[6]). VREG
Table 19. MONITOR Register Bit Definitions
BIT#
MONITOR
7
STATE
NAME
0
1
Active When
Address 10H
ITERM_CMP
VCSIN – VBAT < VITERM
VCSIN – VBAT > VITERM
Charging with TE=1
VCSIN – VBAT < 1 mV
VCSIN – VBAT > 1mV
Charging with TE=0
VBAT < VSHORT
VBAT > VSHORT
Charging
VBAT < VLOWV
VBAT > VLOWV
High-Impedance Mode
6
VBAT_CMP
VBAT < UVLOBST
VBAT > UVLOBST
Boosting
5
LINCHG
Linear Charging Not Enabled
Linear Charging Enabled
Charging
4
T_120
TJ < 120°C
TJ > 120°C
3
ICHG
Charging Current Controlled by
ICHARGE Control Loop
Charging Current Not Controlled by
ICHARGE Control Loop
Charging
2
IBUS
IBUS Limiting Charging Current
Charge Current Not Limited by IBUS
Charging
1
VBUS_VALID
VBUS Not Valid
VBUS is Valid
VBUS > VBAT
0
CV
Constant Current Charging
Constant Voltage Charging
Charging
© 2012 Fairchild Semiconductor Corporation
FAN54015 • Rev. 1.0.2
www.fairchildsemi.com
27
FAN54015 — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
can supply up to 2 mA. This circuit, which is powered from
PMID, is enabled only when PMID > VBAT and does not drain
current from the battery. During boost, VREG is off. It is also
off when the HZ_MODE bit (REG1[1])=1.
VBUS 0
The FAN54015’s serial interface is compatible with
Standard, Fast, Fast Plus, and High-Speed Mode I2C-Bus®
specifications. The SCL line is an input and the SDA line is a
bi-directional open-drain output; it can only pull down the bus
when active. The SDA line only pulls LOW during data reads
and signaling ACK. All data is shifted in MSB (bit 7) first.
During a read from the FAN54015 (Figure 46, Figure 47), the
master issues a Repeated Start after sending the register
address and before resending the slave address. The
Repeated Start is a 1-to-0 transition on SDA while SCL is
HIGH, as shown in Figure 45.
High-Speed (HS) Mode
Slave Address
The protocols for High-Speed (HS), Low-Speed (LS), and
Fast-Speed (FS) Modes are identical except the bus speed for
HS Mode is 3.4 MHz. HS Mode is entered when the bus
master sends the HS master code 00001XXX after a start
condition. The master code is sent in Fast or Fast Plus Mode
(less than 1 MHz clock); slaves do not ACK this transmission.
Table 20. I2C Slave Address Byte
Part Type
7
6
5
4
3
2
1
0
FAN54015
1
1
0
1
0
1
0
R/ W
In hex notation, the slave address assumes a 0 LSB. The
hex slave address for the FAN54015 is D4H and is D6H for
all other parts in the family.
The master then generates a repeated start condition
(Figure 45) that causes all slaves on the bus to switch to HS
Mode. The master then sends I2C packets, as described
above, using the HS Mode clock rate and timing.
Bus Timing
As shown in Figure 42, data is normally transferred when
SCL is LOW. Data is clocked in on the rising edge of SCL.
Typically, data transitions shortly at or after the falling edge
of SCL to allow ample time for the data to set up before the
next SCL rising edge.
The bus remains in HS Mode until a stop bit (Figure 44) is
sent by the master. While in HS Mode, packets are
separated by repeated start conditions (Figure 45).
Slave Releases
SDA
Data change allowed
SDA
SLADDR
MS Bit
Figure 45. Repeated Start Timing
TSU
SCL
Figure 42. Data Transfer Timing
Each bus transaction begins and ends with SDA and SCL
HIGH. A transaction begins with a START condition, which is
defined as SDA transitioning from 1 to 0 with SCL HIGH, as
shown in Figure 43.
THD;STA
Read and Write Transactions
The figures below outline the sequences for data read and
write. Bus control is signified by the shading of the packet,
Master Drives Bus
defined as
and
All addresses and data are MSB first.
Slave Address
MS Bit
Slave Drives Bus
.
Table 21. Bit Definitions for Figure 46, Figure 47,
and Figure 48
SCL
Symbol
Figure 43. Start Bit
A transaction ends with a STOP condition, which is defined
as SDA transitioning from 0 to 1 with SCL HIGH, as shown
in Figure 44.
Slave Releases
SDA
tHD;STA
SCL
TH
SDA
tSU;STA
ACK(0) or
NACK(1)
Master Drives
tHD;STO
ACK(0) or
NACK(1)
Definition
S
START, see Figure 43
A
ACK. The slave drives SDA to 0 to acknowledge
the preceding packet.
A
NACK. The slave sends a 1 to NACK the
preceding packet.
R
Repeated START, see Figure 45
P
STOP, see Figure 44. Figure 44
SCL
Figure 44. Stop Bit
© 2012 Fairchild Semiconductor Corporation
FAN54015 • Rev. 1.0.2
www.fairchildsemi.com
28
FAN54015 — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
I2C Interface
S
Slave Address
0
0
8 bits
0
8 bits
0
A
Reg Addr
A
Data
A
P
Figure 46. Write Transaction
7 bits
S
Slave Address
0
0
8 bits
0
A
Reg Addr
A
7 bits
R
Slave Address
1
0
8 bits
1
A
Data
A
P
Figure 47. Read Transaction
Register Descriptions
The nine FAN54015 user-accessible registers are defined in Table 22.
Table 22. I2C Register Address
Register
Address Bits
Name
REG#
7
6
5
4
3
2
1
0
CONTROL0
0
0
0
0
0
0
0
0
0
CONTROL1
1
0
0
0
0
0
0
0
1
OREG
2
0
0
0
0
0
0
1
0
IC_INFO
03
or
3BH
0
0
0
0
0
0
1
1
IBAT
4
0
0
0
0
0
1
0
0
SP_CHARGER
5
0
0
0
0
0
1
0
1
SAFETY
6
0
0
0
0
0
1
1
0
MONITOR
10h
0
0
0
0
1
0
1
0
Table 23. Register Bit Definitions
This table defines the operation of each register bit for all IC versions. Default values are in bold text.
Bit
Name
Value
Type
CONTROL0
7
6
TMR_RST
OTG
EN_STAT
Register Address: 00
1
0
STAT
Writing a 1 resets the t32S timer; writing a 0 has no effect
R
Returns the OTG pin level (1=HIGH)
R/W
Enables STAT pin LOW when IC is charging
R
BOOST
2:0
FAULT
Ready
Charge in progress
10
Charge done
11
3
Prevents STAT pin from going LOW during charging; STAT pin still pulses to
enunciate faults
01
0
Default Value=X1XX 0XXX
W
1
00
5:4
Description
Fault
R
1
IC is not in Boost Mode
IC is in Boost Mode
R
Fault status bits: for Charge Mode, see Table 13; for Boost Mode, see Table 18
Continued on the following page…
© 2012 Fairchild Semiconductor Corporation
FAN54015 • Rev. 1.0.2
www.fairchildsemi.com
29
FAN54015 — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
7 bits
Bit
Name
Value
Type
CONTROL1
7:6
Register Address: 01
IINLIM
00
5:4
VLOWV
R/W
Input current limit, see Table 7
R/W
3.4V
01
3.5V
10
3.6V
11
3.7V
R/W
Disable charge current termination
TE
1
0
2
CE
Enable charge current termination
R/W
1
0
1
Charger enabled
Charger disabled
R/W
Not High-Impedance Mode
HZ_MODE
1
0
0
Default Value=0011 0000 (30h)
Weak battery voltage threshold
0
3
Description
High-Impedance Mode
R/W
See Table 16
Charge Mode
OPA_MODE
1
Boost Mode
OREG
Register Address: 02
7:2
OREG
1
OTG_PL
0
R/W
Charger output “float” voltage; programmable from 3.5 to 4.44V in 20mV
increments; defaults to 000010 (3.54V), see Table 3
R/W
OTG pin active LOW
1
0
0
Default Value=0000 1010 (0Ah)
OTG pin active HIGH
R/W
Disables OTG pin
OTG_EN
1
Enables OTG pin
IC_INFO
Register Address: 03
7:5
Vendor Code
4:2
PN
1:0
REV
100
00
Default Value=10010100 (94h)
R
Identifies Fairchild Semiconductor as the IC supplier
R
Part number bits, see the Ordering Info on page 2
R
IC Revision, revision 1.X, where X is the decimal of these three bits
IBAT
Register Address: 04
7
RESET
1
W
6:4
IOCHARGE
Table 5
R/W
3
Reserved
1
R
2:0
ITERM
Table 6
R/W
Default Value=1000 1001 (89h)
Writing a 1 resets charge parameters, except the Safety register (Reg6), to their
defaults: writing a 0 has no effect; read returns 1
Programs the maximum charge current, see Table 5
Unused
Sets the current used for charging termination, see Table 6
Continued on the following page…
© 2012 Fairchild Semiconductor Corporation
FAN54015 • Rev. 1.0.2
www.fairchildsemi.com
30
FAN54015 — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Table 23. Register Bit Definitions (Continued)
SP_CHARGER
7
Reserved
6
DIS_VREG
Register Address: 05
0
R
0
R/W
1
0
5
IO_LEVEL
4
SP
3
EN_LEVEL
2:0
VSP
R
Output current is controlled by IOCHARGE bits
Special charger is not active (VBUS is able to stay above VSP)
Special charger has been detected and VBUS is being regulated to VSP
R
1
Table 8
1.8V regulator is ON
Voltage across RSENSE for output current control is set to 34mV (500mA for
RSENSE=68m and 340mA for 100m)
1
0
Unused
1.8V regulator is OFF
R/W
1
0
Default Value=001X X100
DISABLE pin is LOW
DISABLE pin is HIGH
R/W
SAFETY
Special charger input regulation voltage, see Table 8
Register Address: 06
Default Value=0100 0000 (40h)
7
Reserved
0
R
6:4
ISAFE
Table 9
R/W
Sets the maximum IOCHARGE value used by the control circuit, see Table 9
3:0
VSAFE
Table 10
R/W
Sets the maximum VOREG used by the control circuit, see Table 10
MONITOR
Bit disabled and always returns 0 when read back
Register Address: 10h (16)
See Table 19
7
ITERM_CMP
R
ITERM comparator output, 1 when VRSENSE > ITERM reference
6
VBAT_CMP
R
Output of VBAT comparator
5
LINCHG
R
30mA linear charger ON
4
T_120
R
Thermal regulation comparator; when=1 and T_145=0, the charge current is limited
to 22.1 mV across RSENSE
3
ICHG
R
0 indicates the ICHARGE loop is controlling the battery charge current
See
Table 19
2
IBUS
R
0 indicates the IBUS (input current) loop is controlling the battery charge current
1
VBUS_VALID
R
1 indicates VBUS has passed validation and is capable of charging
0
CV
R
1 indicates the constant-voltage loop (OREG) is controlling the charger and all
current limiting loops have released
© 2012 Fairchild Semiconductor Corporation
FAN54015 • Rev. 1.0.2
www.fairchildsemi.com
31
FAN54015 — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Table 23. Register Bit Definitions (Continued)
Bypass capacitors should be placed as close to the IC as
possible. In particular, the total loop length for CMID should
be minimized to reduce overshoot and ringing on the SW,
PMID, and VBUS pins. All power and ground pins must be
routed to their bypass capacitors, using top copper whenever
possible. Copper area connecting to the IC should be
maximized to improve thermal performance if possible.
Figure 48. PCB Layout Recommendations
© 2012 Fairchild Semiconductor Corporation
FAN54015 • Rev. 1.0.2
www.fairchildsemi.com
32
FAN54015 — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
PCB Layout Recommendations
BALL A1
INDEX AREA
F
A
E
1.20
B
1.20
Ø0.20
A1
Cu Pad
0.03 C
2X
1.60
D
Ø0.215
Cu Pad
A1
Ø0.30 Solder
Mask Opening
0.40
Ø0.315 Solder
Mask Opening
0.40
0.03 C
0.40
option 1
2X
TOP VIEW
option 2
RECOMMENDED LAND PATTERN
(NSMD TYPE)
0.06 C
0.625
0.547
0.05 C
0.378±0.018
0.208±0.021
E
C
SEATING PLANE
SIDE VIEWS
D
NOTES:
0.005
1.20
A. NO JEDEC REGISTRATION APPLIES.
C A B
B. DIMENSIONS ARE IN MILLIMETERS.
Ø0.260±0.02
20X
0.40
E
D
C
B
A
1.60
0.40
C. DIMENSIONS AND TOLERANCE
PER ASMEY14.5M, 1994.
D. DATUM C IS DEFINED BY THE SPHERICAL
CROWNS OF THE BALLS.
(Y) ±0.018
E. PACKAGE NOMINAL HEIGHT IS 586 MICRONS
±39 MICRONS (547-625 MICRONS).
F
1 2 3 4
(X) ±0.018
F. FOR DIMENSIONS D, E, X, AND Y SEE
PRODUCT DATASHEET.
BOTTOM VIEW
G. DRAWING FILNAME: MKT-UC020AArev3.
Figure 49. 20-Ball WLCSP, 4X5 Array, 0.4 mm Pitch, 250 µm Ball
Product-Specific Dimensions
Product
D
E
X
Y
FAN54015UCX
1.960 +0.030 mm
1.870 +0.030 mm
0.335 mm
0.180 mm
FAN54015BUCX
1.960 +0.030 mm
1.870 +0.030 mm
0.335 mm
0.180 mm
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without
notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most
recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty
therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/dwg/UC/UC020AA.pdf.
© 2012 Fairchild Semiconductor Corporation
FAN54015 • Rev. 1.0.2
www.fairchildsemi.com
33
FAN54015 — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Physical Dimensions
FAN54015 — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
34
www.fairchildsemi.com
© 2012 Fairchild Semiconductor Corporation
FAN54015 • Rev. 1.0.2