74VCX00 Low Voltage Quad 2-Input NAND Gate with 3.6V Tolerant Inputs and Outputs Features General Description ■ 1.2V to 3.6V VCC supply operation The VCX00 contains four 2-input NAND gates. This product is designed for low voltage (1.2V to 3.6V) VCC applications with I/O compatibility up to 3.6V. ■ 3.6V tolerant inputs and outputs ■ tPD – 2.8ns max. for 3.0V to 3.6V VCC ■ Power-off high impedance inputs and outputs ■ Static Drive (IOH/IOL) ■ ■ ■ ■ The VCX00 is fabricated with an advanced CMOS technology to achieve high-speed operation while maintaining low CMOS power dissipation. – ±24mA @ 3.0V VCC Uses proprietary noise/EMI reduction circuitry Latchup performance exceeds JEDEC 78 conditions ESD performance: – Human body model > 2000V – Machine model > 250V Leadless DQFN package Ordering Information Order Number 74VCX00M Package Number M14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74VCX00BQX(1) MLP14A 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 3.0mm 74VCX00MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Note: 1. DQFN package available in Tape and Reel only. Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. ©1999 Fairchild Semiconductor Corporation 74VCX00 Rev. 1.7.1 www.fairchildsemi.com 74VCX00 — Low Voltage Quad 2-Input NAND Gate with 3.6V Tolerant Inputs and Outputs December 2013 74VCX00 — Low Voltage Quad 2-Input NAND Gate with 3.6V Tolerant Inputs and Outputs Connection Diagrams Logic Symbol Pin Assignments for SOIC and TSSOP IEEE/IEC Pad Assignments for DQFN (Top View) (Bottom View) Pin Description Pin Names Description An, Bn Inputs On Outputs DAP No Connect Note: DAP (Die Attach Pad) ©1999 Fairchild Semiconductor Corporation 74VCX00 Rev. 1.7.1 www.fairchildsemi.com 2 Symbol VCC Parameter Rating Supply Voltage VI DC Input Voltage VO DC Output Voltage –0.5V to +4.6V –0.5V to 4.6V HIGH or LOW State(2) –0.5V to VCC + 0.5V VCC = 0V –0.5V to 4.6V IIK DC Input Diode Current, VI < 0V IOK DC Output Diode Current IOH / IOL –50mA VO < 0V –50mA VO > VCC +50mA DC Output Source/Sink Current ±50mA ICC or GND DC VCC or Gound Current per Supply Pin TSTG Storage Temperature Range ±100mA –65°C to +150°C Note: 2. IO Absolute Maximum Rating must be observed. Recommended Operating Conditions(3) The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC Parameter Power Supply Operating VI Input Voltage VO Output Voltage, HIGH or LOW State IOH / IOL Rating 1.2V to 3.6V –0.3V to 3.6V 0V to VCC Output Current VCC = 3.0V to 3.6V ±24mA VCC = 2.3V to 2.7V ±18mA VCC = 1.65V to 2.3V ±6mA VCC = 1.4V to 1.6V ±2mA VCC = 1.2V TA ∆t / ∆V ± 100µA Free Air Operating Temperature –40°C to +85°C Minimum Input Edge Rate, VIN = 0.8V to 2.0V, VCC = 3.0V 10ns/V Note: 3. Floating or unused inputs must be held HIGH or LOW ©1999 Fairchild Semiconductor Corporation 74VCX00 Rev. 1.7.1 www.fairchildsemi.com 3 74VCX00 — Low Voltage Quad 2-Input NAND Gate with 3.6V Tolerant Inputs and Outputs Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VIH VIL Parameter HIGH Level Input Voltage LOW Level Input Voltage VCC (V) Conditions Min 2.7–3.6 2.0 2.3–2.7 1.6 1.65–2.3 0.65 × VCC 1.4–1.6 0.65 × VCC 1.2 0.65 × VCC HIGH Level Output Voltage 0.8 2.3–2.7 0.7 0.35 × VCC 1.4–1.6 0.35 × VCC IOH = –100µA VCC – 0.2 2.7 IOH = –12mA 2.2 3.0 IOH = –18mA 2.4 3.0 IOH = –24mA 2.2 2.3–2.7 IOH = –100µA VCC – 0.2 2.3 IOH = –6mA 2.0 2.3 IOH = –12mA 1.8 2.3 IOH = –18mA 1.7 IOH = –100µA VCC – 0.2 1.4–1.6 LOW Level Output Voltage 0.05 x VCC 2.7–3.6 1.65 VOL V 1.65–2.3 1.65–2.3 IOH = –6mA IOH = –2mA 1.2 IOH = –100µA V 1.25 IOH = –100µA 1.4 VCC – 0.2 1.05 VCC – 0.2 2.7–3.6 IOL = 100µA 0.2 2.7 IOL = 12mA 0.4 3.0 IOL = 18mA 0.4 3.0 IOL = 24mA 0.55 2.3–2.7 IOL = 100µA 0.2 2.3 IOL = 12mA 0.4 2.3 IOL = 18mA 0.6 1.65–2.3 IOL = 100µA 0.2 IOL = 6mA 0.3 IOL = 100µA 0.2 1.4 IOL = 2mA 0.35 1.2 IOL = 100µA 0.05 1.65 1.4–1.6 Units V 2.7–3.6 1.2 VOH Max V Input Leakage Current 1.4–3.6 0 ≤ VI ≤ 3.6V ±5.0 µA IOZ 3-STATE Output Leakage 1.4–3.6 0 ≤ VO ≤ 3.6V, VI = VIH or VIL ±10 µA IOFF Power-OFF Leakage Current 0 ≤ (VI, VO) ≤ 3.6V 10 µA ICC Quiescent Supply Current VI = VCC or GND 20 µA VCC ≤ (VI, VO) ≤ ±20 II ∆ICC Increase in ICC per Input 0 1.4–3.6 2.7–3.6 VIH = VCC –0.6V 3.6V(4) 750 µA Note: 4. Outputs disabled or 3-STATE only. ©1999 Fairchild Semiconductor Corporation 74VCX00 Rev. 1.7.1 www.fairchildsemi.com 4 74VCX00 — Low Voltage Quad 2-Input NAND Gate with 3.6V Tolerant Inputs and Outputs DC Electrical Characteristics TA = –40°C to +85°C Symbol Parameter VCC (V) tPHL, tPLH Propagation Delay 3.3 ± 0.3 Conditions CL = 30pF, RL = 500Ω 2.5 ± 0.2 1.8 ± 0.15 1.5 ± 0.1 CL = 15pF, RL = 2kΩ 1.2 tOSHL, tOSLH Output to Output Skew(6) 3.3 ± 0.3 Min. Max. Units Figure Number 0.6 2.8 ns Fig. 1 0.8 3.7 1.0 7.4 1.0 14.8 Fig. 3 1.5 37.0 Fig. 4 CL = 30pF, RL = 500Ω 0.5 2.5 ± 0.2 0.5 1.8 ± 0.15 0.75 1.5 ± 0.1 Fig. 2 CL = 15pF, RL = 2kΩ ns 1.5 1.2 1.5 Note: 5. For CL = 50pF, add approximately 300ps to the AC Maximum specification. 6. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Dynamic Switching Characteristics TA = 25°C Symbol VOLP Parameter VCC (V) Quiet Output Dynamic Peak VOL 1.8 2.5 Conditions CL = 30pF, VIH = VCC, VIL = 0V 3.3 VOLV Quiet Output Dynamic Valley VOL 1.8 2.5 Quiet Output Dynamic Valley VOH 1.8 2.5 Unit 0.25 V 0.6 0.8 CL = 30pF, VIH = VCC, VIL = 0V 3.3 VOHV Typical –0.25 V –0.6 –0.8 CL = 30pF, VIH = VCC, VIL = 0V 3.3 1.5 V 1.9 2.2 Capacitance TA = +25°C Symbol Parameter Conditions Typical Units Input Capacitance VI = 0V or VCC, VCC = 1.8V, 2.5V or 3.3V 6 pF COUT Output Capacitance VI = 0V or VCC, VCC = 1.8V, 2.5V or 3.3V 7 pF CPD Power Dissipation Capacitance VI = 0V or VCC, f = 10 MHz, VCC = 1.8V, 2.5V or 3.3V 20 pF CIN ©1999 Fairchild Semiconductor Corporation 74VCX00 Rev. 1.7.1 www.fairchildsemi.com 5 74VCX00 — Low Voltage Quad 2-Input NAND Gate with 3.6V Tolerant Inputs and Outputs AC Electrical Characteristics(5) 74VCX00 — Low Voltage Quad 2-Input NAND Gate with 3.6V Tolerant Inputs and Outputs AC Loading and Waveforms (VCC 3.3V ± 0.3V to 1.8V ± 0.15V) Test Switch tPLH, tPHL Open Figure 1. AC Test Circuit VCC Symbol 3.3V ± 0.3V 2.5V ± 0.2V 1.8V ± 0.15V Vmi 1.5V VCC / 2 VCC / 2 Vmo 1.5V VCC / 2 VCC / 2 Figure 2. Waveform for Inverting and Non-inverting Functions ©1999 Fairchild Semiconductor Corporation 74VCX00 Rev. 1.7.1 www.fairchildsemi.com 6 74VCX00 — Low Voltage Quad 2-Input NAND Gate with 3.6V Tolerant Inputs and Outputs AC Loading and Waveforms (VCC 1.5 ± 0.1V to 1.2V) Test SWITCH tPLH, tPHL Open tPZL, tPLZ VCC x 2 at VCC = 1.5V ± 0.1V tPZH, tPHZ GND Figure 3. AC Test Circuit VCC Symbol 1.5V ± 0.1V Vmi VCC / 2 Vmo VCC / 2 Figure 4. Waveform for Inverting and Non-Inverting Functions ©1999 Fairchild Semiconductor Corporation 74VCX00 Rev. 1.7.1 www.fairchildsemi.com 7 Tape Format for DQFN Package Designator Tape Section Number of Cavities Cavity Status Cover Tape Status BQX Leader (Start End) 125 (Typ.) Empty Sealed Carrier 3000 Filled Sealed Trailer (Hub End) 75 (Typ.) Empty Sealed Tape Dimensions inches (millimeters) Reel Dimensions inches (millimeters) Tape Size A B C D N W1 W2 12mm 13.0 (330.0) 0.059 (1.50) 0.512 (13.00) 0.795 (20.20) 2.165 (55.00) 0.488 (12.4) 0.724 (18.4) ©1999 Fairchild Semiconductor Corporation 74VCX00 Rev. 1.7.1 www.fairchildsemi.com 8 74VCX00 — Low Voltage Quad 2-Input NAND Gate with 3.6V Tolerant Inputs and Outputs Tape and Reel Specification 74VCX00 — Low Voltage Quad 2-Input NAND Gate with 3.6V Tolerant Inputs and Outputs Physical Dimensions 8.75 8.50 0.65 A 7.62 14 8 B 5.60 4.00 3.80 6.00 PIN ONE INDICATOR 1 1.70 7 0.51 0.35 1.27 0.25 1.27 LAND PATTERN RECOMMENDATION M C B A (0.33) 1.75 MAX 1.50 1.25 SEE DETAIL A 0.25 0.10 C 0.25 0.19 0.10 C NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AB, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD GAGE PLANE FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X145-14M 0.36 E) DRAWING CONFORMS TO ASME Y14.5M-1994 F) DRAWING FILE NAME: M14AREV13 0.50 X 45° 0.25 R0.10 R0.10 8° 0° 0.90 0.50 (1.04) SEATING PLANE DETAIL A SCALE: 20:1 Figure 5. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1999 Fairchild Semiconductor Corporation 74VCX00 Rev. 1.7.1 www.fairchildsemi.com 9 74VCX00 — Low Voltage Quad 2-Input NAND Gate with 3.6V Tolerant Inputs and Outputs Physical Dimensions (Continued) Figure 6. 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 3.0mm Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1999 Fairchild Semiconductor Corporation 74VCX00 Rev. 1.7.1 www.fairchildsemi.com 10 0.65 0.43 TYP 1.65 6.10 0.45 12.00° TOP & BOTTOM R0.09 min A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION AB, REF NOTE 6 B. DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS D. DIMENSIONING AND TOLERANCES PER ANSI Y14.5M, 1982 E. LANDPATTERN STANDARD: SOP65P640X110-14M F. DRAWING FILE NAME: MTC14REV6 1.00 R0.09min Figure 7. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1999 Fairchild Semiconductor Corporation 74VCX00 Rev. 1.7.1 www.fairchildsemi.com 11 74VCX00 — Low Voltage Quad 2-Input NAND Gate with 3.6V Tolerant Inputs and Outputs Physical Dimensions (Continued) TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. AccuPower¥ AX-CAP®* BitSiC¥ Build it Now¥ CorePLUS¥ CorePOWER¥ CROSSVOLT¥ CTL¥ Current Transfer Logic¥ DEUXPEED® Dual Cool™ EcoSPARK® EfficientMax¥ ESBC¥ F-PFS¥ FRFET® SM Global Power Resource GreenBridge¥ Green FPS¥ Green FPS¥ e-Series¥ Gmax¥ GTO¥ IntelliMAX¥ ISOPLANAR¥ Making Small Speakers Sound Louder and Better™ MegaBuck¥ MICROCOUPLER¥ MicroFET¥ MicroPak¥ MicroPak2¥ MillerDrive¥ MotionMax¥ mWSaver® OptoHiT¥ OPTOLOGIC® OPTOPLANAR® ® Fairchild® Fairchild Semiconductor® FACT Quiet Series¥ FACT® FAST® FastvCore¥ FETBench¥ FPS¥ Sync-Lock™ ® PowerTrench® PowerXS™ Programmable Active Droop¥ QFET® QS¥ Quiet Series¥ RapidConfigure¥ ¥ Saving our world, 1mW/W/kW at a time™ SignalWise¥ SmartMax¥ SMART START¥ Solutions for Your Success¥ SPM® STEALTH¥ SuperFET® SuperSOT¥-3 SuperSOT¥-6 SuperSOT¥-8 SupreMOS® SyncFET¥ ®* TinyBoost® TinyBuck® TinyCalc¥ TinyLogic® TINYOPTO¥ TinyPower¥ TinyPWM¥ TinyWire¥ TranSiC¥ TriFault Detect¥ TRUECURRENT®* PSerDes¥ UHC® Ultra FRFET¥ UniFET¥ VCX¥ VisualMax¥ VoltagePlus¥ XS™ * Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in cause the failure of the life support device or system, or to affect its safety or effectiveness. accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. ANTI-COUNTERFEITING POLICY Fairchild Semiconductor Corporation's Anti-Counterfeiting Policy. Fairchild's Anti-Counterfeiting Policy is also stated on our external website, www.fairchildsemi.com, under Sales Support. Counterfeiting of semiconductor parts is a growing problem in the industry. All manufacturers of semiconductor products are experiencing counterfeiting of their parts. Customers who inadvertently purchase counterfeit parts experience many problems such as loss of brand reputation, substandard performance, failed applications, and increased cost of production and manufacturing delays. Fairchild is taking strong measures to protect ourselves and our customers from the proliferation of counterfeit parts. Fairchild strongly encourages customers to purchase Fairchild parts either directly from Fairchild or from Authorized Fairchild Distributors who are listed by country on our web page cited above. Products customers buy either from Fairchild directly or from Authorized Fairchild Distributors are genuine parts, have full traceability, meet Fairchild's quality standards for handling and storage and provide access to Fairchild's full range of up-to-date technical and product information. Fairchild and our Authorized Distributors will stand behind all warranties and will appropriately address any warranty issues that may arise. Fairchild will not provide any warranty coverage or other assistance for parts bought from Unauthorized Sources. Fairchild is committed to combat this global problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Advance Information Formative / In Design Preliminary First Production No Identification Needed Full Production Obsolete Not In Production Definition Datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. Rev. I66 © Fairchild Semiconductor Corporation www.fairchildsemi.com