74VHCT08A Quad 2-Input AND Gate Features General Description ■ High speed: tPD = 5.0ns (typ.) at TA = 25°C ■ High noise immunity: VIH = 2.0V, VIL = 0.8V The VHCT08A is an advanced high speed CMOS 2 Input AND Gate fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. ■ Power down protection is provided on all inputs and outputs Low noise: VOLP = 0.8V (max.) ■ ■ Low power dissipation: ICC = 2µA (max.) @ TA = 25°C ■ Pin and function compatible with 74HCT08 The internal circuit is composed of 4 stages including buffer output, which provide high noise immunity and stable output. Protection circuits ensure that 0V to 7V can be applied to the input pins without regard to the supply voltage and to the output pins with VCC = 0V. These circuits prevent device destruction due to mismatched supply and input/ output voltages. This device can be used to interface 3V to 5V systems and two supply systems such as battery backup. Ordering Information Order Number Package Number Package Description 74VHCT08AM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74VHCT08ASJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHCT08AMTC 74HCT08AN MTC14 N14A 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. ©1997 Fairchild Semiconductor Corporation 74VHCT08A Rev. 1.3.0 www.fairchildsemi.com 74VHCT08A — Quad 2-Input AND Gate February 2008 74VHCT08A — Quad 2-Input AND Gate Connection Diagram Logic Symbol IEEE/IEC Pin Description Pin Names Truth Table Description An, Bn Inputs A B O On Outputs L L L ©1997 Fairchild Semiconductor Corporation 74VHCT08A Rev. 1.3.0 L H L H L L H H H www.fairchildsemi.com 2 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Rating VCC Supply Voltage –0.5V to +7.0V VIN DC Input Voltage –0.5V to +7.0V VOUT DC Output Voltage HIGH or LOW state, IOUT absolute maximum rating must be observed VCC = 0V –0.5V to VCC + 0.5V –0.5V to +7.0V IIK Input Diode Current –20mA IOK Output Diode Current, VOUT < GND, VOUT > VCC (Outputs Active) ±20mA IOUT DC Output Current ±25mA ICC DC VCC / GND Current TSTG Storage Temperature TL ±50mA –65°C to +150°C Lead Temperature (Soldering, 10 seconds) 260°C Recommended Operating Conditions(1) The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol Parameter Rating VCC Supply Voltage 4.5V to 5.5V VIN Input Voltage 0V to +5.5V VOUT Output Voltage HIGH or LOW state, IOUT absolute maximum rating must be observed VCC = 0V TOPR tr , tf 0V to VCC 0V to +5.5V Operating Temperature –40°C to +85°C Input Rise and Fall Time, VCC = 5.0V ± 0.5V 0ns/V ∼ 20ns/V Note: 1. Unused inputs must be held HIGH or LOW. They may not float. ©1997 Fairchild Semiconductor Corporation 74VHCT08A Rev. 1.3.0 www.fairchildsemi.com 3 74VHCT08A — Quad 2-Input AND Gate Absolute Maximum Ratings TA = –40°C to +85°C TA = 25°C Symbol Parameter VIH HIGH Level VIL VOH VCC (V) Min. Typ. Max. Min. Max. Units 4.5 2.0 Input Voltage 5.5 2.0 LOW Level 4.5 0.8 0.8 Input Voltage 5.5 0.8 0.8 HIGH Level 4.5 Output Voltage VOL Conditions LOW Level Output Voltage 4.5 VIN = VIH IOH = –50µA or VIL IOH = –8mA 4.40 2.0 2.0 4.50 V 4.40 3.94 VIN = VIH IOL = 50µA or VIL IOL = 8mA V V 3.80 0.0 0.1 0.1 0.36 0.44 V 0–5.5 VIN = 5.5V or GND ±0.1 ±1.0 µA Quiescent Supply Current 5.5 VIN = VCC or GND 2.0 20.0 µA ICCT Maximum ICC / Input 5.5 V IN = 3.4V, Other Inputs = VCC or GND 1.35 1.50 mA IOFF Output Leakage Current (Power Down State) 0.0 VOUT = 5.5V 0.5 5.0 µA IIN Input Leakage Current ICC Noise Characteristics TA = 25°C Symbol Parameter VCC (V) Conditions Typ. Limits Units Quiet Output Maximum Dynamic VOL 5.0 CL = 50pF 0.4 0.8 V VOLV(2) Quiet Output Minimum Dynamic VOL 5.0 CL = 50pF –0.4 –0.8 V VIHD(2) Minimum HIGH Level Dynamic Input Voltage 5.0 CL = 50pF 2.0 V VILD(2) Maximum LOW Level Dynamic Input Voltage 5.0 CL = 50pF 0.8 V VOLP (2) Note: 2. Parameter guaranteed by design. ©1997 Fairchild Semiconductor Corporation 74VHCT08A Rev. 1.3.0 www.fairchildsemi.com 4 74VHCT08A — Quad 2-Input AND Gate DC Electrical Characteristics TA = –40°C to +85°C TA = 25°C Symbol tPLH, tPHL Parameter Propagation Delay CIN Input Capacitance CPD Power Dissipation Capacitance VCC (V) Conditions Typ Max Min Max Units 5.0 ± 0.5 CL = 15pF 5.0 6.9 1.0 8.0 ns CL = 50pF 5.5 7.9 1.0 9.0 4 10 VCC (3) = Open Min 10 18 pF pF Note: 3. CPD is defined as the value of the internal equivalent capacitance, which is calculated from the operating current consumption without load. Average operating current can be obtained from the equation: ICC (opr.) = CPD • VCC • fIN + ICC / 4 (per gate) ©1997 Fairchild Semiconductor Corporation 74VHCT08A Rev. 1.3.0 www.fairchildsemi.com 5 74VHCT08A — Quad 2-Input AND Gate AC Electrical Characteristics 8.75 8.50 0.65 A 7.62 14 8 B 5.60 4.00 3.80 6.00 PIN ONE INDICATOR 1 1.70 7 0.51 0.35 1.27 0.25 1.27 LAND PATTERN RECOMMENDATION M C B A (0.33) 1.75 MAX 1.50 1.25 SEE DETAIL A 0.25 0.10 C 0.25 0.19 0.10 C NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AB, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD GAGE PLANE FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X145-14M 0.36 E) DRAWING CONFORMS TO ASME Y14.5M-1994 F) DRAWING FILE NAME: M14AREV13 0.50 X 45° 0.25 R0.10 R0.10 8° 0° 0.90 0.50 (1.04) SEATING PLANE DETAIL A SCALE: 20:1 Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1997 Fairchild Semiconductor Corporation 74VHCT08A Rev. 1.3.0 www.fairchildsemi.com 6 74VHCT08A — Quad 2-Input AND Gate Physical Dimensions 74VHCT08A — Quad 2-Input AND Gate Physical Dimensions (Continued) Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1997 Fairchild Semiconductor Corporation 74VHCT08A Rev. 1.3.0 www.fairchildsemi.com 7 74VHCT08A — Quad 2-Input AND Gate Physical Dimensions (Continued) 0.65 0.43 TYP 1.65 6.10 0.45 12.00° TOP & BOTTOM R0.09 min A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION AB, REF NOTE 6 B. DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS D. DIMENSIONING AND TOLERANCES PER ANSI Y14.5M, 1982 E. LANDPATTERN STANDARD: SOP65P640X110-14M F. DRAWING FILE NAME: MTC14REV6 1.00 R0.09min Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1997 Fairchild Semiconductor Corporation 74VHCT08A Rev. 1.3.0 www.fairchildsemi.com 8 74VHCT08A — Quad 2-Input AND Gate Physical Dimensions (Continued) 19.56 18.80 14 8 6.60 6.09 1 7 (1.74) 8.12 7.62 1.77 1.14 3.56 3.30 0.35 0.20 5.33 MAX 0.38 MIN 3.81 3.17 0.58 0.35 8.82 2.54 NOTES: UNLESS OTHERWISE SPECIFIED THIS PACKAGE CONFORMS TO A) JEDEC MS-001 VARIATION BA B) ALL DIMENSIONS ARE IN MILLIMETERS. DIMENSIONS ARE EXCLUSIVE OF BURRS, C) MOLD FLASH, AND TIE BAR EXTRUSIONS. D) DIMENSIONS AND TOLERANCES PER ASME Y14.5-1994 E) DRAWING FILE NAME: MKT-N14AREV7 Figure 4. 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1997 Fairchild Semiconductor Corporation 74VHCT08A Rev. 1.3.0 www.fairchildsemi.com 9 ACEx® Build it Now™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ EcoSPARK® EZSWITCH™ * ™ PDP-SPM™ SyncFET™ ® Power220® ® Power247 The Power Franchise® POWEREDGE® Power-SPM™ PowerTrench® TinyBoost™ Programmable Active Droop™ TinyBuck™ ® QFET TinyLogic® QS™ TINYOPTO™ QT Optoelectronics™ TinyPower™ ® Quiet Series™ TinyPWM™ RapidConfigure™ TinyWire™ Fairchild® SMART START™ Fairchild Semiconductor® µSerDes™ ® SPM FACT Quiet Series™ UHC® STEALTH™ FACT® Ultra FRFET™ SuperFET™ FAST® UniFET™ SuperSOT™-3 FastvCore™ VCX™ ® ®* SuperSOT™-6 FlashWriter SuperSOT™-8 * EZSWITCH™ and FlashWriter® are trademarks of System General Corporation, used under license by Fairchild Semiconductor. FPS™ FRFET® Global Power ResourceSM Green FPS™ Green FPS™ e-Series™ GTO™ i-Lo™ IntelliMAX™ ISOPLANAR™ MegaBuck™ MICROCOUPLER™ MicroFET™ MicroPak™ MillerDrive™ Motion-SPM™ OPTOLOGIC® OPTOPLANAR® DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I32 ©1997 Fairchild Semiconductor Corporation 74VHCT08A Rev. 1.3.0 www.fairchildsemi.com 10 74VHCT08A — Quad 2-Input AND Gate TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks.