74VHCT74A Dual D-Type Flip-Flop with Preset and Clear Features General Description n High speed: fMAX = 160MHz (Typ.) at TA = 25°C n High noise immunity: VIH = 2.0V, VIL = 0.8V The VHCT74A is an advanced high speed CMOS Dual D-Type Flip-Flop fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The signal level applied to the D INPUT is transferred to the Q OUTPUT during the positive going transition of the CK pulse. CLR and PR are independent of the CK and are accomplished by setting the appropriate input LOW. n Power down protection is provided on all inputs and outputs n Low power dissipation: ICC = 2µA (Max.) at TA = 25°C n Pin and function compatible with 74HCT74 Protection circuits ensure that 0V to 7V can be applied to the input pins without regard to the supply voltage and to the output pins with VCC = 0V. These circuits prevent device destruction due to mismatched supply and input/ output voltages. This device can be used to interface 3V to 5V systems and two supply systems such as battery backup. Ordering Information Order Number Package Number Package Description 74VHCT74AM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74VHCT74ASJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHCT74AMTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. ©2008 Fairchild Semiconductor Corporation 74VHCT74A Rev. 1.4.0 www.fairchildsemi.com 74VHCT74A — Dual D-Type Flip-Flop with Preset and Clear May 2008 Logic Symbol IEEE/IEC Pin Description Pin Names Truth Table Description D1, D2 Data Inputs CK1, CK2 Clock Pulse Inputs CLR1, CLR2 Direct Clear Inputs PR1, PR2 Direct Preset Inputs Q1, Q1, Q2, Q2 Outputs ©2008 Fairchild Semiconductor Corporation 74VHCT74A Rev. 1.4.0 Inputs Outputs CLR PR D CK Q Q Function L H X X L H Clear H L X X H L Preset L L X X H H H H L L H H H H H L H H X Qn Qn No Change www.fairchildsemi.com 2 74VHCT74A — Dual D-Type Flip-Flop with Preset and Clear Connection Diagram Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Rating VCC Supply Voltage –0.5V to +7.0V VIN DC Input Voltage –0.5V to +7.0V VOUT DC Output Voltage Note 1 –0.5V to VCC + 0.5V Note 2 –0.5V to 7.0V IIK Input Diode Current –20mA IOK Output Diode Current(3) ±20mA IOUT DC Output Current ±25mA ICC DC VCC / GND Current ±50mA TSTG TL Storage Temperature –65°C to +150°C Lead Temperature (Soldering, 10 seconds) 260°C Recommended Operating Conditions(4) The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol Parameter VCC Supply Voltage VIN Input Voltage VOUT Rating 4.5V to +5.5V 0V to +5.5V Output Voltage Note 1 0V to VCC Note 2 TOPR Operating Temperature t r, t f Input Rise and Fall Time 0V to 5.5V –40°C to +85°C VCC = 5.0V ±0.5V 0ns/V ∼ 20ns/V Notes: 1. HIGH or LOW state. IOUT absolute maximum rating must be observed. 2. VCC = 0V. 3. VOUT < GND, VOUT > VCC (Outputs Active). 4. Unused inputs must be held HIGH or LOW. They may not float. ©2008 Fairchild Semiconductor Corporation 74VHCT74A Rev. 1.4.0 www.fairchildsemi.com 3 74VHCT74A — Dual D-Type Flip-Flop with Preset and Clear Absolute Maximum Ratings TA = –40°C to +85°C TA = 25°C Symbol VIH VIL VOH VOL Parameter VCC (V) Conditions Min. Typ. Max. Min. Max. HIGH Level Input Voltage 4.5 2.0 2.0 5.5 2.0 2.0 LOW Level Input Voltage 4.5 0.8 0.8 5.5 0.8 0.8 HIGH Level Output Voltage 4.5 LOW Level Output Voltage 4.5 4.5 4.5 VIN = VIH IOH = –50µA or VIL IOH = –8mA 4.40 4.50 VIN = VIH IOL = 50µA or VIL IOL = 8mA V 4.40 3.94 Units V V 3.80 0.0 0.1 0.1 0.36 0.44 V 0–5.5 VIN = 5.5V or GND ±0.1 ±1.0 µA Quiescent Supply Current 5.5 VIN = VCC or GND 2.0 20.0 µA ICCT Maximum ICC / Input 5.5 VIN = 3.4V, Other Inputs = VCC or GND 1.35 1.50 mA IOFF Output Leakage Current (Power Down State) 0.0 VOUT = 5.5V +0.5 +5.0 µA IIN Input Leakage Current ICC AC Electrical Characteristics TA = –40°C to +85°C TA = 25°C Symbol fMAX Parameter Maximum Clock Frequency tPLH, tPHL Propagation Delay Time (CK-Q, Q) tPLH, tPHL Propagation Delay Time (CLR, PR-Q, Q) CIN CPD VCC (V)(5) Conditions Min. Typ. 5.0 CL = 15pF 100 160 80 5.0 CL = 50pF 80 140 65 5.0 CL = 15pF 5.8 5.0 CL = 50pF 6.3 8.8 1.0 10.0 5.0 CL = 15pF 7.6 10.4 1.0 12.0 5.0 CL = 50pF 8.1 11.4 1.0 13.0 4 10 Input Capacitance VCC = Open Power Dissipation Capacitance (6) Max. 7.8 Min. 1.0 Max. Units MHz 9.0 10 24 ns ns pF pF Notes: 5. VCC is 5.0 ± 0.5V 6. CPD is defined as the value of internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (Opr.) = CPD • VCC • fIN + ICC / 2 (per flip-flop). ©2008 Fairchild Semiconductor Corporation 74VHCT74A Rev. 1.4.0 www.fairchildsemi.com 4 74VHCT74A — Dual D-Type Flip-Flop with Preset and Clear DC Electrical Characteristics TA = –40°C to +85°C TA = 25°C Symbol Guaranteed Minimum Typ. Units Parameter VCC (V) Minimum Pulse Width (CK) 5.0 ± 0.5 5.0 5.0 ns Minimum Pulse Width (CLR, PR) 5.0 ± 0.5 5.0 5.0 ns tS Minimum Setup Time 5.0 ± 0.5 5.0 5.0 ns tH Minimum Hold Time 5.0 ± 0.5 0 0 ns Minimum Removal Time (CLR, PR) 5.0 ± 0.5 3.5 3.5 ns tW(L), tW(H) tW(L) tREM ©2008 Fairchild Semiconductor Corporation 74VHCT74A Rev. 1.4.0 www.fairchildsemi.com 5 74VHCT74A — Dual D-Type Flip-Flop with Preset and Clear AC Operating Requirements 74VHCT74A — Dual D-Type Flip-Flop with Preset and Clear Physical Dimensions Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©2008 Fairchild Semiconductor Corporation 74VHCT74A Rev. 1.4.0 www.fairchildsemi.com 6 74VHCT74A — Dual D-Type Flip-Flop with Preset and Clear Physical Dimensions (Continued) Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©2008 Fairchild Semiconductor Corporation 74VHCT74A Rev. 1.4.0 www.fairchildsemi.com 7 74VHCT74A — Dual D-Type Flip-Flop with Preset and Clear Physical Dimensions (Continued) Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©2008 Fairchild Semiconductor Corporation 74VHCT74A Rev. 1.4.0 www.fairchildsemi.com 8 ACEx® Build it Now™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ EcoSPARK® EZSWITCH™ * ™ PDP-SPM™ SyncFET™ ® Power220® ® Power247 The Power Franchise® POWEREDGE® Power-SPM™ PowerTrench® TinyBoost™ Programmable Active Droop™ TinyBuck™ ® QFET TinyLogic® QS™ TINYOPTO™ QT Optoelectronics™ TinyPower™ ® Quiet Series™ TinyPWM™ RapidConfigure™ TinyWire™ Fairchild® SMART START™ Fairchild Semiconductor® μSerDes™ ® SPM FACT Quiet Series™ UHC® STEALTH™ FACT® Ultra FRFET™ SuperFET™ FAST® UniFET™ SuperSOT™-3 FastvCore™ VCX™ ® ®* SuperSOT™-6 FlashWriter SuperSOT™-8 * EZSWITCH™ and FlashWriter® are trademarks of System General Corporation, used under license by Fairchild Semiconductor. FPS™ FRFET® Global Power ResourceSM Green FPS™ Green FPS™ e-Series™ GTO™ i-Lo™ IntelliMAX™ ISOPLANAR™ MegaBuck™ MICROCOUPLER™ MicroFET™ MicroPak™ MillerDrive™ Motion-SPM™ OPTOLOGIC® OPTOPLANAR® DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I32 ©2008 Fairchild Semiconductor Corporation 74VHCT74A Rev. 1.4.0 www.fairchildsemi.com 9 74VHCT74A — Dual D-Type Flip-Flop with Preset and Clear TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks.