W9816G6JH 512K 2 BANKS 16 BITS SDRAM Table of Contents1. 2. 3. 4. 5. 6. 7. 8. 9. 10. GENERAL DESCRIPTION ......................................................................................................... 3 FEATURES ................................................................................................................................. 3 ORDER INFORMATION ............................................................................................................. 4 PIN CONFIGURATION ............................................................................................................... 4 PIN DESCRIPTION..................................................................................................................... 5 BLOCK DIAGRAM ...................................................................................................................... 6 FUNCTIONAL DESCRIPTION.................................................................................................... 7 7.1 Power Up and Initialization ............................................................................................. 7 7.2 Programming Mode Register .......................................................................................... 7 7.3 Bank Activate Command ................................................................................................ 7 7.4 Read and Write Access Modes ...................................................................................... 7 7.5 Burst Read Command .................................................................................................... 8 7.6 Burst Write Command .................................................................................................... 8 7.7 Read Interrupted by a Read ........................................................................................... 8 7.8 Read Interrupted by a Write............................................................................................ 8 7.9 Write Interrupted by a Write ............................................................................................ 8 7.10 Write Interrupted by a Read............................................................................................ 8 7.11 Burst Stop Command ..................................................................................................... 9 7.12 Addressing Sequence of Sequential Mode .................................................................... 9 7.13 Addressing Sequence of Interleave Mode ...................................................................... 9 7.14 Auto-precharge Command ........................................................................................... 10 7.15 Precharge Command .................................................................................................... 10 7.16 Self Refresh Command ................................................................................................ 10 7.17 Power Down Mode ....................................................................................................... 11 7.18 No Operation Command ............................................................................................... 11 7.19 Deselect Command ...................................................................................................... 11 7.20 Clock Suspend Mode .................................................................................................... 11 OPERATION MODE ................................................................................................................. 12 ELECTRICAL CHARACTERISTICS ......................................................................................... 13 9.1 Absolute Maximum Ratings .......................................................................................... 13 9.2 Recommended DC Operating Conditions .................................................................... 13 9.3 Capacitance .................................................................................................................. 13 9.4 DC Characteristics ........................................................................................................ 14 9.5 AC Characteristics ........................................................................................................ 15 TIMING WAVEFORMS ............................................................................................................. 17 10.1 Command Input Timing ................................................................................................ 17 10.2 Read Timing.................................................................................................................. 18 10.3 Control Timing of Input/Output Data ............................................................................. 19 10.4 Mode Register Set Cycle .............................................................................................. 20 -1- Publication Release Date: Jun. 24, 2014 Revision: A01 W9816G6JH 11. 12. 13. OPERATING TIMING EXAMPLE ............................................................................................. 21 11.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3) ...................................... 21 11.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge) ........... 22 11.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) ...................................... 23 11.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge) ........... 24 11.5 Interleaved Bank Write (Burst Length = 8) ................................................................... 25 11.6 Interleaved Bank Write (Burst Length = 8, Auto-precharge) ........................................ 26 11.7 Page Mode Read (Burst Length = 4, CAS Latency = 3) .............................................. 27 11.8 Page Mode Read / Write (Burst Length = 8, CAS Latency = 3) ................................... 28 11.9 Auto Precharge Read (Burst Length = 4, CAS Latency = 3) ........................................ 29 11.10 Auto Precharge Write (Burst Length = 4) .................................................................... 30 11.11 Auto Refresh Cycle ..................................................................................................... 31 11.12 Self Refresh Cycle ....................................................................................................... 32 11.13 Burst Read and Single Write (Burst Length = 4, CAS Latency = 3)............................ 33 11.14 Power Down Mode ...................................................................................................... 34 11.15 Auto-precharge Timing (Read Cycle) .......................................................................... 35 11.16 Auto-precharge Timing (Write Cycle) .......................................................................... 36 11.17 Timing Chart of Read to Write Cycle ........................................................................... 37 11.18 Timing Chart of Write to Read Cycle ........................................................................... 37 11.19 Timing Chart of Burst Stop Cycle (Burst Stop Command) .......................................... 38 11.20 Timing Chart of Burst Stop Cycle (Precharge Command) .......................................... 38 11.21 CKE/DQM Input Timing (Write Cycle) ......................................................................... 39 11.22 CKE/DQM Input Timing (Read Cycle) ......................................................................... 40 PACKAGE SPECIFICATION .................................................................................................... 41 REVISION HISTORY ................................................................................................................ 42 -2- Publication Release Date: Jun. 24, 2014 Revision: A01 W9816G6JH 1. GENERAL DESCRIPTION W9816G6JH is a high-speed synchronous dynamic random access memory (SDRAM), organized as 512K words 2 banks 16 bits. W9816G6JH delivers a data bandwidth of up to 200M words per second. To fully comply with the personal computer industrial standard, W9816G6JH is sorted into the following speed grades: -5, -6, -6I, -7 and -7I. The -5 grade parts can run up to 200MHz/CL3. The -6 and -6I grade parts can run up to 166MHz/CL3 (the -6I industrial grade parts which is guaranteed to support -40°C ≤ TA ≤ 85°C). The -7 and -7I grade parts can run up to 143MHz/CL3 (the -7I industrial grade parts which is guaranteed to support -40°C ≤ TA ≤ 85°C). Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time. By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W9816G6JH is ideal for main memory in high performance applications. 2. FEATURES 3.3V ± 0.3V power supply for -5/-6/-6I speed grades 2.7V~3.6V power supply for -7/-7I speed grades Up to 200 MHz Clock Frequency 524,288 words x 2 banks x 16 bits organization Self Refresh current: standard and low power CAS Latency: 2 and 3 Burst Length: 1, 2, 4, 8 and Full Page Burst Read, Single Writes Mode Byte Data Controlled by LDQM, UDQM Auto-precharge and Controlled Precharge 2K Refresh Cycles/32 mS Interface: LVTTL Packaged in 50-pin, 400 mil TSOP II, using Lead free materials with RoHS compliant -3- Publication Release Date: Jun. 24, 2014 Revision: A01 W9816G6JH 3. ORDER INFORMATION PART NUMBER SPEED GRADE SELF REFRESH CURRENT (MAX) OPERATING TEMPERATURE W9816G6JH-5 200MHz/CL3 2mA 0°C ~ 70°C W9816G6JH-6 166MHz/CL3 2mA 0°C ~ 70°C W9816G6JH-6I 166MHz/CL3 2mA -40°C ~ 85°C W9816G6JH-7 143MHz/CL3 2mA 0°C ~ 70°C W9816G6JH-7I 143MHz/CL3 2mA -40°C ~ 85°C 4. PIN CONFIGURATION VDD 1 50 VSS DQ0 2 49 DQ15 DQ1 3 48 DQ14 VSSQ 4 47 VSSQ DQ2 5 46 DQ13 DQ3 6 45 VDDQ 7 44 VDDQ DQ4 8 43 DQ11 DQ5 9 42 DQ10 VSSQ 10 41 VSSQ DQ6 11 40 DQ9 DQ7 12 39 DQ8 VDDQ 13 38 VDDQ LDQM 14 37 NC WE 15 36 UDQM CAS 16 35 CLK RAS 17 34 CKE CS 18 33 NC BA 19 32 A9 A10 20 31 A8 A0 21 30 A7 A1 22 29 A6 A2 23 28 A5 A3 24 27 A4 VDD 25 26 VSS -4- DQ12 Publication Release Date: Jun. 24, 2014 Revision: A01 W9816G6JH 5. PIN DESCRIPTION PIN NUMBER PIN NAME FUNCTION 2024, 2732 A0A10 Address 19 BA Bank Select 2, 3, 5, 6, 8, 9, 11, 12, 39, 40, DQ0DQ15 42, 43, 45, 46, 48, 49 18 CS Data Input/ Output Chip Select DESCRIPTION Multiplexed pins for row and column address. Row address: A0A10. Column address: A0A7. Select bank to activate during row address latch time, or bank to read/write during column address latch time. Multiplexed pins for data input and output. Disable or enable the command decoder. When command decoder is disabled, new command is ignored and previous operation continues. Command input. When sampled at the rising edge of Row Address the clock, R A S , C A S and W E define the operation Strobe to be executed. 17 RAS 16 CAS 15 WE Write Enable Referred to 36, 14 UDQM/ LDQM Input/Output Mask The output buffer is placed at Hi-Z (with latency of 2) when DQM is sampled high in read cycle. In write cycle, sampling DQM high will block the write operation with zero latency. 35 CLK Clock Inputs System clock used to sample inputs on the rising edge of clock. 34 CKE Clock Enable CKE controls the clock activation and deactivation. When CKE is low, Power Down mode, Suspend mode, or Self Refresh mode is entered. 1, 25 VDD Power Power for input buffers and logic circuit inside DRAM. 26, 50 VSS Ground Ground for input buffers and logic circuit inside DRAM. 7, 13, 38, 44, VDDQ Power for I/O buffer 4, 10, 41, 47 VSSQ Ground for I/O Separated ground from VSS, used for output buffers buffer to improve noise immunity. 33, 37 NC Column Address Strobe Referred to RAS RAS Separated power from VDD, used for output buffers to improve noise immunity. No Connection No connection. -5- Publication Release Date: Jun. 24, 2014 Revision: A01 W9816G6JH 6. BLOCK DIAGRAM CLK CLOCK BUFFER CKE CS CONTROL RAS GENERATOR COLUMN DECODER SIGNAL COMMAND CAS R O W DECODER D E C O D E R WE CELL ARRAY BANK #0 SENSE AMPLIFIER A10 MODE REGISTER A0 A9 BA ADDRESS BUFFER DQ DATA CONTROL DQ0 BUFFER CIRCUIT DQ15 LDQM UDQM REFRESH COLUMN COUNTER COUNTER COLUMN DECODER R O W D E C O D E R CELL ARRAY BANK #1 SENSE AMPLIFIER Note: The cell array configuration is 2048 * 256 * 16 -6- Publication Release Date: Jun. 24, 2014 Revision: A01 W9816G6JH 7. FUNCTIONAL DESCRIPTION 7.1 Power Up and Initialization The default power up state of the mode register is unspecified. The following power up and initialization sequence need to be followed to guarantee the device being preconditioned to each user specific needs during power up, all VDD and VDDQ pins must be ramp up simultaneously to the specified voltage when the input signals are held in the “NOP” state. The power up voltage must not exceed VDD + 0.3V on any of the input pins or VDD supplies. After power up, an initial pause of 200 µS is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power up, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. An additional eight Auto Refresh cycles (CBR) are also required before or after programming the Mode Register to ensure proper subsequent operation. 7.2 Programming Mode Register After initial power up, the Mode Register Set Command must be issued for proper device operation. All banks must be in a precharged state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. The Mode Register Set Command is activated by the low signals of R A S , C A S , C S and W E at the positive edge of the clock. The address input data during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new command may be issued following the mode register set command once a delay equal to tRSC has elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table. 7.3 Bank Activate Command The Bank Activate command must be applied before any Read or Write operation can be executed. The delay from when the Bank Activate command is applied to when the first read or write operation can begin must not be less than the RAS to CAS delay time (tRCD). Once a bank has been activated it must be precharged before another Bank Activate command can be issued to the same bank. The minimum time interval between successive Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC). The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank-to-Bank delay time (tRRD). The maximum time that each bank can be held active is specified as tRAS(max.). 7.4 Read and Write Access Modes After a bank has been activated, a read or write cycle can be followed. This is accomplished by setting R A S high and C A S low at the clock rising edge after minimum of tRCD delay. W E pin voltage level defines whether the access cycle is a read operation ( W E high), or a write operation ( W E low). The address inputs determine the starting column address. Reading or writing to a different row within an activated bank requires the bank be precharged and a new Bank Activate command be issued. When more than one bank is activated, interleaved bank Read or Write operations are possible. By using the programmed burst length and alternating the access and precharge operations between multiple banks, seamless data access operation among many different pages can be realized. Read or Write Commands can also be issued to the same bank or between active banks on every clock cycle. -7- Publication Release Date: Jun. 24, 2014 Revision: A01 W9816G6JH 7.5 Burst Read Command The Burst Read command is initiated by applying logic low level to C S and C A S while holding R A S and W E high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst length (1, 2, 4, 8 and full page) during the Mode Register Set Up cycle. 7.6 Burst Write Command The Burst Write command is initiated by applying logic low level to C S , C A S and W E while holding R A S high at the rising edge of the clock. The address inputs determine the starting column address. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle that the Write Command is issued. The remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes will be ignored. 7.7 Read Interrupted by a Read A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted, the remaining addresses are overridden by the new read address with the full burst length. The data from the first Read Command continues to appear on the outputs until the CAS Latency from the interrupting Read Command the is satisfied. 7.8 Read Interrupted by a Write To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM masking is no longer needed. 7.9 Write Interrupted by a Write A burst write may be interrupted before completion of the burst by another Write Command. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied. 7.10 Write Interrupted by a Read A Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is activated. The DQs must be in the high impedance state at least one cycle before the new read data appears on the outputs to avoid data contention. When the Read Command is activated, any residual data from the burst write cycle will be ignored. -8- Publication Release Date: Jun. 24, 2014 Revision: A01 W9816G6JH 7.11 Burst Stop Command A Burst Stop Command may be used to terminate the existing burst operation but leave the bank open for future Read or Write Commands to the same page of the active bank, if the burst length is full page. Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop Command is defined by having R A S and C A S high with C S and W E low at the rising edge of the clock. The data DQs go to a high impedance state after a delay, which is equal to the C A S Latency in a burst read cycle, interrupted by Burst Stop. If a Burst Stop Command is issued during a full page burst write operation, then any residual data from the burst write cycle will be ignored. 7.12 Addressing Sequence of Sequential Mode A column access is performed by increasing the address from the column address, which is input to the device. The disturb address is varied by the Burst Length as shown in Table 2. Table 2 Address Sequence of Sequential Mode DATA ACCESS ADDRESS BURST LENGTH Data 0 n BL = 2 (disturb address is A0) Data 1 n+1 No address carry from A0 to A1 Data 2 n+2 BL = 4 (disturb addresses are A0 and A1) Data 3 n+3 No address carry from A1 to A2 Data 4 n+4 Data 5 n+5 BL = 8 (disturb addresses are A0, A1 and A2) Data 6 n+6 No address carry from A2 to A3 Data 7 n+7 7.13 Addressing Sequence of Interleave Mode A column access is started in the input column address and is performed by inverting the address bit in the sequence shown in Table 3. Table 3 Address Sequence of Interleave Mode DATA ACCESS ADDRESS BURST LENGTH Data 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 BL = 2 Data 1 A8 A7 A6 A5 A4 A3 A2 A1 Data 2 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 3 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 4 A8 A7 A6 A5 A4 A3 Data 5 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 6 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 7 A8 A7 A6 A5 A4 A3 A2 A1 A0 A2 -9- A0 A1 A0 BL = 4 BL = 8 Publication Release Date: Jun. 24, 2014 Revision: A01 W9816G6JH 7.14 Auto-precharge Command If A10 is set to high when the Read or Write Command is issued, then the Auto-precharge function is entered. During Auto-precharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge automatically before all burst read cycles have been completed. Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled burst cycle. The number of clocks is determined by CAS Latency. A Read or Write Command with Auto-precharge can not be interrupted before the entire burst operation is completed. Therefore, use of a Read, Write, or Precharge Command is prohibited during a read or write cycle with Auto-precharge. Once the precharge operation has started, the bank cannot be reactivated until the Precharge time (tRP) has been satisfied. Issue of Auto-precharge command is illegal if the burst is set to full page length. If A10 is high when a Write Command is issued, the Write with Auto-precharge function is initiated. The SDRAM automatically enters the precharge operation two clock delay from the last burst write cycle. This delay is referred to as Write tWR. The bank undergoing Auto-precharge can not be reactivated until tWR and tRP are satisfied. This is referred to as tDAL, Data-in to Active delay (tDAL = tWR + tRP). When using the Auto-precharge Command, the interval between the Bank Activate Command and the beginning of the internal precharge operation must satisfy tRAS(min). 7.15 Precharge Command The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is entered when C S , R A S and W E are low and C A S is high at the rising edge of the clock. The Precharge Command can be used to precharge each bank separately or all banks simultaneously. The address bits, A10, and BA, are used to define which bank(s) is to be precharged when the command is issued. After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write access can be executed. The delay between the Precharge Command and the Activate Command must be greater than or equal to the Precharge time (tRP). 7.16 Self Refresh Command The Self-Refresh Command is defined by having C S , R A S , C A S and CKE held low with W E high at the rising edge of the clock. All banks must be idle prior to issuing the Self-Refresh Command. Once the command is registered, CKE must be held low to keep the device in Self-Refresh mode. When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are disabled. The clock is internally disabled during Self-Refresh Operation to save power. The device will exit Self-Refresh operation after CKE is returned high. Any subsequent commands can be issued after tXSR from the end of Self Refresh command. - 10 - Publication Release Date: Jun. 24, 2014 Revision: A01 W9816G6JH 7.17 Power Down Mode The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are gated off to reduce the power. The Power Down mode does not perform any refresh operations; therefore the device can not remain in Power Down mode longer than the Refresh period (tREF) of the device. The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation Command is required on the next rising clock edge, depending on tCK. The input buffers need to be enabled with CKE held high for a period equal to tCKS(min) + tCK(min). 7.18 No Operation Command The No Operation Command should be used in cases when the SDRAM is in an idle or a wait state to prevent the SDRAM from registering any unwanted commands between operations. A No Operation Command is registered when C S is low with R A S , C A S and W E held high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle. 7.19 Deselect Command The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when C S is brought high, the R A S , C A S and W E signals become don't cares. 7.20 Clock Suspend Mode During normal access mode, CKE must be held high enabling the clock. When CKE is registered low while at least one of the banks is active and a column access/burst is in progess, Clock Suspend mode is entered. The Clock Suspend mode deactivates the internal clock and suspends any clocked operation that was currently being executed. There is a one-clock delay between the registration of CKE low and the time at which the SDRAM operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are issued. The Clock Suspend mode is exited by bringing CKE high. There is a one-clock cycle delay from when CKE returns high to when Clock Suspend mode is exited. - 11 - Publication Release Date: Jun. 24, 2014 Revision: A01 W9816G6JH 8. OPERATION MODE Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 1 shows the truth table for the operation commands. Table 1 Truth Table (Note 1, 2) COMMAND DEVICE STATE CKEn-1 CKEn DQM BA A10 A9-A0 CS RAS CAS WE Bank Active Idle H X X V V V L L H H Bank Precharge Any H X X V L X L L H L Precharge All Any H X L L H L H X X X Write Active (3) H X X V L V L H L L Write with Auto-precharge Active (3) H X X V H V L H L L Read Active (3) H X X V L V L H L H Read with Auto-precharge Active (3) H X X V H V L H L H H X X V V V L L L L H X X X X X L H H H H X X X X X L H H L Mode Register Set No-Operation Burst Stop Idle Any Active (4) Device Deselect Any H X X X X X H X X X Auto-Refresh Idle H H X X X X L L L H Self-Refresh Entry Idle H L X X X X L L L H Self-Refresh Exit Idle (S.R) L L H H X X X X X X X X H L X H X H X X Clock Suspend Mode Entry Active H L X X X X X X X X Power Down Mode Entry Idle (5) Active H H L L X X X X X X X X H L X H X H X X Clock Suspend Mode Exit Active L H X X X X X X X X Any (power down) L L H H X X X X X X X X H L X H X H X X H X L X X X X X X X X H X X X X X X X Power Down Mode Exit Data Write/Output Enable Active Data Write/Output Disable Active H Notes: (1) V = valid, X = Don't care, L = Low Level, H = High Level (2) CKEn signal is input level when commands are provided. CKEn-1 signal is the input level one clock cycle before the command is issued. (3) These are state of bank designated by BA signals. (4) Device state is full page burst operation. (5) Power Down Mode can not be entered in the burst cycle. When this command asserts in the burst cycle, device state is clock suspend mode. - 12 - Publication Release Date: Jun. 24, 2014 Revision: A01 W9816G6JH 9. ELECTRICAL CHARACTERISTICS 9.1 Absolute Maximum Ratings PARAMETER SYMBOL RATING UNIT NOTES Voltage on any pin relative to VSS VIN, VOUT -0.5 ~ VDD + 0.5 ( 4.6V max.) V 1 Voltage on VDD/VDDQ supply relative to VSS VDD, VDDQ -0.5 ~ 4.6 V 1 Operating Temperature for -5/-6/-7 TA 0 ~ 70 °C 1 Operating Temperature for -6I/-7I TA -40 ~ 85 °C 1 TSTG -55 ~ 150 °C 1 TSOLDER 260 °C 1 PD 1 W 1 IOUT 50 mA 1 Storage Temperature Soldering Temperature (10s) Power Dissipation Short Circuit Output Current Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device 9.2 Recommended DC Operating Conditions PARAMETER SYM. MIN. TYP. MAX. UNIT NOTES Power Supply Voltage for -5/-6/-6I VDD 3.0 3.3 3.6 V 2 Power Supply Voltage for -7/-7I VDD 2.7 3.3 3.6 V 2 Power Supply Voltage for -5/-6/-6I (for I/O Buffer) VDDQ 3.0 3.3 3.6 V 2 Power Supply Voltage for -7/-7I (for I/O Buffer) VDDQ 2.7 3.3 3.6 V 2 Input High Voltage VIH 2.0 - VDD + 0.3 V 2 Input Low Voltage VIL -0.3 - 0.8 V 2 Note: VIH (max.) = VDD/VDDQ +1.5V for pulse width ≤ 5 nS VIL (min.) = VSS/VSSQ -1.5V for pulse width ≤ 5 nS 9.3 Capacitance (VDD = 3.3V ± 0.3V, TA = 25°C, f = 1MHz) PARAMETER Input Capacitance (A0 to A10, BA, LDQM, CKE) CS , RAS , CAS , WE , UDQM, SYM. MIN. MAX. UNIT CI - 4 pf - 4 pf - 5.5 pf Input Capacitance (CLK) Input/Output capacitance (DQ0 to DQ15) CIO Note: These parameters are periodically sampled and not 100% tested - 13 - Publication Release Date: Jun. 24, 2014 Revision: A01 W9816G6JH 9.4 DC Characteristics (VDD = 3.3V ± 0.3V for -5/-6/-6I, VDD = 2.7V to 3.6V for -7/-7I, TA = 0 to 70°C for -5/-6/-7, TA= -40 to 85°C for -6I//-7I) PARAMETER SYM. -5 -6/-6I -7/-7I MAX. MAX. MAX. UNIT NOTES Operating Current tCK = min., tRC = min. Active precharge command cycling without burst operation 1 Bank operation IDD1 40 35 30 3 Standby Current tCK = min., CS = VIH VIH/L = VIH (min.)/VIL (max.) CKE = VIH IDD2 15 15 15 3 CKE = VIL (Power Down Mode) IDD2P 2 2 2 3 CKE = VIH IDD2S 6 6 6 CKE = VIL IDD2PS (Power Down Mode) 2 2 2 Bank: Inactive state Standby Current CLK = VIL, CS = VIH VIH/L=VIH (min.)/VIL (max.) Bank: Inactive state No Operating Current tCK = min., CS = VIH(min) mA CKE = VIH IDD3 25 23 20 CKE = VIL (Power Down Mode) IDD3P 6 6 6 Burst Operating Current tCK = min. Read/ Write command cycling IDD4 60 55 50 3, 4 Auto Refresh Current tCK = min. Auto refresh command cycling IDD5 45 40 35 3 Self Refresh Current Self Refresh Mode CKE = 0.2V IDD6 2 2 2 Bank: Active state (2 Banks) PARAMETER SYM. MIN. MAX. UNIT Input Leakage Current (0V ≤ VIN ≤ VDD, all other pins not under test = 0V) II(L) -5 5 µA Output Leakage Current (Output disable , 0V ≤ VOUT ≤ VDDQ ) IO(L) -5 5 µA LVTTL Output “H” Level Voltage (IOUT = -2 mA) VOH 2.4 - V LVTTL Output “L” Level Voltage (IOUT = 2 mA) VOL - 0.4 V - 14 - NOTES Publication Release Date: Jun. 24, 2014 Revision: A01 W9816G6JH 9.5 AC Characteristics (VDD = 3.3V ± 0.3V for -5/-6/-6I, VDD = 2.7V to 3.6V for -7/-7I, TA = 0 to 70°C for -5/-6/-7, TA= -40 to 85°C for -6I//-7I) PARAMETER SYM. -5 MIN. -6/-6I MAX. MIN. -7/-7I MAX. Ref/Active to Ref/Active Command Period tRC 55 Active to Precharge Command Period tRAS 40 Active to Read/Write Command Delay Time tRCD 15 18 20 Read/Write(a) to Read/Write(b)Command Period tCCD 1 1 1 Precharge to Active(b) Command Period tRP 15 18 18 Active(a) to Active(b) Command Period tRRD 10 12 14 2 2 2 2 2 2 Write Recovery Time CLK Cycle Time CL* = 2 CL* = 3 CL* = 2 CL* = 3 tWR tCK 60 MIN. 100000 42 MAX. UNIT NOTES 65 100000 45 100000 nS tCK nS tCK 7 1000 8 1000 10 1000 5 1000 6 1000 7 1000 CLK High Level Width tCH 2 2 2 8 CLK Low Level Width tCL 2 2 2 8 Access Time from CLK CL* = 2 CL* = 3 Output Data Hold Time Output Data High Impedance Time tAC tOH CL* = 2 CL* = 3 6 5.5 5.5 4.5 5 5 2 2 tHZ 9 2 9 6 5.5 5.5 4.5 5 5 0 Output Data Low Impedance Time tLZ 0 Power Down Mode Entry Time tSB 0 Data-in-Set-up Time tDS 1.5 1.5 1.5 8 Data-in Hold Time tDH 0.7 0.7 1 8 Address Set-up Time tAS 1.5 1.5 1.5 8 Address Hold Time tAH 0.7 0.7 1 8 CKE Set-up Time tCKS 1.5 1.5 1.5 8 CKE Hold Time tCKH 0.7 0.7 1 8 Command Set-up Time tCMS 1.5 1.5 1.5 8 Command Hold Time tCMH 0.7 0.7 1 8 Refresh Time (2K Refresh Cycles) tREF Mode Register Set Cycle Time tRSC 2 2 2 tCK Exit self refresh to ACTIVE command tXSR 70 72 75 nS 5 0 32 0 7 6 0 32 nS 9 7 32 mS * CL = CAS Latency - 15 - Publication Release Date: Jun. 24, 2014 Revision: A01 W9816G6JH Notes: 1. Operation exceeds “Absolute Maximum Ratings” may cause permanent damage to the devices. 2. All voltages are referenced to VSS. • 3.3V ± 0.3V power supply for -5/-6/-6I speed grades. • 2.7V~3.6V power supply for -7/-7I speed grades. 3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum values of tCK and tRC. 4. These parameters depend on the output loading conditions. Specified values are obtained with output open. 5. Power up sequence please refer to “Functional Description” section described before. 6. AC test load diagram. 1.4 V 50 ohms output Z = 50 ohms 30pF AC TEST LOAD 7. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to output level. 8. Assumed input rise and fall time (tT) = 1nS. If tr & tf is longer than 1nS, transient time compensation should be considered, i.e., [(tr + tf)/2-1]nS should be added to the parameter 9. If clock rising time (tT) is longer than 1nS, (tT/2-0.5)nS should be added to the parameter. - 16 - Publication Release Date: Jun. 24, 2014 Revision: A01 W9816G6JH 10. TIMING WAVEFORMS 10.1 Command Input Timing tCK tCL tCH VIH CLK VIL tT tCMS tCMH tCMS tCMH tCMS tCMH tCMS tCMH tAS tAH tCMH tT tCMS CS RAS CAS WE A0-A10 BA tCKS tCKH tCKS tCKS tCKH tCKH CKE - 17 - Publication Release Date: Jun. 24, 2014 Revision: A01 W9816G6JH 10.2 Read Timing Read CAS Latency CLK CS RAS CAS WE A0-A10 BA tAC tLZ Valid Data-Out DQ Read Command tHZ tAC tOH tOH Valid Data-Out Burst Length - 18 - Publication Release Date: Jun. 24, 2014 Revision: A01 W9816G6JH 10.3 Control Timing of Input/Output Data Control Timing of Input Data (Word Mask) CLK tCMS tCMH tCMH tCMS DQM tDS tDH tDS tDS Valid Data-in Valid Data-in DQ0~15 tDH tDH tDS tDH Valid Data-in Valid Data-in (Clock Mask) CLK tCKH tCKS tCKH tDH tDS tDH tCKS CKE tDS DQ0~15 Valid Data-in tDS Valid Data-in tDH tDS tDH Valid Data-in Valid Data-in Control Timing of Output Data (Output Enable) CLK tCMS tCMH tCMH tCMS DQM tAC tOH tAC tLZ Valid Data-Out Valid Data-Out DQ0~15 tAC tHZ tOH tOH tAC tOH Valid Data-Out OPEN (Clock Mask) CLK tCKS tCKH tCKH tCKS CKE DQ0~15 tAC tAC tAC tAC tOH tOH tOH Valid Data-Out Valid Data-Out - 19 - tOH Valid Data-Out Publication Release Date: Jun. 24, 2014 Revision: A01 W9816G6JH 10.4 Mode Register Set Cycle tRSC CLK tCMS tCMH tCMS tCMH tCMS tCMH tCMS tCMH tAS tAH CS RAS CAS WE A0-A10 BA Register set data A0 A1 Burst Length A2 A3 Addressing Mode A4 A5 CAS Latency next command A0 A0 A0 A2 A1 0 A0 0 0 0 A0 0 1 0 A0 1 0 0 A0 1 1 1 A0 0 0 1 A0 0 1 1 A0 1 0 1 A0 1 1 A0 A3 A0 0 A0 1 A6 A0 A7 "0" (Test Mode) A8 "0" Reserved Write Mode A9 A10 "0" A0 BA "0" Reserved A6 0 0 0 0 1 A0 A5 A0 0 A0 0 A0 1 A0 1 A0 0 A0 A9 A0 0 A0 1 - 20 - BurstA0 Length A0 A0 Sequential Interleave 1 A0 1 A0 A0 2 2 A0 A0 4 4 A0 A0 8 8 A0 Reserved A0 Reserved FullA0 Page A0 Mode Addressing A0 Sequential A0 Interleave A4 0 1 0 1 0 CAS A0 Latency A0 Reserved A0 Reserved 2 A0 3 Reserved Single Write Mode A0 Burst write Burst read and A0 single write Burst read and Publication Release Date: Jun. 24, 2014 Revision: A01 W9816G6JH 11. OPERATING TIMING EXAMPLE 11.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3) 0 1 2 3 4 6 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC tRC tRC tRC RAS tRAS tRP tRAS tRAS tRP tRP tRAS CAS WE BA tRCD A10 RAa A0-A9 RAa tRCD tRCD RBb CAw tRCD RAc CBx RBb RBd RAc CAy RAe RBd CBz RAe DQM CKE aw0 tRRD Bank #0 Active Bank #1 tAC tAC tAC DQ aw1 aw2 aw3 bx0 Precharge Active bx2 bx3 Active - 21 - cy1 cy2 cy3 tRRD Precharge Read Precharge Read tAC cy0 tRRD tRRD Read bx1 Active Active Read Publication Release Date: Jun. 24, 2014 Revision: A01 W9816G6JH 11.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC tRC tRC tRC RAS tRAS tRP tRAS tRP tRAS tRP tRAS CAS WE BA tRCD tRCD A10 RAa A0-A9 RAa RBb CAw tRCD tRCD RBd RAc CBx RBb CAy RAc RAe CBz RBd RAe DQM CKE tAC tAC DQ aw0 tRRD Bank #0 Bank #1 Active aw1 aw2 aw3 tAC bx0 bx1 Active AP* Active bx3 tAC cy0 cy1 tRRD tRRD Read bx2 Read cy3 dz0 tRRD AP* Read AP* cy2 Active Active Read * AP is the internal precharge start timing - 22 - Publication Release Date: Jun. 24, 2014 Revision: A01 W9816G6JH 11.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS t RC RAS t RAS tRP t RAS tRP CAS WE BA t RCD A10 RAa A0-A9 RAa t RCD t RCD RAc RBb CAx RBb CBy RAc CAz DQM CKE tAC DQ tAC ax0 ax1 t RRD Bank #0 Bank #1 Active ax2 ax3 ax4 by0 by1 by4 by5 by6 by7 CZ0 t RRD Read Precharge ax6 ax5 tAC Precharge Active Read - 23 - Active Read Precharge Publication Release Date: Jun. 24, 2014 Revision: A01 W9816G6JH 11.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK tRC CS RAS tRAS tRAS tRP tRAS tRP CAS WE BA tRCD A10 RAa A0-A9 RAa tRCD tRCD RAc RBb CAx RAc CBy RBb CAz DQM CKE tAC DQ ax0 ax1 ax2 tRRD Bank #0 Bank #1 Active tAC tAC ax3 ax4 ax5 ax6 ax7 by0 by1 by4 Active Read by5 by6 CZ0 tRRD AP* Read Active Read AP* * AP is the internal precharge start timing - 24 - Publication Release Date: Jun. 24, 2014 Revision: A01 W9816G6JH 11.5 Interleaved Bank Write (Burst Length = 8) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC RAS tRAS tRP tRAS tRAS tRP CAS WE BA tRCD tRCD A10 RAa A0-A9 RAa tRCD RBb CAx RAb RBb CBy CAz RAc DQM CKE ax0 DQ ax1 ax4 ax5 ax6 ax7 by0 by1 Bank #1 Active by3 by4 by5 by6 by7 CZ0 CZ1 CZ2 tRRD tRRD Bank #0 by2 Write AP* Active Write Active Write AP* * AP is the internal precharge start timing - 25 - Publication Release Date: Jun. 24, 2014 Revision: A01 W9816G6JH 11.6 Interleaved Bank Write (Burst Length = 8, Auto-precharge) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC RAS tRAS tRP tRAS tRAS tRP CAS WE BA tRCD tRCD A10 RAa A0-A9 RAa tRCD RBb CAx RAb RBb CBy CAz RAc DQM CKE ax0 DQ ax1 ax4 ax5 ax6 ax7 by0 by1 Bank #1 Active by3 by4 by5 by6 by7 CZ0 CZ1 CZ2 tRRD tRRD Bank #0 by2 Write Active AP* Active Write AP* Write * AP is the internal precharge start timing - 26 - Publication Release Date: Jun. 24, 2014 Revision: A01 W9816G6JH 11.7 Page Mode Read (Burst Length = 4, CAS Latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK tCCD tCCD tCCD CS tRAS tRAS RAS CAS WE BA tRCD A10 RAa A0-A9 RAa tRCD RBb RBb CAI CBx CAy CAm CBz DQM CKE tAC a0 DQ tAC tAC a2 a1 a3 bx0 bx1 Ay0 tAC Ay1 Ay2 tAC am0 am1 am2 bz0 bz1 bz2 bz3 tRRD Bank #0 Active Bank #1 Read Active Read Read Read Precharge Read AP* * AP is the internal precharge start timing - 27 - Publication Release Date: Jun. 24, 2014 Revision: A01 W9816G6JH 11.8 Page Mode Read / Write (Burst Length = 8, CAS Latency = 3) 0 1 2 3 5 4 6 7 8 9 11 10 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRAS RAS CAS WE BA tRCD A10 RAa A0-A9 RAa CAy CAx DQM CKE tAC DQ tWR ax0 Q Q Bank #0 Active ax1 ax3 ax2 Q Q ax5 ax4 Q Q Read ay1 ay0 D D Write ay2 D ay3 D ay4 D Precharge Bank #1 - 28 - Publication Release Date: Jun. 24, 2014 Revision: A01 W9816G6JH 11.9 Auto Precharge Read (Burst Length = 4, CAS Latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC RAS tRAS tRAS tRP CAS WE BA tRCD A10 RAa A0-A9 RAa tRCD RAb CAw RAb CAx DQM CKE tAC DQ Bank #0 tAC aw0 Active Read aw1 aw2 bx0 aw3 AP* Active Read bx1 bx2 bx3 AP* Bank #1 * AP is the internal precharge start timing - 29 - Publication Release Date: Jun. 24, 2014 Revision: A01 W9816G6JH 11.10 Auto Precharge Write (Burst Length = 4) CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CS tRC tRC RAS tRP tRAS tRAS tRP CAS WE BA tRCD tRCD A10 RAa A0-A9 RAa RAc RAb CAw RAb CAx RAc DQM CKE aw0 DQ Bank #0 Active Write aw1 aw2 aw3 bx0 AP* Active Write bx1 bx2 bx3 AP* Active Bank #1 * AP is the internal precharge start timing - 30 - Publication Release Date: Jun. 24, 2014 Revision: A01 W9816G6JH 11.11 Auto Refresh Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK tRP tRC tRC CS RAS CAS WE BA A10 A0-A9 DQM CKE DQ All Banks Prechage Auto Refresh Auto Refresh (Arbitrary Cycle) - 31 - Publication Release Date: Jun. 24, 2014 Revision: A01 W9816G6JH 11.12 Self Refresh Cycle CLK CS tRP RAS CAS WE BA A10 A0-A9 DQM tCKS tSB CKE tCKS DQ tXSR Self Refresh Cycle All Banks Precharge Self Refresh Entry No Operation / Command Inhibit Self Refresh Exit - 32 - Arbitrary Cycle Publication Release Date: Jun. 24, 2014 Revision: A01 W9816G6JH 11.13 Burst Read and Single Write (Burst Length = 4, CAS Latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS RAS CAS tRCD WE BA A10 RBa A0-A9 RBa CBv CBw CBx CBy CBz DQM CKE tAC tAC DQ av0 Q Bank #0 Active av1 Q av2 av3 aw0 ax0 ay0 az0 az1 az2 az3 Q Q D D D Q Q Q Q Read Single Write Read Bank #1 - 33 - Publication Release Date: Jun. 24, 2014 Revision: A01 W9816G6JH 11.14 Power Down Mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS RAS CAS WE BA A10 RAa A0-A9 RAa RAa CAa RAa CAx DQM tSB tSB CKE tCKS tCKS ax0 Active tCKS tCKS DQ ax1 ax2 NOP Read ax3 Precharge NOP Active Precharge Standby Power Down mode Active Standby Power Down mode Note: The Power Down Mode is entered by asserting CKE "low". All Input/Output buffers (except CKE buffers) are turned off in the Power Down mode. When CKE goes high, command input must be No operation at next CLK rising edge. Violating refresh requirements during power-down may result in a loss of data. - 34 - Publication Release Date: Jun. 24, 2014 Revision: A01 W9816G6JH 11.15 Auto-precharge Timing (Read Cycle) 0 1 R ead AP 2 3 4 5 6 7 8 Q5 Q6 9 10 11 (1 ) C A S L a te n cy =2 ( a ) b u r s t le n g t h = 1 C om m and Act tR P DQ Q0 ( b ) b u rs t le n g t h = 2 C om m and R ead AP Act tR P DQ Q0 Q1 ( c ) b u r s t le n g t h = 4 C om m and R ead AP Act tR P DQ Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 ( d ) b u rs t le n g t h = 8 C om m and R ead AP Act tR P DQ Q4 Q7 (2 ) C A S L a te n cy =3 ( a ) b u r s t le n g t h = 1 C om m and R ead AP Act tR P Q0 DQ ( b ) b u rs t le n g t h = 2 C om m and R ead AP Act tR P Q0 DQ Q1 ( c ) b u r s t le n g t h = 4 C om m and R ead AP Act tR P Q0 DQ Q1 Q2 Q3 ( d ) b u rs t le n g t h = 8 C om m and R ead AP Act tR P Q0 DQ Q1 Q2 Q3 Q4 Q5 Q6 Q7 N o te : R ead AP A ct re p re s e n t s t h e R e a d w i t h A u t o p re c h a rg e c o m m a n d . re p re s e n t s t h e s t a rt o f in t e rn a l p re c h a rg in g . re p re s e n t s t h e B a n k A c t i v a t e c o m m a n d . W h e n t h e A u t o p re c h a rg e c o m m a n d is a s s e rt e d , t h e p e ri o d f ro m B a n k A c t iv a t e c o m m a n d t o t h e s t a rt o f i n t e rn a l p re c g a rg i n g m u s t b e a t l e a s t Rt A S (m in ). - 35 - Publication Release Date: Jun. 24, 2014 Revision: A01 W9816G6JH 11.16 Auto-precharge Timing (Write Cycle) 0 1 2 3 4 5 6 7 8 9 10 11 12 CLK ( 1 ) C A S L a te n c y = 2 ( a ) b u r s t l e n g th = 1 C ommand W r it e AP tW R DQ A ct tR P D0 ( b ) b u r s t l e n g th = 2 C ommand W r it e AP A ct tW R DQ D0 tR P D1 ( c ) b u r s t l e n g th = 4 C ommand AP W r it e DQ D0 D1 D2 A ct tR P tW R D3 ( d ) b u r s t l e n g th = 8 C ommand W r it e AP tW R DQ D0 D1 D2 D3 D4 D5 D6 A ct tR P D7 ( 2 ) C A S L a te n c y = 3 ( a ) b u r s t l e n g th = 1 C ommand W r it e AP A ct tW R DQ tR P D0 ( b ) b u r s t l e n g th = 2 C ommand W r it e AP A ct tW R DQ D0 tR P D1 ( c ) b u r s t l e n g th = 4 C ommand W r it e AP A ct tW R DQ D0 D1 D2 tR P D3 ( d ) b u r s t l e n g th = 8 C ommand W r it e AP tW R DQ D0 D1 D2 D3 D4 D5 D6 A ct tR P D7 N o te ) W r it e r e p r e s e n t s t h e W r it e w it h A u t o p r e c h a r g e c o m m a n d . AP r e p r e s e n t s t h e s ta r t o f in t e r n a l p r e c h a r in g . A ct r e p r e s e n t s t h e B a n k A c tiv e c o m m a n d . W h e n t h e / a u t o p r e c h a r g e c o m m a n d is a s s e r t e d , t h e p e r io d f r o m B a n k A c t iv a t e c o m m a n d t o t h e s t a r t o f in t e r m a l p r e c g a r g in g m u s t b e a t le a s t t R A S ( m in ) . - 36 - Publication Release Date: Jun. 24, 2014 Revision: A01 W9816G6JH 11.17 Timing Chart of Read to Write Cycle In th e c a s e o f B u r s t L e n g th = 4 0 1 2 R ead W r ite 3 4 5 D1 D2 D3 D0 D1 D2 D1 D2 D3 D1 D2 6 7 8 9 10 11 9 10 11 (1 ) C A S L a t e n c y = 2 ( a ) C o m m an d DQM DQ D0 ( b ) C o m m an d R ead W r ite DQM DQ D3 (2 ) C A S L a t e n c y = 3 R ead ( a ) C o m m an d W r ite DQM D0 DQ R ead ( b ) C o m m an d W r ite DQM D0 DQ D3 N o te : T h e O u tp u t d a ta m u s t b e m a s k e d b y D Q M to a v o id I/O c o n fli c t 11.18 Timing Chart of Write to Read Cycle In th e c a s e o f B u r s t L e n g th = 4 0 1 2 W ri te R ead 3 4 5 6 7 8 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Q0 Q1 Q2 ( 1 ) C A S L a te n c y = 2 ( a ) C o m m an d DQM DQ ( b ) C o m m an d D0 R ead W ri te DQM DQ D0 D1 W ri te R ead ( 2 ) C A S L a te n c y = 3 ( a ) C o m m an d DQM DQ ( b ) C o m m an d D0 W ri te R ead DQM DQ D0 D1 - 37 - Q3 Publication Release Date: Jun. 24, 2014 Revision: A01 W9816G6JH 11.19 Timing Chart of Burst Stop Cycle (Burst Stop Command) 0 1 2 3 4 5 6 7 8 9 10 11 ( 1 ) R e a d c y c le ( a ) C A S la t e n c y = 2 C o m m an d R ead BST Q0 DQ Q1 Q2 Q4 Q3 ( b ) C A S la t e n c y = 3 C o m m an d R ead BST Q0 DQ Q1 Q2 Q3 Q4 ( 2 ) W rit e c y c le C o m m an d W ri te BST DQ Q0 Q1 Q2 N o te : Q3 BST Q4 re p re s e n ts th e B u rs t s to p c o m m a n d 11.20 Timing Chart of Burst Stop Cycle (Precharge Command) 0 1 2 3 4 5 6 7 8 9 10 11 (1 ) R e a d c y c le ( a ) C A S la t e n c y = 2 C om m and Read PRCG DQ Q0 Q1 Q2 Q3 Q4 ( b ) C A S la t e n c y = 3 C om m and Read PRCG DQ Q0 Q1 Q2 Q3 Q4 (2 ) W r ite c y c le C om m and PRCG W r it e tW R DQM DQ Q0 Q1 Q2 Q3 Q4 - 38 - Publication Release Date: Jun. 24, 2014 Revision: A01 W9816G6JH 11.21 CKE/DQM Input Timing (Write Cycle) C L K c y c le N o . 1 2 D1 D2 3 4 5 6 7 E x te r n a l CLK In t e r n a l C KE DQM DQ D3 D5 D Q M MASK D6 C KE MASK ( 1 ) C L K c y c le N o . 1 2 3 D1 D2 D3 4 5 6 7 E x te r n a l CLK In t e r n a l C KE DQM DQ D Q M MASK D5 D6 6 7 C KE MASK ( 2 ) C L K c y c le N o . 1 2 3 D1 D2 D3 4 5 E x te r n a l CLK In t e r n a l CKE DQM DQ D4 D5 D6 C KE MASK ( 3 ) - 39 - Publication Release Date: Jun. 24, 2014 Revision: A01 W9816G6JH 11.22 CKE/DQM Input Timing (Read Cycle) C L K c y c le N o . 1 2 3 4 Q2 Q3 Q4 6 5 7 E x te r n a l C LK In te r n a l CKE DQM DQ Q1 Q6 O pe n O pe n ( 1 ) C L K c y c le N o . 1 2 3 Q1 Q2 Q3 4 5 7 6 E x te r n a l C LK In te r n a l CKE DQM DQ Q6 Q4 O pe n ( 2 ) C L K c y c le N o . 1 2 Q1 Q2 3 4 5 6 7 E x te r n a l C LK In te r n a l CKE DQM DQ Q4 Q3 Q5 Q6 ( 3 ) - 40 - Publication Release Date: Jun. 24, 2014 Revision: A01 W9816G6JH 12. PACKAGE SPECIFICATION Package Outline 50L TSOP (II)-400 mil 50 26 HE E 1 25 e b C D q L A2 A L1 A1 ZD SEATING PLANE Y Controlling Dimension: Millimeters DIMENSION SYM. MIN. NOM. A (MM) DIMENSION MAX. MIN. NOM. 1.20 (INCH) MAX. 0.047 A1 0.05 0.10 0.15 0.002 0.004 0.006 A2 0.90 1.00 1.10 0.035 0.039 0.043 b 0.30 0.45 0.012 c 0.10 0.15 0.20 0.004 0.006 0.008 D 20.82 20.95 21.08 0.820 0.825 0.830 E 10.03 10.16 10.29 0.395 0.400 0.405 HE 11.56 11.76 11.96 0.455 0.463 0.471 0.80 e L 0.40 0.50 0.60 0.016 0.020 0.004 0.031 0.88 0o 0.024 0.031 0.10 Y ZD 0.031 0.80 L1 0.018 o 10 0o - 41 - 10 o Publication Release Date: Jun. 24, 2014 Revision: A01 W9816G6JH 13. REVISION HISTORY VERSION DATE PAGE A01 Jun. 24, 2014 All DESCRIPTION Initial formally datasheet Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. - 42 - Publication Release Date: Jun. 24, 2014 Revision: A01