W25Q20CL - Winbond

W25Q20CL
2.5/3/3.3V
2M-BIT
SERIAL FLASH MEMORY WITH
4KB SECTORS, DUAL AND QUAD SPI
-1-
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
Table of Contents
1.
2.
3.
4.
5.
6.
7.
GENERAL DESCRIPTION ......................................................................................................... 5
FEATURES ................................................................................................................................. 5
PIN CONFIGURATION SOIC 150-MIL AND VSOP 150-MIL ..................................................... 6
PAD CONFIGURATION WSON 6X5-MM AND USON 2X3-MM ................................................ 6
PIN DESCRIPTION SOIC/ VSOP 150-MIL, WSON 5X6-MM AND USON 2X3-MM.................. 6
5.1
Package Types ............................................................................................................... 7
5.2
Chip Select (/CS) ............................................................................................................ 7
5.3
Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3)............................... 7
5.4
Write Protect (/WP) ......................................................................................................... 7
5.5
HOLD (/HOLD)................................................................................................................ 7
5.6
Serial Clock (CLK) .......................................................................................................... 7
BLOCK DIAGRAM ...................................................................................................................... 8
FUNCTIONAL DESCRIPTION.................................................................................................... 9
7.1
SPI OPERATIONS.......................................................................................................... 9
7.1.1
7.1.2
7.1.3
7.1.4
7.2
WRITE PROTECTION .................................................................................................. 10
7.2.1
8.
Standard SPI Instructions ................................................................................................. 9
Dual SPI Instructions ........................................................................................................ 9
Quad SPI Instructions....................................................................................................... 9
Hold Function ................................................................................................................... 9
Write Protect Features.................................................................................................... 10
CONTROL AND STATUS REGISTERS ................................................................................... 11
8.1
STATUS REGISTER .................................................................................................... 11
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
8.1.6
8.1.7
8.1.8
8.1.9
8.1.10
8.1.11
8.1.12
8.2
BUSY.............................................................................................................................. 11
Write Enable Latch (WEL) .............................................................................................. 11
Block Protect Bits (BP2, BP1, BP0) ................................................................................ 11
Top/Bottom Block Protect (TB) ....................................................................................... 11
Sector/Block Protect (SEC) ............................................................................................ 11
Complement Protect (CMP) ........................................................................................... 12
Status Register Protect (SRP1, SRP0)........................................................................... 12
Erase/Program Suspend Status (SUS) .......................................................................... 12
Security Register Lock Bits (LB3, LB2, LB1, LB0) .......................................................... 12
Quad Enable (QE) ........................................................................................................ 13
2M-BIT Status Register Memory Protection (CMP = 0) ................................................ 14
2M-BIT Status Register Memory Protection (CMP = 1) ................................................ 15
INSTRUCTIONS ........................................................................................................... 16
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
Manufacturer and Device Identification .......................................................................... 16
Instruction Set Table 1 (Erase, Program Instructions) .................................................... 17
Instruction Set Table 2 (Read Instructions) .................................................................... 18
Instruction Set Table 3 (ID, Security Instructions) .......................................................... 19
Write Enable (06h).......................................................................................................... 20
Write Enable for Volatile Status Register (50h) .............................................................. 20
Write Disable (04h) ......................................................................................................... 21
Read Status Register-1 (05h) and Read Status Register-2 (35h) .................................. 21
-2-
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
8.2.9 Write Status Register (01h) ............................................................................................ 22
8.2.10 Read Data (03h) ........................................................................................................... 23
8.2.11 Fast Read (0Bh) ........................................................................................................... 24
8.2.12 Fast Read Dual Output (3Bh) ....................................................................................... 25
8.2.13 Fast Read Quad Output (6Bh) ...................................................................................... 26
8.2.14 Fast Read Dual I/O (BBh) ............................................................................................. 27
8.2.15 Fast Read Quad I/O (EBh) ........................................................................................... 29
8.2.16 Set Burst with Wrap (77h) ............................................................................................ 31
8.2.17 Continuous Read Mode Bits (M7-0) ............................................................................. 32
8.2.18 Continuous Read Mode Reset (FFh or FFFFh) ............................................................ 32
8.2.19 Page Program (02h) ..................................................................................................... 33
8.2.20 Quad Input Page Program (32h) .................................................................................. 34
8.2.21 Sector Erase (20h) ....................................................................................................... 35
8.2.22 32KB Block Erase (52h) ............................................................................................... 36
8.2.23 64KB Block Erase (D8h) ............................................................................................... 37
8.2.24 Chip Erase (C7h / 60h) ................................................................................................. 38
8.2.25 Erase / Program Suspend (75h) ................................................................................... 39
8.2.26 Erase / Program Resume (7Ah) ................................................................................... 40
8.2.27 Power-down (B9h) ........................................................................................................ 41
8.2.28 Release Power-down / Device ID (ABh) ....................................................................... 42
8.2.29 Read Manufacturer / Device ID (90h) ........................................................................... 44
8.2.30 Read Manufacturer / Device ID Dual I/O (92h) ............................................................. 45
8.2.31 Read Manufacturer / Device ID Quad I/O (94h) ........................................................... 46
8.2.32 Read Unique ID Number (4Bh) .................................................................................... 47
8.2.33 Read JEDEC ID (9Fh) .................................................................................................. 48
8.2.34 Erase Security Registers (44h) ..................................................................................... 49
8.2.35 Program Security Registers (42h) ................................................................................ 50
8.2.36 Read Security Registers (48h) ..................................................................................... 51
9.
10.
ELECTRICAL CHARACTERISTICS ......................................................................................... 52
9.1
Absolute Maximum Ratings ........................................................................................ 52
9.2
Operating Ranges ......................................................................................................... 52
9.3
Power-up Timing and Write Inhibit Threshold .............................................................. 53
9.4
DC Electrical Characteristics ........................................................................................ 54
9.5
AC Measurement Conditions ........................................................................................ 55
9.6
AC Electrical Characteristics ........................................................................................ 56
9.7
AC Electrical Characteristics (cont’d) ........................................................................... 57
9.8
Serial Output Timing ..................................................................................................... 58
9.9
Serial Input Timing ........................................................................................................ 58
9.10 Hold Timing ................................................................................................................... 58
9.11 WP Timing .................................................................................................................... 58
PACKAGE SPECIFICATION .................................................................................................... 59
10.1 8-Pin SOIC 150-mil (Package Code SN) ...................................................................... 59
10.2 8-Pin VSOP8 150-mil (Package Code SV) ................................................................... 60
10.3 8-Pad 6x5mm WSON (Package Code ZP) .................................................................. 61
10.4 8-Pad WSON 6x5mm Cont’d. ....................................................................................... 62
-3-
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
11.
12.
10.5 8-Pad USON 2x3-mm (Package Code UX) .................................................................. 63
ORDERING INFORMATION..................................................................................................... 64
11.1 Valid Part Numbers and Top Side Marking .................................................................. 65
REVISION HISTORY ................................................................................................................ 66
-4-
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
1. GENERAL DESCRIPTION
The W25Q20CL (2M-bit) Serial Flash memories provide a storage solution for systems with limited
space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial
Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad
SPI (XIP) and storing voice, text and data. The device operates on a single 2.3V to 3.6V power
supply with current consumption as low as 1mA active and 1µA for power-down. All devices are
offered in space-saving packages.
The W25Q20CL array are organized into 1,024 programmable pages of 256-bytes each. Up to 256
bytes can be programmed at a time. The W25Q20CL have 64 erasable sectors, 8 erasable 32KB
blocks and 4 erasable 64KB blocks respectively. The small 4KB sectors allow for greater flexibility in
applications that require data and parameter storage. (See figure 2.)
The W25Q20CL support the standard Serial Peripheral Interface (SPI), and a high performance
Dual/Quad output as well as Dual/Quad I/O SPI: Serial Clock, Chip Select, Serial Data I/O0 (DI),
I/O1 (DO), I/O2 (/WP), and I/O3 (/HOLD). SPI clock frequencies of up to 104MHz are supported
allowing equivalent clock rates of 208MHz (104MHz x 2) for Dual I/O and 416MHz (104MHz x 4) for
Quad I/O when using the Fast Read Dual/Quad I/O instructions. These transfer rates can outperform
standard Asynchronous 8 and 16-bit Parallel Flash memories. The Continuous Read Mode allows
for efficient memory access with as few as 8-clocks of instruction-overhead to read a 24-bit address,
allowing true XIP (execute in place) operation.
A Hold pin, Write Protect pin and programmable write protect, with top, bottom or complement array
control, provide further control flexibility. Additionally, the device supports JEDEC standard
manufacturer and device identification with a 64-bit Unique Serial Number.
2. FEATURES
 Family of SpiFlash Memories
– W25Q20CL: 2M-bit/256K -byte (262,144)
– 256-byte per programmable page
– Uniform 4KB Sectors, 32KB & 64KB Blocks
 Software and Hardware Write Protection
– Write-Protect all or portion of memory
– Enable/Disable protection with /WP pin
– Top or bottom array protection
 SPI with Single / Dual Outputs / I/O
 Flexible Architecture with 4KB sectors
– Standard SPI: CLK, /CS, DI, DO, /WP, /Hold
– Uniform Sector/Block Erase (4/32/64-kbytes)
– Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold
– Program one to 256 bytes < 1ms
– Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3
– Erase/Program Suspend & Resume
– More than 100,000 erase/write cycles
 Data Transfer up to 480M-bits / second
– More than 20-year data retention
– Clock operation to 104MHz.
– 208/416MHz equivalent Dual/Quad SPI
 Low Power, Wide Temperature Range
– Auto-increment Read capability.
– Single 2.3 to 3.6V supply
– 1mA active current, <1µA Power-down(typ.)
 Efficient “Continuous Read Mode”
– -40°C to +85°C operating range
– Low Instruction overhead
– Continous Read
 Space Efficient Packaging
– As few as 8 clocks to address memory
– 8-pin SOIC 150-mil \ VSOP 150-mil
– Allows true XIP operation
– 8-pad WSON 6x5-mm
– 8-pad USON 2x3-mm
– Contact Winbond for KGD and other options
-5-
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
3.
PIN CONFIGURATION SOIC 150-MIL AND VSOP 150-MIL
Figure 1a. W25Q20CL Pin Assignments, 8-pin SOIC 150-mil and VSOP 150-mil (Package Code SN & SV)
4.
PAD CONFIGURATION WSON 6X5-MM AND USON 2X3-MM
Figure 1b. W25Q20CL Pad Assignments, 8-pad WSON 6x5-mm and USON 2x3-mm (Package Code ZP & UX)
5.
PIN DESCRIPTION SOIC/ VSOP 150-MIL, WSON 5X6-MM AND USON 2X3-MM
PIN NO.
PIN NAME
I/O
FUNCTION
1
/CS
I
2
DO (IO1)
I/O
Data Output (Data Input Output 1)(1) (2)
3
/WP (IO2)
I/O
Write Protect Input ( Data Input Output 2) (2)
4
GND
5
DI (IO0)
I/O
6
CLK
I
7
/HOLD (IO3)
I/O
8
VCC
Chip Select Input
Ground
Data Input (Data Input Output 0) (1) (2)
Serial Clock Input
Hold Input (Data Input Output 3) (2)
Power Supply
Note:
1 IO0 and IO1 are used for Standard and Dual SPI instructions
2 IO0 – IO3 are used for Quad SPI instructions
- 6 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
5.1
Package Types
W25Q20CL are offered in an 8-pin plastic 150-mil width SOIC (package code SN), 150-mil width
VSOP (package code SV), 6x5-mm WSON (package code ZP) and 2x3-mm USON (package code
UX). Refer to see figures 1a and 1b, respectively.
5.2 Chip Select (/CS)
The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is
deselected and the Serial Data Output (DO, or IO0, IO1, IO2, IO3) pins are at high impedance. When
deselected, the devices power consumption will be at standby levels unless an internal erase,
program or write status register cycle is in progress. When /CS is brought low the device will be
selected, power consumption will increase to active levels and instructions can be written to and data
read from the device. After power-up, /CS must transition from high to low before a new instruction will
be accepted. The /CS input must track the VCC supply level at power-up (see “Power-up Timing and
Write inhibit threshold” and figure 35). If needed, a pull-up resister on /CS can be used to accomplish
this.
5.3 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3)
The W25Q20CL support standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions
use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the
rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output)
to read data or status from the device on the falling edge of CLK.
Dual and Quad SPI instructions use the bidirectional IO pins to serially write instructions, addresses or
data to the device on the rising edge of CLK and read data or status from the device on the falling
edge of CLK. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register 2
to be set. When QE=1, the /WP pin becomes IO2 and /HOLD pin becomes IO3.
5.4 Write Protect (/WP)
The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect (CMP, SEC, TB, BP2, BP1 and BP0) bits and
Status Register Protect (SRP0) bits, a portion as small as 4KB sector or the entire memory array can
be hardware protected. The /WP pin is active low. When the QE bit of Status Register-2 is set for
Quad I/O, the /WP pin function is not available since this pin is used for IO2.
5.5 HOLD (/HOLD)
The /HOLD pin allows the device to be paused while it is actively selected. When /HOLD is brought
low, while /CS is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be
ignored (don’t care). When /HOLD is brought high, device operation can resume. The /HOLD function
can be useful when multiple devices are sharing the same SPI signals. The /HOLD pin is active low.
When the QE bit of Status Register-2 is set for Quad I/O, the /HOLD pin function is not available since
this pin is used for IO3. See figure 1a and 1b for the pin configuration of Quad I/O operation.
5.6 Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations.
- 7 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
6. BLOCK DIAGRAM
Figure 2. W25Q20CL Serial Flash Memory Block Diagram
- 8 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
7.
FUNCTIONAL DESCRIPTION
7.1 SPI OPERATIONS
7.1.1 Standard SPI Instructions
The W25Q20CL are accessed through an SPI compatible bus consisting of four signals: Serial Clock
(CLK), Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI
instructions use the DI input pin to serially write instructions, addresses or data to the device on the
rising edge of CLK. The DO output pin is used to read data or status from the device on the falling
edge CLK.
SPI bus operation Modes 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0
and Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and
data is not being transferred to the Serial Flash. For Mode 0 the CLK signal is normally low on the
falling and rising edges of /CS. For Mode 3 the CLK signal is normally high on the falling and rising
edges of /CS.
7.1.2 Dual SPI Instructions
The W25Q20CL support Dual SPI operation when using the “Fast Read Dual Output (3Bh)” and “Fast
Read Dual I/O (BBh)” instructions. These instructions allow data to be transferred to or from the device
at two to three times the rate of ordinary Serial Flash devices. The Dual SPI Read instructions are
ideal for quickly downloading code to RAM upon power-up (code-shadowing) or for executing nonspeed-critical code directly from the SPI bus (XIP). When using Dual SPI instructions, the DI and DO
pins become bidirectional I/O pins: IO0 and IO1.
7.1.3 Quad SPI Instructions
The W25Q20CL support Quad SPI operation when using the “Fast Read Quad Output (6Bh)”, “Fast
Read Quad I/O (EBh)” instructions. These instructions allow data to be transferred to or from the
device six to eight times the rate of ordinary Serial Flash. The Quad Read instructions offer a
significant improvement in continuous and random access transfer rates allowing fast code-shadowing
to RAM or execution directly from the SPI bus (XIP). When using Quad SPI instructions the DI and DO
pins become bidirectional IO0 and IO1, and the /WP and /HOLD pins become IO2 and IO3
respectively. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register 2
to be set.
7.1.4 Hold Function
For Standard SPI and Dual SPI operations, the /HOLD signal allows the W25Q20CL operation to be
paused while it is actively selected (when /CS is low). The /HOLD function may be useful in cases
where the SPI data and clock signals are shared with other devices. For example, consider if the page
buffer was only partially written when a priority interrupt requires use of the SPI bus. In this case the
/HOLD function can save the state of the instruction and the data in the buffer so programming can
resume where it left off once the bus is available again. The /HOLD function is only available for
standard SPI and Dual SPI operation, not during Quad SPI.
- 9 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will
activate on the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not
already low the /HOLD condition will activate after the next falling edge of CLK. The /HOLD condition
will terminate on the rising edge of the /HOLD signal if the CLK signal is already low. If the CLK is not
already low the /HOLD condition will terminate after the next falling edge of CLK. During a /HOLD
condition, the Serial Data Output (DO) is high impedance, and Serial Data Input (DI) and Serial Clock
(CLK) are ignored. The Chip Select (/CS) signal should be kept active low for the full duration of the
/HOLD operation to avoid resetting the internal logic state of the device.
7.2
WRITE PROTECTION
Applications that use non-volatile memory must take into consideration the possibility of noise and
other adverse system conditions that may compromise data integrity. To address this concern, the
W25Q20CL provide several means to protect the data from inadvertent writes.
7.2.1 Write Protect Features
 Device resets when VCC is below threshold
 Time delay write disable after Power-up
 Write enable/disable instructions
 Automatic write disable after erase or program
 Software and Hardware (/WP pin) write protection using Status Register
 Write Protection using Power-down instruction
 Lock Down write protection until next power-up

One Time Program (OTP) write protection
*
* Note: This feature is available upon special order. Please contact Winbond for details.
Upon power-up or at power-down, the W25Q20CL will maintain a reset condition while VCC is below
the threshold value of VWI, (See Power-up Timing and Voltage Levels and Figure 35). While reset, all
operations are disabled and no instructions are recognized. During power-up and after the VCC
voltage exceeds VWI, all program and erase related instructions are further disabled for a time delay of
tPUW. This includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and the
Write Status Register instructions. Note that the chip select pin (/CS) must track the VCC supply level
at power-up until the VCC-min level and tVSL time delay is reached. If needed, a pull-up resister on
/CS can be used to accomplish this.
After power-up the device is automatically placed in a write-disabled state with the Status Register
Write Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page
Program, Sector Erase, Block Erase, Chip Erase or Write Status Register instruction will be accepted.
After completing a program, erase or write instruction the Write Enable Latch (WEL) is automatically
cleared to a write-disabled state of 0.
Software controlled write protection is facilitated using the Write Status Register instruction and setting
the Status Register Protect (SRP0, SRP1) and Block Protect (CMP, SEC,TB, BP2, BP1 and BP0) bits.
These settings allow a portion as small as 4KB sector or the entire memory array to be configured as
read only. Used in conjunction with the Write Protect (/WP) pin, changes to the Status Register can be
enabled or disabled under hardware control. See Status Register section for further information.
Additionally, the Power-down instruction offers an extra level of write protection as all instructions are
ignored except for the Release Power-down instruction.
- 10 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
8.
CONTROL AND STATUS REGISTERS
The Read Status Register-1 and Status Register-2 instructions can be used to provide status on the
availability of the Flash memory array, if the device is write enabled or disabled, the state of write
protection, Quad SPI setting, Security Register lock status and Erase/Program Suspend status. The
Write Status Register instruction can be used to configure the device write protection features, Quad SPI
setting and Security Register OTP lock. Write access to the Status Register is controlled by the state of
the non-volatile Status Register Protect bits (SRP0, SRP1), the Write Enable instruction, and during
Standard/Dual SPI operations, the /WP pin.
8.1
STATUS REGISTER
8.1.1 BUSY
BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing
a Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register
or Erase/Program Security Register instruction. During this time the device will ignore further
instructions except for the Read Status Register and Erase/Program Suspend instruction (see tW, tPP,
tSE, tBE, and tCE in AC Characteristics). When the program, erase or write status/security register
instruction has completed, the BUSY bit will be cleared to a 0 state indicating the device is ready for
further instructions.
8.1.2 Write Enable Latch (WEL)
Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to 1 after executing a
Write Enable Instruction. The WEL status bit is cleared to 0 when the device is write disabled. A write
disable state occurs upon power-up or after any of the following instructions finished: Write Disable,
Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register,
Erase Security Register and Program Security Register.
8.1.3 Block Protect Bits (BP2, BP1, BP0)
The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register (S4, S3,
and S2) that provide Write Protection control and status. Block Protect bits can be set using the Write
Status Register Instruction (see tW in AC characteristics). All, none or a portion of the memory array
can be protected from Program and Erase instructions (see Status Register Memory Protection table).
The factory default setting for the Block Protection Bits is 0, none of the array protected.
8.1.4 Top/Bottom Block Protect (TB)
The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect from
the Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection
table. The factory default setting is TB=0. The TB bit can be set with the Write Status Register
Instruction depending on the state of the SRP0, SRP1 and WEL bits.
8.1.5 Sector/Block Protect (SEC)
The non-volatile Sector/Block Protect bit (SEC) controls if the Block Protect Bits (BP2, BP1, BP0)
protect either 4KB Sectors (SEC=1) or 64KB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1)
of the array as shown in the Status Register Memory Protection table. The default setting is SEC=0.
- 11 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
8.1.6 Complement Protect (CMP)
The Complement Protect bit (CMP) is a non-volatile read/write bit in the status register (S14). It is
used in conjunction with SEC, TB, BP2, BP1 and BP0 bits to provide more flexibility for the array
protection. Once CMP is set to 1, previous array protection set by SEC, TB, BP2, BP1 and BP0 will be
reversed. For instance, when CMP=0, a top 4KB sector can be protected while the rest of the array is
not; when CMP=1, the top 4KB sector will become unprotected while the rest of the array become
read-only. Please refer to the Status Register Memory Protection table for details. The default setting
is CMP=0.
8.1.7 Status Register Protect (SRP1, SRP0)
The Status Register Protect bits (SRP1 and SRP0) are non-volatile read/write bits in the status
register (S8 and S7). The SRP bits control the method of write protection: software protection,
hardware protection, power supply lock-down or one time programmable (OTP) protection.
SRP1
SRP0
/WP
Status
Register
Description
0
0
X
Software
Protection
/WP pin has no control. The Status register can be written to
after a Write Enable instruction, WEL=1. [Factory Default]
0
1
0
Hardware
Protected
When /WP pin is low the Status Register locked and can not
be written to.
0
1
1
Hardware
Unprotected
When /WP pin is high the Status register is unlocked and can
be written to after a Write Enable instruction, WEL=1.
1
0
X
Power Supply
Lock-Down
1
1
X
One Time
Program(2)
Status Register is protected and can not be written to again
until the next power-down, power-up cycle.(1)
Status Register is permanently protected and can not be
written to.
Note:
1. When SRP1, SRP0 = (1, 0), a power-down, power-up cycle will change SRP1, SRP0 to (0, 0) state.
2. This feature is available upon special order. Please contact Winbond for details.
8.1.8 Erase/Program Suspend Status (SUS)
The Suspend Status bit is a read only bit in the status register (S15) that is set to 1 after executing a
Erase/Program Suspend (75h) instruction. The SUS status bit is cleared to 0 by Erase/Program
Resume (7Ah) instruction as well as a power-down, power-up cycle.
8.1.9 Security Register Lock Bits (LB3, LB2, LB1, LB0)
The Security Register Lock Bits (LB3, LB2, LB1, LB0) are non-volatile One Time Program (OTP) bits
in Status Register (S13, S12, S11, S10) that provide the write protect control and status to the
Security Registers. The default state of LB3-0 is 0, Security Registers are unlocked. LB3-0 can be set
to 1 individually using the Write Status Register instruction. LB3-0 are One Time Programmable
(OTP), once it’s set to 1, the corresponding 256-Byte Security Register will become read-only
permanently.
- 12 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
8.1.10
Quad Enable (QE)
The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows Quad
SPI operation. When the QE bit is set to a 0 state (factory default), the /WP pin and /HOLD are
enabled. When the QE bit is set to a 1, the Quad IO2 and IO3 pins are enabled.
WARNING: The QE bit should never be set to a 1 during standard SPI or Dual SPI operation if the /WP or /HOLD pins
are tied directly to the power supply or ground.
S7
SRP0
S6
SEC
S5
TB
S4
S3
S3
S2
S2
S1
S1
S0
S0
BP2
BP 1
BP0
WEL
BUSY
STATUS REGISTER PROTECT0
(Non-volatile)
SECTOR PROTECT
(Non-volatile)
TOP/BOTTOM PROTECT
(Non-volatile)
BLOCK PROTECT BITS
(Non-volatile)
WRITE ENABLE LATCH
ERASE/WRITE IN PROGRESS
(volatile)
Figure 3a. Status Register-1
S15
S14
S13
S12
S11
S10
S9
S8
SUS
CMP
LB3
LB2
LB1
LB0
QE
SRP1
SUSPEND STATUS
COMPLEMENT PROTECT
(Non-volatile)
SECURITY REGISTER LOCK BITS
(Non-Volatile OPT)
QUAD ENABLE
(Non-volatile)
STATUS REGISTER PROTECT 2
(Non-volatile)
Figure 3b. Status Register-2
- 13 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
8.1.11
2M-BIT Status Register Memory Protection (CMP = 0)
STATUS REGISTER(1)
W25Q20CL 2M-BIT MEMORY PROTECTED(2)
SEC
TB
BP2
BP1
BP0
BLOCK(S)
ADDRESSES
DENSITY
PORTION
0
0
0
X
0
0
X
X
X
0
0
1
0
1
0
NONE
3
2 and 3
NONE
030000h – 03FFFFh
020000h – 03FFFFh
NONE
64KB
128KB
NONE
Upper 1/4
Upper 1/2
0
0
0
1
1
X
X
X
X
0
1
1
1
0
1
0
0 and 1
0 thru 3
000000h – 00FFFFh
000000h – 01FFFFh
000000h – 03FFFFh
64KB
128KB
256KB
Lower 1/4
Lower 1/2
ALL
1
1
1
1
1
1
X
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
X
0
NONE
3
3
3
3
3
NONE
03F000h – 03FFFFh
03E000h – 03FFFFh
03C000h – 03FFFFh
038000h – 03FFFFh
038000h – 03FFFFh
NONE
4KB
8KB
16KB
32KB
32KB
NONE
Upper 1/64
Upper 1/32
Upper 1/16
Upper 1/8
Upper 1/8
1
1
1
1
1
1
1
1
1
1
1
X
0
0
0
1
1
1
0
1
1
0
1
1
1
0
1
X
0
1
0
0
0
0
0
0 thru 3
000000h – 000FFFh
000000h – 001FFFh
000000h – 003FFFh
000000h – 007FFFh
000000h – 007FFFh
000000h – 03FFFFh
4KB
8KB
16KB
32KB
32KB
256KB
Lower 1/64
Lower 1/32
Lower 1/16
Lower 1/8
Lower 1/8
ALL
- 14 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
8.1.12
2M-BIT Status Register Memory Protection (CMP = 1)
STATUS REGISTER(1)
W25Q20CL 2M-BIT MEMORY PROTECTED(2)
SEC
TB
BP2
BP1
BP0
BLOCK(S)
ADDRESSES
DENSITY
PORTION
0
0
0
X
0
0
X
X
X
0
0
1
0
1
0
0 thru 3
0 thru 2
0 and 1
000000h – 03FFFFh
000000h – 02FFFFh
000000h – 01FFFFh
256KB
192KB
128KB
ALL
Lower 3/4
Lower 1/2
0
0
0
1
1
X
X
X
X
0
1
1
1
0
1
1 thru 3
2 and 3
NONE
010000h – 03FFFFh
020000h – 03FFFFh
NONE
192KB
128KB
NONE
Upper 3/4
Upper 1/2
NONE
1
1
1
1
1
1
X
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
X
0
0 thru 3
0 thru 3
0 thru 3
0 thru 3
0 thru 3
0 thru 3
000000h – 03FFFFh
000000h – 03EFFFh
000000h – 03DFFFh
000000h – 03BFFFh
000000h – 037FFFh
000000h – 037FFFh
256KB
252KB
248KB
240KB
224KB
224KB
ALL
Lower 63/64
Lower 31/32
Lower 15/16
Lower 7/8
Lower 7/8
1
1
1
1
1
1
1
1
1
1
1
X
0
0
0
1
1
1
0
1
1
0
1
1
1
0
1
X
0
1
0 thru 3
0 thru 3
0 thru 3
0 thru 3
0 thru 3
NONE
001000h – 03FFFFh
002000h – 03FFFFh
004000h – 03FFFFh
008000h – 03FFFFh
008000h – 03FFFFh
NONE
252KB
248KB
240KB
224KB
224KB
NONE
Upper 63/64
Upper 31/32
Upper 15/16
Upper 7/8
Upper 7/8
NONE
- 15 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
8.2
INSTRUCTIONS
The instruction set of the W25Q20CL consists of thirty three basic instructions that are fully controlled
through the SPI bus (see Instruction Set table). Instructions are initiated with the falling edge of Chip
Select (/CS). The first byte of data clocked into the DI input provides the instruction code. Data on the
DI input is sampled on the rising edge of clock with most significant bit (MSB) first.
Instructions vary in length from a single byte to several bytes and may be followed by address bytes,
data bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed
with the rising edge of edge /CS. Clock relative timing diagrams for each instruction are included in
figures 4 through 34. All read instructions can be completed after any clocked bit. However, all
instructions that Write, Program or Erase must complete on a byte boundary (/CS driven high after a
full 8-bits have been clocked) otherwise the instruction will be ignored. This feature further protects the
device from inadvertent writes. Additionally, while the memory is being programmed or erased, or
when the Status Register is being written, all instructions except for Read Status Register will be
ignored until the program or erase cycle has completed.
8.2.1 Manufacturer and Device Identification
MANUFACTURER ID
(MF7-MF0)
Winbond Serial Flash
EFh
Device ID
(ID7-ID0)
(ID15-ID0)
Instruction
ABh, 90h, 92h, 94h
9Fh
W25Q20CL
11h
4012h
- 16 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
8.2.2 Instruction Set Table 1 (Erase, Program Instructions)(1)
INSTRUCTION NAME
BYTE 1
(CODE)
BYTE 2
BYTE 3
BYTE 4
BYTE 5
Write Enable
06h
Write Enable for
Volatile Status Register
50h
Write Disable
04h
Read Status Register-1
05h
(S7–S0)
Read Status Register-2
35h
(S15–S8)
Write Status Register
01h
S7–S0
S15-S8
Page Program
02h
A23–A16
A15–A8
A7–A0
D7–D0
Quad Page Program
32h
A23–A16
A15–A8
A7–A0
D7–D0, …
Sector Erase (4KB)
20h
A23–A16
A15–A8
A7–A0
Block Erase (32KB)
52h
A23–A16
A15–A8
A7–A0
Block Erase (64KB)
D8h
A23–A16
A15–A8
A7–A0
Chip Erase
75h
Erase / Program Resume
7Ah
Power-down
B9h
Continuous Read Mode
(4)
(2)
(2)
(3)
C7h/60h
Erase / Program Suspend
Reset
BYTE 6
FFh
FFh
Notes:
1.
Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “()” indicate data being read from
the device on the DO pin.
2.
The Status Register contents will repeat continuously until /CS terminates the instruction.
3.
Quad Page Program Input Data:
IO0 = D4, D0, ……
IO1 = D5, D1, ……
IO2 = D6, D2, ……
IO3 = D7, D3, ……
4.
This instruction is recommended when using the Dual or Quad “Continuous Read Mode” feature. See section 8.2.19 &
8.2.20 for more information.
- 17 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
8.2.3 Instruction Set Table 2 (Read Instructions)
BYTE 1
(CODE)
BYTE 2
BYTE 3
BYTE 4
BYTE 5
Read Data
03h
A23-A16
A15-A8
A7-A0
(D7-D0)
Fast Read
0Bh
A23-A16
A15-A8
A7-A0
dummy
Fast Read Dual Output
3Bh
A23-A16
A15-A8
A7-A0
dummy
(D7-D0, …)
Fast Read Quad Output
6Bh
A23-A16
A15-A8
A7-A0
dummy
(D7-D0, …)
Fast Read Dual I/O
BBh
A23-A8
Fast Read Quad I/O
EBh
A23-A0, M7-M0
Set Burst with Wrap
77h
xxxxxx, W6-W4
INSTRUCTION NAME
(2)
A7-A0, M7-M0
(4)
(2)
BYTE 6
(D7-D0)
(1)
(1)
(D7-D0, …)
(5)
(x,x,x,x, D7-D0,…)
(3)
(D7-D0, …)
(4)
Notes:
1. Dual Output data
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
2. Dual Input Address
IO0 = A22, A20, A18, A16, A14, A12, A10, A8
IO1 = A23, A21, A19, A17, A15, A13, A11, A9
A6, A4, A2, A0, M6, M4, M2, M0
A7, A5, A3, A1, M7, M5, M3, M1
3. Quad Output Data
IO0 = (D4, D0, …..)
IO1 = (D5, D1, …..)
IO2 = (D6, D2, …..)
IO3 = (D7, D3, …..)
4. Quad Input Address
Set Burst with Wrap Input
IO0 = A20, A16, A12, A8, A4, A0, M4, M0
IO1 = A21, A17, A13, A9, A5, A1, M5, M1
IO2 = A22, A18, A14, A10, A6, A2, M6, M2
IO3 = A23, A19, A15, A11, A7, A3, M7, M3
IO0 = x, x, x, x, x, x, W4, x
IO1 = x, x, x, x, x, x, W5, x
IO2 = x, x, x, x, x, x, W6, x
IO3 = x, x, x, x, x, x, x, x
5. Fast Read Quad I/O Data
IO0 = (x, x, x, x, D4, D0, …..)
IO1 = (x, x, x, x, D5, D1, …..)
IO2 = (x, x, x, x, D6, D2, …..)
IO3 = (x, x, x, x, D7, D3, …..)
6. Word Read Quad I/O Data
IO0 = (x, x, D4, D0, …..)
IO1 = (x, x, D5, D1, …..)
IO2 = (x, x, D6, D2, …..)
IO3 = (x, x, D7, D3, …..)
7. The lowest address bit must be 0. ( A0 = 0 )
8. The lowest 4 address bits must be 0. ( A0, A1, A2, A3 = 0 )
- 18 -
Publication Release Date: August 06, 2013
Revision A1
(3)
W25Q20CL
8.2.4 Instruction Set Table 3 (ID, Security Instructions)
INSTRUCTION
NAME
Release Power down/
Device ID
Manufacturer/
Device ID
(2)
Manufacturer/Device ID
by Dual I/O
Manufacture/Device ID
by Quad I/O
BYTE 1
(CODE)
BYTE 2
BYTE 3
BYTE 4
ABh
dummy
dummy
dummy
90h
dummy
dummy
00h
92h
A23-A8
A7-A0, M[7:0]
(MF[7:0], ID[7:0])
94h
A23-A0, M[7:0]
xxxx, (MF[7:0], ID[7:0])
(MF[7:0], ID[7:0], …)
(MF7-MF0)
(ID7-ID0)
dummy
(ID63-ID0)
(ID15-ID8)
(ID7-ID0)
Memory Type
Capacity
4Bh
dummy
dummy
dummy
(3)
44h
A23–A16
A15–A8
A7–A0
(3)
42h
A23–A16
A15–A8
A7–A0
D7-D0
D7-D0
(3)
48h
A23–A16
A15–A8
A7–A0
dummy
(D7-0)
Read Unique ID
Erase
Program
Read
Security Registers
(1)
(ID7-ID0)
(MF7-MF0)
9Fh
Security Registers
BYTE 6
Manufacturer
JEDEC ID
Security Registers
BYTE 5
Notes:
1. The Device ID will repeat continuously until /CS terminates the instruction.
2. See Manufacturer and Device Identification table for Device ID information.
3. Security Register Address:
Security Register 0:
Security Register 1:
Security Register 2:
Security Register 3:
A23-16 = 00h;
A23-16 = 00h;
A23-16 = 00h;
A23-16 = 00h;
A15-8 = 00h;
A15-8 = 10h;
A15-8 = 20h;
A15-8 = 30h;
A7-0 = byte address
A7-0 = byte address
A7-0 = byte address
A7-0 = byte address
Please note that Security Register 0 is Reserved by Winbond for future use. It is recommended to use Security registers 13 before using register 0.
- 19 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
8.2.5 Write Enable (06h)
The Write Enable instruction (Figure 4) sets the Write Enable Latch (WEL) bit in the Status Register to
a 1. The WEL bit must be set prior to every Page Program, Quad Page Program, Sector Erase, Block
Erase, Chip Erase, Write Status Register and Erase/Program Security Registers instruction. The Write
Enable instruction is entered by driving /CS low, shifting the instruction code “06h” into the Data Input
(DI) pin on the rising edge of CLK, and then driving /CS high.
/CS
Mode 3
CLK
0
1
2
3
4
5
6
7
Mode 0
Mode 3
Mode 0
Instruction (06h)
DI
(IO0)
DO
(IO1)
High Impedance
Figure 4. Write Enable Instruction Sequence Diagram
8.2.6 Write Enable for Volatile Status Register (50h)
The non-volatile Status Register bits described in section 8.1 can also be written to as volatile bits.
This gives more flexibility to change the system configuration and memory protection schemes quickly
without waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status
Register non-volatile bits. To write the volatile values into the Status Register bits, the Write Enable for
Volatile Status Register (50h) instruction must be issued prior to a Write Status Register (01h)
instruction. Write Enable for Volatile Status Register instruction (Figure 5) will not set the Write Enable
Latch (WEL) bit, it is only valid for the Write Status Register instruction to change the volatile Status
Register bit values.
Instruction (50h)
Figure 5. Write Enable for Volatile Status Register Instruction Sequence Diagram
- 20 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
8.2.7 Write Disable (04h)
The Write Disable instruction (Figure 6) resets the Write Enable Latch (WEL) bit in the Status Register
to a 0. The Write Disable instruction is entered by driving /CS low, shifting the instruction code “04h”
into the DI pin and then driving /CS high. Note that the WEL bit is automatically reset after Power-up
and upon completion of the Write Status Register. Erase/Program Security Registers, Page Program,
Quad Page Program, Sector Erase, Block Erase and Chip Erase instructions. Write Disable instruction
can also be used to invalidate the Write Enable for Volatile Status Register instruction
Figure 6. Write Disable Instruction Sequence Diagram
8.2.8 Read Status Register-1 (05h) and Read Status Register-2 (35h)
The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction is
entered by driving /CS low and shifting the instruction code “05h” for Status Register-1 or “35h” for
Status Register-2 into the DI pin on the rising edge of CLK. The status register bits are then shifted out
on the DO pin at the falling edge of CLK with most significant bit (MSB) first as shown in figure 7. The
Status Register bits are shown in figure 3a and 3b and include the BUSY, WEL, BP2-BP0, TB, SEC,
SRP0, SRP1, QE, LB3-0, CMP and SUS bits (see Status Register section earlier in this datasheet).
The Read Status Register instruction may be used at any time, even while a Program, Erase or Write
Status Register cycle is in progress. This allows the BUSY status bit to be checked to determine when
the cycle is complete and if the device can accept another instruction. The Status Register can be
read continuously, as shown in Figure 7. The instruction is completed by driving /CS high.
Figure 7. Read Status Register Instruction Sequence Diagram
- 21 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
8.2.9 Write Status Register (01h)
The Write Status Register instruction allows the Status Register to be written. Only non-volatile Status
Register bits SRP0, SEC, TB, BP2, BP1, BP0 (bits 7 thru 2 of Status Register-1) and CMP, LB3, LB2,
LB1, LB0, QE, SRP1 (bits 14 thru 8 of Status Register-2) can be written to. All other Status Register
bit locations are read-only and will not be affected by the Write Status Register instruction. LB3-0 are
non-volatile OTP bits, once it is set to 1, it cannot be cleared to 0. The Status Register bits are shown
in figure 3 and described in 10.1.
To write non-volatile Status Register bits, a standard Write Enable (06h) instruction must previously
have been executed for the device to accept the Write Status Register Instruction (Status Register bit
WEL must equal 1). Once write enabled, the instruction is entered by driving /CS low, sending the
instruction code “01h”, and then writing the status register data byte as illustrated in figure 8.
To write volatile Status Register bits, a Write Enable for Volatile Status Register (50h) instruction must
have been executed prior to the Write Status Register instruction (Status Register bit WEL remains 0).
However, SRP1 and LB3, LB2, LB1, LB0 cannot be changed from “1” to “0” because of the OTP
protection for these bits. Upon power off, the volatile Status Register bit values will be lost, and the
non-volatile Status Register bit values will be restored when power on again.
To complete the Write Status Register instruction, the /CS pin must be driven high after the eighth or
sixteenth bit of data that is clocked in. If this is not done the Write Status Register instruction will not
be executed. If /CS is driven high after the eighth clock (compatible with the 25X series) the CMP, QE
and SRP1 bits will be cleared to 0.
During non-volatile Status Register write operation (06h combined with 01h), after /CS is driven high,
the self-timed Write Status Register cycle will commence for a time duration of tW (See AC
Characteristics). While the Write Status Register cycle is in progress, the Read Status Register
instruction may still be accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the
Write Status Register cycle and a 0 when the cycle is finished and ready to accept other instructions
again. After the Write Status Register cycle has finished, the Write Enable Latch (WEL) bit in the
Status Register will be cleared to 0.
During volatile Status Register write operation (50h combined with 01h), after /CS is driven high, the
Status Register bits will be refreshed to the new values within the time period of tSHSL2 (See AC
Characteristics). BUSY bit will remain 0 during the Status Register bit refresh period.
Please refer to 10.1 for detailed Status Register Bit descriptions. Factory default for all status Register
bits are 0.
/CS
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Mode 0
Mode 0
Instruction (01h)
DI
(IO0)
Mode 3
Status Register 1 in
7
6
5
4
3
*
2
Status Register 2 in
1
0
15
14
13
12
11
10
9
8
*
High Impedance
DO
(IO1)
* = MSB
Figure 8. Write Status Register Instruction Sequence Diagram
- 22 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
8.2.10
Read Data (03h)
The Read Data instruction allows one or more data bytes to be sequentially read from the memory.
The instruction is initiated by driving the /CS pin low and then shifting the instruction code “03h”
followed by a 24-bit address (A23-A0) into the DI pin. The code and address bits are latched on the
rising edge of the CLK pin. After the address is received, the data byte of the addressed memory
location will be shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first.
The address is automatically incremented to the next higher address after each byte of data is shifted
out allowing for a continuous stream of data. This means that the entire memory can be accessed with
a single instruction as long as the clock continues. The instruction is completed by driving /CS high.
The Read Data instruction sequence is shown in figure 9. If a Read Data instruction is issued while an
Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any
effects on the current cycle. The Read Data instruction allows clock rates from D.C. to a maximum of
fR (see AC Electrical Characteristics).
/CS
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
10
28
29
30
31
32
33
34
35
36
37
38
39
Mode 0
Instruction (03h)
24-Bit Address
DI
(IO0)
23
22
21
3
2
1
0
*
High Impedance
DO
(IO1)
*
Data Out 1
7
6
5
4
3
2
1
0
7
*
= MSB
Figure 9. Read Data Instruction Sequence Diagram
- 23 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
8.2.11
Fast Read (0Bh)
The Fast Read instruction is similar to the Read Data instruction except that it can operate at the
highest possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding
eight “dummy” clocks after the 24-bit address as shown in figure 10. The dummy clocks allow the
devices internal circuits additional time for setting up the initial address. During the dummy clocks the
data value on the DO pin is a “don’t care”.
/CS
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
10
28
29
30
31
Mode 0
Instruction (0Bh)
24-Bit Address
DI
(IO0)
23
22
21
42
43
3
2
1
0
45
46
47
48
*
High Impedance
DO
(IO1)
* = MSB
/CS
31
32
33
34
35
36
37
38
39
40
41
44
49
50
51
52
53
54
55
CLK
Dummy Clocks
DI
(IO0)
DO
(IO1)
0
High Impedance
Data Out 1
7
6
5
*
4
3
Data Out 2
2
1
0
7
6
5
4
3
2
1
0
7
*
Figure 10. Fast Read Instruction Sequence Diagram
- 24 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
8.2.12
Fast Read Dual Output (3Bh)
The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction
except that data is output on two pins, IO0 and IO1. This allows data to be transferred from the
W25Q20CL at twice the rate of standard SPI devices. The Fast Read Dual Output instruction is ideal
for quickly downloading code from Flash to RAM upon power-up or for applications that cache codesegments to RAM for execution.
Similar to the Fast Read instruction, the Fast Read Dual Output instruction can operate at the highest
possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight
“dummy” clocks after the 24-bit address as shown in figure 11. The dummy clocks allow the device's
internal circuits additional time for setting up the initial address. The input data during the dummy
clocks is “don’t care”. However, the IO0 pin should be high-impedance prior to the falling edge of the
first data out clock.
/CS
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
10
28
29
30
31
Mode 0
Instruction (3Bh)
24-Bit Address
DI
(IO0)
23
22
21
42
43
3
2
1
0
45
46
47
48
*
High Impedance
DO
(IO1)
* = MSB
/CS
31
32
33
34
35
36
37
38
39
40
41
44
49
50
51
52
53
54
55
CLK
IO0 switches from
Input to Output
Dummy Clocks
DI
(IO0)
DO
(IO1)
0
6
High Impedance
7
*
4
2
0
6
5
3
1
7
Data Out 1
*
4
2
0
6
5
3
1
7
Data Out 2
*
4
2
0
6
5
3
1
7
Data Out 3
*
4
2
0
6
5
3
1
7
Data Out 4
Figure 11. Fast Read Dual Output Instruction Sequence Diagram
- 25 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
8.2.13
Fast Read Quad Output (6Bh)
The Fast Read Quad Output (6Bh) instruction is similar to the Fast Read Dual Output (3Bh) instruction
except that data is output on four pins, IO0, IO1, IO2, and IO3. A Quad enable of Status Register-2 must
be executed before the device will accept the Fast Read Quad Output Instruction (Status Register bit
QE must equal 1). The Fast Read Quad Output Instruction allows data to be transferred from the
W25Q20CL at four times the rate of standard SPI devices.
The Fast Read Quad Output instruction can operate at the highest possible frequency of FR (see AC
Electrical Characteristics). This is accomplished by adding eight “dummy” clocks after the 24-bit
address as shown in figure 12. The dummy clocks allow the device's internal circuits additional time
for setting up the initial address. The input data during the dummy clocks is “don’t care”. However, the
IO pins should be high-impedance prior to the falling edge of the first data out clock.
Figure 12. Fast Read Quad Output Instruction Sequence Diagram
- 26 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
8.2.14
Fast Read Dual I/O (BBh)
The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO
pins, IO0 and IO1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to
input the Address bits (A23-0) two bits per clock. This reduced instruction overhead may allow for
code execution (XIP) directly from the Dual SPI in some applications.
Fast Read Dual I/O with “Continuous Read Mode”
The Fast Read Dual I/O instruction can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in figure 13a. The
upper nibble of the (M7-4) controls the length of the next Fast Read Dual I/O instruction through the
inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t
care (“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out
clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Dual I/O instruction (after
/CS is raised and then lowered) does not require the BBh instruction code, as shown in figure 13b.
This reduces the instruction sequence by eight clocks and allows the Read address to be immediately
entered after /CS is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the
next instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus
returning to normal operation. A “Continuous Read Mode” Reset instruction can also be used to reset
(M7-0) before issuing normal instructions (See 8.2.20 for detail descriptions).
/CS
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Mode 0
Instruction (BBh)
A23-16
A15-8
A7-0
M7-0
DI
(IO0)
22
20
18
16
14
12
10
8
6
4
2
0
6
4
2
0
DO
(IO1)
23
21
19
17
15
13
11
9
7
5
3
1
7
5
3
1
*
* = MSB
*
/CS
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
CLK
IOs switch from
Input to Output
DI
(IO0)
0
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
6
DO
(IO1)
1
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
7
*
Byte 1
*
Byte 2
*
Byte 3
*
Byte 4
Figure 13a. Fast Read Dual I/O Instruction Sequence (Initial instruction or previous M5-4  10)
- 27 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
/CS
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Mode 0
A23-16
A15-8
A7-0
M7-0
DI
(IO0)
22
20
18
16
14
12
10
8
6
4
2
0
6
4
2
0
DO
(IO1)
23
21
19
17
15
13
11
9
7
5
3
1
7
5
3
1
30
31
*
*
/CS
15
*
= MSB
16
17
18
19
20
21
22
23
24
25
26
27
28
29
CLK
IOs switch from
Input to Output
DI
(IO0)
0
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
6
DO
(IO1)
1
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
7
*
Byte 1
*
Byte 2
*
Byte 3
*
Byte 4
Figure 13b. Fast Read Dual I/O Instruction Sequence (Previous instruction set M5-4 = 10)
- 28 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
8.2.15
Fast Read Quad I/O (EBh)
The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except
that address and data bits are input and output through four pins IO0, IO1, IO2 and IO3 and four Dummy
clock are required prior to the data output. The Quad I/O dramatically reduces instruction overhead
allowing faster random access for code execution (XIP) directly from the Quad SPI. The Quad Enable
bit (QE) of Status Register-2 must be set to enable the Fast Read Quad I/O Instruction.
Fast Read Quad I/O with “Continuous Read Mode”
The Fast Read Quad I/O instruction can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in figure 14a. The
upper nibble of the (M7-4) controls the length of the next Fast Read Quad I/O instruction through the
inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t
care (“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out
clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after
/CS is raised and then lowered) does not require the EBh instruction code, as shown in figure 14b.
This reduces the instruction sequence by eight clocks and allows the Read address to be immediately
entered after /CS is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the
next instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus
returning to normal operation. A “Continuous Read Mode” Reset instruction can also be used to reset
(M7-0) before issuing normal instructions (See 8.2.20 for detail descriptions).
Byte 1
Byte 2
Figure 14a. Fast Read Quad I/O Instruction Sequence (Initial instruction or previous M5-4  10)
- 29 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
Figure 14b. Fast Read Quad I/O Instruction Sequence (Previous instruction set M5-4 = 10)
Fast Read Quad I/O with “8/16/32/64-Byte Wrap Around”
The Fast Read Quad I/O instruction can also be used to access a specific portion within a page by
issuing a “Set Burst with Wrap” command prior to EBh. The “Set Burst with Wrap” command can
either enable or disable the “Wrap Around” feature for the following EBh commands. When “Wrap
Around” is enabled, the data being accessed can be limited to either a 8, 16, 32 or 64-byte section of a
256-byte page. The output data starts at the initial address specified in the instruction, once it reaches
the ending boundary of the 8/16/32/64-byte section, the output will wrap around to the beginning
boundary automatically until /CS is pulled high to terminate the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and
then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple
read commands.
The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to
enable or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap
around section within a page. See 8.2.18 for detail descriptions.
- 30 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
8.2.16
Set Burst with Wrap (77h)
The Set Burst with Wrap (77h) instruction is used in conjunction with “Fast Read Quad I/O” and “Word
Read Quad I/O” instructions to access a fixed length of 8/16/32/64-byte section within a 256-byte
page. Certain applications can benefit from this feature and improve the overall system code
execution performance.
Similar to a Quad I/O instruction, the Set Burst with Wrap instruction is initiated by driving the /CS pin
low and then shifting the instruction code “77h” followed by 24 dummy bits and 8 “Wrap Bits”, W7-0.
The instruction sequence is shown in figure 15. Wrap bit W7 and the lower nibble W3-0 are not used.
W4 = 0
W6, W5
0
0
1
1
W4 =1 (DEFAULT)
Wrap Around
Wrap Length
Wrap Around
Wrap Length
Yes
Yes
Yes
Yes
8-byte
16-byte
32-byte
64-byte
No
No
No
No
N/A
N/A
N/A
N/A
0
1
0
1
Once W6-4 is set by a Set Burst with Wrap instruction, all the following “Fast Read Quad I/O” and
“Word Read Quad I/O” instructions will use the W6-4 setting to access the 8/16/32/64-byte section
within any page. To exit the “Wrap Around” function and return to normal read operation, another Set
Burst with Wrap instruction should be issued to set W4 = 1. The default value of W4 upon power on is
1. In the case of a system Reset while W4 = 0, it is recommended that the controller issues a Set
Burst with Wrap instruction to reset W4 = 1 prior to any normal Read instructions since W25Q20CL
does not have a hardware Reset Pin.
/CS
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Mode 0
Instruction (77h)
IO0
X
X
X
X
X
X
w4
X
IO1
X
X
X
X
X
X
w5
X
IO2
X
X
X
X
X
X
w6
X
IO3
X
X
X
X
X
X
X
X
don’t care don’t care don’t care
wrap bit
Figure 15. Set Burst with Wrap Instruction Sequence
- 31 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
8.2.17
Continuous Read Mode Bits (M7-0)
The “Continuous Read Mode” bits are used in conjunction with “Fast Read Dual I/O”, “Fast Read
Quad I/O”, “Word Read Quad I/O” and “Octal Word Read Quad I/O” instructions to provide the highest
random Flash memory access rate with minimum SPI instruction overhead, thus allow true XIP
(execute in place) to be performed on serial flash devices.
M7-0 need to be set by the Dual/Quad I/O Read instructions. M5-4 are used to control whether the 8bit SPI instruction code (BBh, EBh) is needed or not for the next command. When M5-4 = (1,0), the
next command will be treated same as the current Dual/Quad I/O Read command without needing the
8-bit instruction code; when M5-4 do not equal to (1,0), the device returns to normal SPI mode, all
commands can be accepted. M7-6 and M3-0 are reserved bits for future use, either 0 or 1 values can
be used.
8.2.18
Continuous Read Mode Reset (FFh or FFFFh)
Continuous Read Mode Reset instruction can be used to set M4 = 1, thus the device will release the
Continuous Read Mode and return to normal SPI operation, as shown in figure 16.
Mode Bit Reset
for Dual I/O
Mode Bit Reset
for Quad I/O
/CS
Mode 3
CLK
IO0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
Mode 0
14
15
Mode 3
Mode 0
FFh
FFh
IO1
Don’t Care
IO2
Don’t Care
IO3
Don’t Care
Figure 16. Continuous Read Mode Reset for Fast Read Dual/Quad I/O
Since W25Q20CL does not have a hardware Reset pin, so if the controller resets while W25Q20CL is
set to Continuous Mode Read, the W25Q20CL will not recognize any initial standard SPI instructions
from the controller. To address this possibility, it is recommended to issue a Continuous Read Mode
Reset instruction as the first instruction after a system Reset. Doing so will release the device from the
Continuous Read Mode and allow Standard SPI instructions to be recognized.
To reset “Continuous Read Mode” during Quad I/O operation, only eight clocks are needed. The
instruction is “FFh”. To reset “Continuous Read Mode” during Dual I/O operation, sixteen clocks are
needed to shift in instruction “FFFFh”.
- 32 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
8.2.19
Page Program (02h)
The Page Program instruction allows from one byte to 256 bytes (a page) of data to be programmed
at previously erased (FFh) memory locations. A Write Enable instruction must be executed before the
device will accept the Page Program Instruction (Status Register bit WEL= 1). The instruction is
initiated by driving the /CS pin low then shifting the instruction code “02h” followed by a 24-bit address
(A23-A0) and at least one data byte, into the DI pin. The /CS pin must be held low for the entire length
of the instruction while data is being sent to the device.
If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address
bits) should be set to 0. If the last address byte is not zero, and the number of clocks exceed the
remaining page length, the addressing will wrap to the beginning of the page. In some cases, less
than 256 bytes (a partial page) can be programmed without having any effect on other bytes within the
same page. One condition to perform a partial page program is that the number of clocks cannot
exceed the remaining page length. If more than 256 bytes are sent to the device the addressing will
wrap to the beginning of the page and overwrite previously sent data.
As with the write and erase instructions, the /CS pin must be driven high after the eighth bit of the last
byte has been latched. If this is not done the Page Program instruction will not be executed. After /CS
is driven high, the self-timed Page Program instruction will commence for a time duration of tpp (See
AC Characteristics). While the Page Program cycle is in progress, the Read Status Register
instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during
the Page Program cycle and becomes a 0 when the cycle is finished and the device is ready to accept
other instructions again. After the Page Program cycle has finished the Write Enable Latch (WEL) bit
in the Status Register is cleared to 0. The Page Program instruction will not be executed if the
addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits (see
Status Register Memory Protection table).
Figure 17. Page Program Instruction Sequence Diagram
- 33 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
8.2.20
Quad Input Page Program (32h)
The Quad Page Program instruction allows up to 256 bytes of data to be programmed at previously
erased (FFh) memory locations using four pins: IO0, IO1, IO2, and IO3. The Quad Page Program can
improve performance for PROM Programmer and applications that have slow clock speeds <5MHz.
Systems with faster clock speed will not realize much benefit for the Quad Page Program instruction
since the inherent page program time is much greater than the time it take to clock-in the data.
To use Quad Page Program the Quad Enable in Status Register-2 must be set (QE=1). A Write
Enable instruction must be executed before the device will accept the Quad Page Program instruction
(Status Register-1, WEL=1). The instruction is initiated by driving the /CS pin low then shifting the
instruction code “32h” followed by a 24-bit address (A23-A0) and at least one data byte, into the IO
pins. The /CS pin must be held low for the entire length of the instruction while data is being sent to
the device. All other functions of Quad Page Program are identical to standard Page Program. The
Quad Page Program instruction sequence is shown in figure 18.
Figure 18. Quad Input Page Program Instruction Sequence Diagram
- 34 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
8.2.21
Sector Erase (20h)
The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased state
of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Sector
Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS
pin low and shifting the instruction code “20h” followed a 24-bit sector address (A23-A0) (see Figure 2).
The Sector Erase instruction sequence is shown in figure 19.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not
done the Sector Erase instruction will not be executed. After /CS is driven high, the self-timed Sector
Erase instruction will commence for a time duration of tSE (See AC Characteristics). While the Sector
Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the
status of the BUSY bit. The BUSY bit is a 1 during the Sector Erase cycle and becomes a 0 when the
cycle is finished and the device is ready to accept other instructions again. After the Sector Erase
cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Sector
Erase instruction will not be executed if the addressed page is protected by the Block Protect (CMP,
SEC, TB, BP2, BP1, and BP0) bits (see Status Register Memory Protection table).
/CS
Mode 3
CLK
0
1
2
3
4
5
6
7
8
29
30
31
Mode 3
Mode 0
Instruction (20h)
DI
(IO0)
DO
(IO1)
9
Mode 0
24-Bit Address
23
22
2
1
0
*
High Impedance
* = MSB
Figure 19. Sector Erase Instruction Sequence Diagram
- 35 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
8.2.22
32KB Block Erase (52h)
The Block Erase instruction sets all memory within a specified block (32K-bytes) to the erased state of
all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block
Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS
pin low and shifting the instruction code “52h” followed a 24-bit block address (A23-A0) (see Figure 2).
The Block Erase instruction sequence is shown in figure 20.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not
done the Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block
Erase instruction will commence for a time duration of tBE1 (See AC Characteristics). While the Block
Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the
status of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the
cycle is finished and the device is ready to accept other instructions again. After the Block Erase cycle
has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase
instruction will not be executed if the addressed page is protected by the Block Protect (CMP, SEC,
TB, BP2, BP1, and BP0) bits (see Status Register Memory Protection table).
/CS
Mode 3
CLK
0
1
2
3
4
5
6
7
8
29
30
31
Mode 0
Mode 3
Mode 0
Instruction (52h)
DI
(IO0)
DO
(IO1)
9
24-Bit Address
23
22
2
1
0
*
High Impedance
* = MSB
Figure 20. 32KB Block Erase Instruction Sequence Diagram
- 36 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
8.2.23
64KB Block Erase (D8h)
The Block Erase instruction sets all memory within a specified block (64K-bytes) to the erased state of
all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block
Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS
pin low and shifting the instruction code “D8h” followed a 24-bit block address (A23-A0) (see Figure 2).
The Block Erase instruction sequence is shown in figure 21.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not
done the Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block
Erase instruction will commence for a time duration of tBE (See AC Characteristics). While the Block
Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the
status of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the
cycle is finished and the device is ready to accept other instructions again. After the Block Erase cycle
has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase
instruction will not be executed if the addressed page is protected by the Block Protect (CMP, SEC,
TB, BP2, BP1, and BP0) bits (see Status Register Memory Protection table).
/CS
Mode 3
CLK
0
1
2
3
4
5
6
7
8
29
30
31
Mode 0
Mode 3
Mode 0
Instruction (D8h)
DI
(IO0)
DO
(IO1)
9
24-Bit Address
23
22
2
1
0
*
High Impedance
* = MSB
Figure 21. 64KB Block Erase Instruction Sequence Diagram
- 37 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
8.2.24
Chip Erase (C7h / 60h)
The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A
Write Enable instruction must be executed before the device will accept the Chip Erase Instruction
(Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and
shifting the instruction code “C7h” or “60h”. The Chip Erase instruction sequence is shown in figure 22.
The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Chip
Erase instruction will not be executed. After /CS is driven high, the self-timed Chip Erase instruction
will commence for a time duration of tCE (See AC Characteristics). While the Chip Erase cycle is in
progress, the Read Status Register instruction may still be accessed to check the status of the BUSY
bit. The BUSY bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is
ready to accept other instructions again. After the Chip Erase cycle has finished the Write Enable
Latch (WEL) bit in the Status Register is cleared to 0. The Chip Erase instruction will not be executed
if any page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits (see Status
Register Memory Protection table).
/CS
Mode 3
CLK
0
1
2
3
4
5
6
7
Mode 0
Mode 3
Mode 0
Instruction (C7h/60h)
DI
(IO0)
DO
(IO1)
High Impedance
Figure 22. Chip Erase Instruction Sequence Diagram
- 38 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
8.2.25 Erase / Program Suspend (75h)
The Erase/Program Suspend instruction “75h”, allows the system to interrupt a Sector or Block Erase
operation or a Page Program operation and then read from or program/erase data to, any other
sectors or blocks. The Erase/Program Suspend instruction sequence is shown in figure 23.
The Write Status Register instruction (01h) and Erase instructions (20h, 52h, D8h, C7h, 60h, 44h) are
not allowed during Erase Suspend. Erase Suspend is valid only during the Sector or Block erase
operation. If written during the Chip Erase operation, the Erase Suspend instruction is ignored. The
Write Status Register instruction (01h) and Program instructions (02h, 32h, 42h) are not allowed
during Program Suspend. Program Suspend is valid only during the Page Program or Quad Page
Program operation.
The Erase/Program Suspend instruction “75h” will be accepted by the device only if the SUS bit in the
Status Register equals to 0 and the BUSY bit equals to 1 while a Sector or Block Erase or a Page
Program operation is on-going. If the SUS bit equals to 1 or the BUSY bit equals to 0, the Suspend
instruction will be ignored by the device. A maximum of time of “tSUS” (See AC Characteristics) is
required to suspend the erase or program operation. The BUSY bit in the Status Register will be
cleared from 1 to 0 within “tSUS” and the SUS bit in the Status Register will be set from 0 to 1
immediately after Erase/Program Suspend. For a previously resumed Erase/Program operation, it is
also required that the Suspend instruction “75h” is not issued earlier than a minimum of time of “t SUS”
following the preceding Resume instruction “7Ah”.
Unexpected power off during the Erase/Program suspend state will reset the device and release the
suspend state. SUS bit in the Status Register will also reset to 0. The data within the page, sector or
block that was being suspended may become corrupted. It is recommended for the user to implement
system design techniques against the accidental power interruption and preserve data integrity during
erase/program suspend state.
Figure 23. Erase/Program Suspend Instruction Sequence
- 39 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
8.2.26 Erase / Program Resume (7Ah)
The Erase/Program Resume instruction “7Ah” must be written to resume the Sector or Block Erase
operation or the Page Program operation after an Erase/Program Suspend. The Resume instruction
“7Ah” will be accepted by the device only if the SUS bit in the Status Register equals to 1 and the
BUSY bit equals to 0. After issued the SUS bit will be cleared from 1 to 0 immediately, the BUSY bit
will be set from 0 to 1 within 200ns and the Sector or Block will complete the erase operation or the
page will complete the program operation. If the SUS bit equals to 0 or the BUSY bit equals to 1, the
Resume instruction “7Ah” will be ignored by the device. The Erase/Program Resume instruction
sequence is shown in figure 24.
Resume instruction is ignored if the previous Erase/Program Suspend operation was interrupted by
unexpected power off. It is also required that a subsequent Erase/Program Suspend instruction not to
be issued within a minimum of time of “tSUS” following a previous Resume instruction.
Figure 24. Erase/Program Resume Instruction Sequence
- 40 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
8.2.27
Power-down (B9h)
Although the standby current during normal operation is relatively low, standby current can be further
reduced with the Power-down instruction. The lower power consumption makes the Power-down
instruction especially useful for battery powered applications (See ICC1 and ICC2 in AC
Characteristics). The instruction is initiated by driving the /CS pin low and shifting the instruction code
“B9h” as shown in figure 25.
The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Powerdown instruction will not be executed. After /CS is driven high, the power-down state will entered
within the time duration of tDP (See AC Characteristics). While in the power-down state only the
Release from Power-down / Device ID instruction, which restores the device to normal operation, will
be recognized. All other instructions are ignored. This includes the Read Status Register instruction,
which is always available during normal operation. Ignoring all but one instruction makes the Power
Down state a useful condition for securing maximum write protection. The device always powers-up in
the normal operation with the standby current of ICC1.
/CS
tDP
Mode 3
CLK
0
1
2
3
4
5
6
7
Mode 3
Mode 0
Mode 0
Instruction (B9h)
DI
(IO0)
Stand-by current
Power-down current
Figure 25. Deep Power-down Instruction Sequence Diagram
- 41 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
8.2.28
Release Power-down / Device ID (ABh)
The Release from Power-down / Device ID instruction is a multi-purpose instruction. It can be used to
release the device from the power-down state, or obtain the devices electronic identification (ID)
number.
To release the device from the power-down state, the instruction is issued by driving the /CS pin low,
shifting the instruction code “ABh” and driving /CS high as shown in figure 26a. Release from powerdown will take the time duration of tRES1 (See AC Characteristics) before the device will resume
normal operation and other instructions are accepted. The /CS pin must remain high during the tRES1
time duration.
When used only to obtain the Device ID while not in the power-down state, the instruction is initiated
by driving the /CS pin low and shifting the instruction code “ABh” followed by 3-dummy bytes. The
Device ID bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first as
shown in figure 26a. The Device ID values for the W25Q20CL is listed in Manufacturer and Device
Identification table. The Device ID can be read continuously. The instruction is completed by driving
/CS high.
When used to release the device from the power-down state and obtain the Device ID, the instruction
is the same as previously described, and shown in figure 26b, except that after /CS is driven high it
must remain high for a time duration of tRES2 (See AC Characteristics). After this time duration the
device will resume normal operation and other instructions will be accepted.
If the Release from Power-down / Device ID instruction is issued while an Erase, Program or Write
cycle is in process (when BUSY equals 1) the instruction is ignored and will not have any effects on
the current cycle.
/CS
tRES1
Mode 3
CLK
0
1
2
3
4
5
6
7
Mode 3
Mode 0
Mode 0
Instruction (ABh)
DI
(IO0)
Power-down current
Stand-by current
Figure 26a. Release Power-down Instruction Sequence
- 42 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
/CS
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
29
30
31
32
33
34
35
36
37
38
Mode 3
Mode 0
Mode 0
Instruction (ABh)
DI
(IO0)
tRES2
3 Dummy Bytes
23
22
2
1
0
*
Device ID
High Impedance
DO
(IO1)
7
6
5
4
3
2
1
0
*
* = MSB
Power-down current
Stand-by current
Figure 26b. Release Power-down / Device ID Instruction Sequence Diagram
- 43 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
8.2.29
Read Manufacturer / Device ID (90h)
The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down /
Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device
ID.
The Read Manufacturer/Device ID instruction is very similar to the Release from Power-down / Device
ID instruction. The instruction is initiated by driving the /CS pin low and shifting the instruction code
“90h” followed by a 24-bit address (A23-A0) of 000000h. After which, the Manufacturer ID for Winbond
(EFh) and the Device ID are shifted out on the falling edge of CLK with most significant bit (MSB) first
as shown in figure 27. The Device ID values for the W25Q20CL is listed in Manufacturer and Device
Identification table. If the 24-bit address is initially set to 000001h the Device ID will be read first and
then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously,
alternating from one to the other. The instruction is completed by driving /CS high.
/CS
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
10
28
29
30
31
Mode 0
Instruction (90h)
Address (000000h)
DI
(IO0)
23
22
21
42
43
3
2
45
46
1
0
*
High Impedance
DO
(IO1)
* = MSB
/CS
31
32
33
34
35
36
37
38
39
40
41
44
Mode 3
CLK
DI
(IO0)
Mode 0
0
DO
(IO1)
7
Manufacturer ID (EFh)
*
6
5
4
3
2
1
0
Device ID
Figure 27. Read Manufacturer / Device ID Diagram
- 44 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
8.2.30
Read Manufacturer / Device ID Dual I/O (92h)
The Manufacturer / Device ID Dual I/O instruction is an alternative to the Read Manufacturer/Device
ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID at 2x
speed.
The Read Manufacturer / Device ID Dual I/O instruction is similar to the Fast Read Dual I/O instruction.
The instruction is initiated by driving the /CS pin low and shifting the instruction code “92h” followed by
a 24-bit address (A23-A0) of 000000h, 8-bit Continuous Read Mode Bits, with the capability to input
the Address bits two bits per clock. After which, the Manufacturer ID for Winbond (EFh) and the
Device ID are shifted out 2 bits per clock on the falling edge of CLK with most significant bits (MSB)
first as shown in figure 28. The Device ID values for the W25Q20CL are listed in Manufacturer and
Device Identification table. If the 24-bit address is initially set to 000001h the Device ID will be read
first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read
continuously, alternating from one to the other. The instruction is completed by driving /CS high.
/CS
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Mode 0
Instruction (92h)
A23-16
DI
(IO0)
High Impedance
DO
(IO1)
*
= MSB
A15-8
A7-0 (00h)
M7-0
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
*
*
*
*
/CS
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
Mode 3
CLK
Mode 0
IOs switch from
Input to Output
DI
(IO0)
0
6
4
2
0
6
4
2
0
6
DO
(IO1)
1
7
5
3
1
7
5
3
1
*
MFR ID
*
Device ID
4
2
0
6
7
5
3
1
7
*
MFR ID
(repeat)
*
4
2
0
5
3
1
Device ID
(repeat)
Figure 28. Read Manufacturer / Device ID Dual I/O Diagram
Note:
1. The “Continuous Read Mode” bits M7-0 must be set to Fxh to be compatible with Fast Read Dual I/O instruction.
- 45 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
8.2.31
Read Manufacturer / Device ID Quad I/O (94h)
The Read Manufacturer / Device ID Quad I/O instruction is an alternative to the Read Manufacturer /
Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device
ID at 4x speed.
The Read Manufacturer / Device ID Quad I/O instruction is similar to the Fast Read Quad I/O
instruction. The instruction is initiated by driving the /CS pin low and shifting the instruction code “94h”
followed by a 24-bit address (A23-A0) of 000000h, 8-bit Continuous Read Mode Bits and then four
clock dummy cycles, with the capability to input the Address bits four bits per clock. After which, the
Manufacturer ID for Winbond (EFh) and the Device ID are shifted out four bits per clock on the falling
edge of CLK with most significant bit (MSB) first as shown in figure 29. The Device ID values for the
W25Q20CL is listed in Manufacturer and Device Identification table. If the 24-bit address is initially set
to 000001h the Device ID will be read first and then followed by the Manufacturer ID. The
Manufacturer and Device IDs can be read continuously, alternating from one to the other. The
instruction is completed by driving /CS high.
Figure 29. Read Manufacturer / Device ID Quad I/O Diagram
Note:
1. The “Continuous Read Mode” bits M7-0 must be set to Fxh to be compatible with Fast Read Quad I/O instruction.
- 46 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
8.2.32
Read Unique ID Number (4Bh)
The Read Unique ID Number instruction accesses a factory-set read-only 64-bit number that is unique
to each W25Q20CL device. The ID number can be used in conjunction with user software methods to
help prevent copying or cloning of a system. The Read Unique ID instruction is initiated by driving the
/CS pin low and shifting the instruction code “4Bh” followed by a four bytes of dummy clocks. After
which, the 64-bit ID is shifted out on the falling edge of CLK as shown in figure 30.
/CS
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Mode 0
Instruction (4Bh)
Dummy Byte 1
Dummy Byte 2
DI
(IO0)
High Impedance
DO
(IO1)
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
102
24
101
23
100
/CS
Mode 3
CLK
Mode 0
Dummy Byte 3
Dummy Byte 4
DI
(IO0)
DO
(IO1)
High Impedance
*
= MSB
63
62
61
2
1
*
64-bit Unique Serial Number
0
Figure 30. Read Unique ID Number Instruction Sequence
- 47 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
8.2.33
Read JEDEC ID (9Fh)
For compatibility reasons, the W25Q20CL provide several instructions to electronically determine the
identity of the device. The Read JEDEC ID instruction is compatible with the JEDEC standard for SPI
compatible serial memories that was adopted in 2003.
The instruction is initiated by driving the /CS pin low and shifting the instruction code “9Fh”. The
JEDEC assigned Manufacturer ID byte for Winbond (EFh) and two Device ID bytes, Memory Type
(ID15-ID8) and Capacity (ID7-ID0) are then shifted out on the falling edge of CLK with most significant
bit (MSB) first as shown in figure 31. For memory type and capacity values refer to Manufacturer and
Device Identification table.
Figure 31. Read JEDEC ID Instruction Sequence
- 48 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
8.2.34
Erase Security Registers (44h)
The W25Q20CL offers four 256-byte Security Registers which can be erased and programmed
individually. These registers may be used by the system manufacturers to store security and other
important information separately from the main memory array.
The Erase Security Register instruction is similar to the Sector Erase instruction. A Write Enable
instruction must be executed before the device will accept the Erase Security Register Instruction
(Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and
shifting the instruction code “44h” followed by a 24-bit address (A23-A0) to erase one of the four
security registers.
ADDRESS
A23-16
A15-12
A11-8
A7-0
Security Register #0*
00h
0000
0000
Don’t Care
Security Register #1
00h
0001
0000
Don’t Care
Security Register #2
00h
0010
0000
Don’t Care
Security Register #3
00h
0011
0000
Don’t Care
* Please note that Security Register 0 is Reserved by Winbond for future use. It is recommended to use Security
registers 1- 3 before using register 0.
The Erase Security Register instruction sequence is shown in figure 32. The /CS pin must be driven
high after the eighth bit of the last byte has been latched. If this is not done the instruction will not be
executed. After /CS is driven high, the self-timed Erase Security Register operation will commence for
a time duration of tSE (See AC Characteristics). While the Erase Security Register cycle is in progress,
the Read Status Register instruction may still be accessed for checking the status of the BUSY bit.
The BUSY bit is a 1 during the erase cycle and becomes a 0 when the cycle is finished and the device
is ready to accept other instructions again. After the Erase Security Register cycle has finished the
Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Security Register Lock Bits
(LB3-0) in the Status Register-2 can be used to OTP protect the security registers. Once a lock bit is
set to 1, the corresponding security register will be permanently locked, Erase Security Register
instruction to that register will be ignored (See 8.1.9 for detail descriptions).
Instruction (44h)
Figure 32. Erase Security Registers Instruction Sequence
- 49 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
8.2.35
Program Security Registers (42h)
The Program Security Register instruction is similar to the Page Program instruction. It allows from
one byte to 256 bytes of security register data to be programmed at previously erased (FFh) memory
locations. A Write Enable instruction must be executed before the device will accept the Program
Security Register Instruction (Status Register bit WEL= 1). The instruction is initiated by driving the
/CS pin low then shifting the instruction code “42h” followed by a 24-bit address (A23-A0) and at least
one data byte, into the DI pin. The /CS pin must be held low for the entire length of the instruction
while data is being sent to the device.
ADDRESS
A23-16
A15-12
A11-8
A7-0
Security Register #0*
00h
0000
0000
Byte Address
Security Register #1
00h
0001
0000
Byte Address
Security Register #2
00h
0010
0000
Byte Address
Security Register #3
00h
0011
0000
Byte Address
* Please note that Security Register 0 is Reserved by Winbond for future use. It is recommended to use Security
registers 1- 3 before using register 0.
The Program Security Register instruction sequence is shown in figure 33. The Security Register Lock
Bits (LB3-0) in the Status Register-2 can be used to OTP protect the security registers. Once a lock bit
is set to 1, the corresponding security register will be permanently locked, Program Security Register
instruction to that register will be ignored (See 8.1.9, 8.2.21 for detail descriptions).
Instruction (42h)
Figure 33. Program Security Registers Instruction Sequence
- 50 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
8.2.36
Read Security Registers (48h)
The Read Security Register instruction is similar to the Fast Read instruction and allows one or more
data bytes to be sequentially read from one of the four security registers. The instruction is initiated by
driving the /CS pin low and then shifting the instruction code “48h” followed by a 24-bit address (A23A0) and eight “dummy” clocks into the DI pin. The code and address bits are latched on the rising
edge of the CLK pin. After the address is received, the data byte of the addressed memory location
will be shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first. The
byte address is automatically incremented to the next byte address after each byte of data is shifted
out. Once the byte address reaches the last byte of the register (byte FFh), It will reset to 00h, the first
byte of the register, and continue to increment. The instruction is completed by driving /CS high. The
Read Security Register instruction sequence is shown in figure 34. If a Read Security Register
instruction is issued while an Erase, Program or Write cycle is in process (BUSY=1) the instruction is
ignored and will not have any effects on the current cycle. The Read Security Register instruction
allows clock rates from D.C. to a maximum of FR (see AC Electrical Characteristics).
ADDRESS
A23-16
A15-12
A11-8
A7-0
Security Register #0*
00h
0000
0000
Byte Address
Security Register #1
00h
0001
0000
Byte Address
Security Register #2
00h
0010
0000
Byte Address
Security Register #3
00h
0011
0000
Byte Address
* Please note that Security Register 0 is Reserved by Winbond for future use. It is recommended to use Security
registers 1- 3 before using register 0.
Instruction (48h)
Figure 34. Read Security Registers Instruction Sequence
- 51 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
9. ELECTRICAL CHARACTERISTICS
9.1 Absolute Maximum Ratings (1)
PARAMETERS
SYMBOL
Supply Voltage
VCC
Voltage Applied to Any Pin
VIO
Transient Voltage on any Pin
VIOT
Storage Temperature
TSTG
Lead Temperature
TLEAD
Electrostatic Discharge Voltage
VESD
CONDITIONS
RANGE
UNIT
–0.6 to VCC+0.6
V
Relative to Ground
–0.6 to VCC+0.4
V
<20nS Transient
Relative to Ground
–2.0V to VCC+2.0V
V
–65 to +150
°C
(2)
°C
See Note
Human Body Model(3)
–2000 to +2000
V
Notes:
1. This device has been designed and tested for the specified operation ranges. Proper operation outside of these levels is not
guaranteed. Exposure to absolute maximum ratings may affect device reliability. Exposure beyond absolute maximum ratings
may cause permanent damage.
2. Compliant with JEDEC Standard J-STD-20C for small body Sn-Pb or Pb-free (Green) assembly and the European directive
on restrictions on hazardous substances (RoHS) 2002/95/EU.
3. JEDEC Std JESD22-A114A (C1=100pF, R1=1500 ohms, R2=500 ohms).
9.2 Operating Ranges
PARAMETER
Supply Voltage(1)
Ambient Temperature,
Operating
SYMB
OL
VCC
CONDITIONS
FR = 80MHz, fR = 33MHz
FR = 104MHz, fR = 50MHz
Industrial
TA
SPEC
UNIT
MIN
MAX
2.3
2.7
2.7
3.6
V
–40
+85
°C
Note:
1. VCC voltage during Read can operate across the min and max range but should not exceed ±10% of the programming
(erase/write) voltage.
- 52 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
9.3
Power-up Timing and Write Inhibit Threshold
Parameter
Symbol
spec
MIN
MAX
Unit
VCC (min) to /CS Low
tVSL(1)
10
µs
Time Delay Before Write Instruction
tPUW(1)
5
ms
Write Inhibit Threshold Voltage
VWI(1)
1.0
2.0
V
Note:
1. These parameters are characterized only.
Figure 35a. Power-up Timing and Voltage Levels
Figure 35b. Power-up, Power-Down Requirement
- 53 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
9.4 DC Electrical Characteristics
PARAMETER
Input Capacitance
Output Capacitance
SYMBOL
CIN(1)
Cout(1)
CONDITIONS
SPEC
MIN
TYP
MAX
UNIT
VIN = 0V(1)
6
pF
VOUT = 0V(1)
8
pF
Input Leakage
ILI
±2
µA
I/O Leakage
ILO
±2
µA
Standby Current
ICC1
/CS = VCC,
VIN = GND or VCC
10
50
µA
Power-down Current
ICC2
/CS = VCC,
VIN = GND or VCC
1
5
µA
Current Read Data /
Dual /Quad 1MHz(2)
ICC3
C = 0.1 VCC / 0.9 VCC
DO = Open
1/3/5
4/8/10
mA
Current Read Data /
Dual /Quad 33MHz(2)
ICC3
C = 0.1 VCC / 0.9 VCC
DO = Open
4/5/6
8/10/12
mA
Current Read Data /
Dual Output Read/Quad
Output Read 80MHz(2)
ICC3
C = 0.1 VCC / 0.9 VCC
DO = Open
5/6/7
10/12/14
mA
Current Read Data /
Dual Output / Quad
Output Read 104MHz(2)
Icc3
C = 0.1 VCC / 0.9 VCC
DO = Open
6/7/8
12/14/16
mA
Current Write Status
Register
Icc4
/CS = VCC
8
12
mA
Current Page Program
Icc5
/CS = VCC
10
15
mA
Current Sector/Block
Erase
Icc6
/CS = VCC
10
15
mA
Current Chip Erase
Icc7
/CS = VCC
15
mA
Input Low Voltage
Vil
-0.5
VCC x 0.3
V
Input High Voltage
Vih
VCC x 0.7
Output Low Voltage
Vol
Iol = 100 µA
Output High Voltage
Voh
Ioh = –100 µA
10
V
0.2
VCC – 0.2
V
V
Notes:
1. Tested on sample basis and specified through design and characterization data. TA = 25° C, VCC = 3V.
2. Checker Board Pattern.
- 54 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
9.5 AC Measurement Conditions
PARAMETER
SYMBOL
Load Capacitance
Input Rise and Fall Times
Input Pulse Voltages
Input Timing Reference Voltages
Output Timing Reference Voltages
SPEC
MIN
MAX
UNIT
CL
30
pF
TR, TF
5
ns
VIN
0.1 VCC to 0.9 VCC
V
IN
0.3 VCC to 0.7 VCC
V
OUT
0.5 VCC to 0.5 VCC
V
Note:
1. Output Hi-Z is defined as the point where data out is no longer driven.
Input Levels
Input and Output Timing
Reference Levels
0.9 VCC
0.5 VCC
0.1 VCC
Figure 36. AC Measurement I/O Waveform
- 55 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
9.6 AC Electrical Characteristics
SPEC
DESCRIPTION
SYMBOL
ALT
UNIT
MIN
TYP
MAX
Clock frequency for all instructions
except for Read Data (03h)
2.3V-3.6V VCC & Industrial Temperature
FR
fC
D.C.
104
MHz
Clock frequency for all instructions,
except Read Data (03h)
2.3V-2.7V VCC & Industrial Temperature
FR
fC
D.C.
80
MHz
Clock frequency for Read Data instruction (03h)
2.7V-3.6V VCC & Industrial Temperature
fR
D.C.
50
MHz
Clock frequency for Read Data instruction (03h)
2.3V-2.7V VCC & Industrial Temperature
fR
D.C.
33
MHz
Clock High, Low Time for all instructions
except Read Data (03h)
tCLH1,
tCLL1(1)
4
ns
Clock High, Low Time
for Read Data (03h) instruction
tCRLH,
tCRLL(1)
8
ns
Clock Rise Time peak to peak
tCLCH(2)
0.1
V/ns
Clock Fall Time peak to peak
tCHCL(2)
0.1
V/ns
5
ns
5
ns
/CS Active Setup Time relative to CLK
tSLCH
/CS Not Active Hold Time relative to CLK
tCHSL
Data In Setup Time
tDVCH
tDSU
2
ns
Data In Hold Time
tCHDX
tDH
5
ns
/CS Active Hold Time relative to CLK
tCHSH
5
ns
/CS Not Active Setup Time relative to CLK
tSHCH
5
ns
/CS Deselect Time (for Array Read  Array Read)
tSHSL1
tCSH
50
ns
/CS Deselect Time (for Erase/Program  Read SR)
Volatile Status Register Write Time
tSHSL2
tCSH
100
50
ns
Output Disable Time
tSHQZ(2)
tDIS
7
ns
Clock Low to Output Valid
tCLQV1
tV1
8
ns
Clock Low to Output Valid (for Read ID instructions)
tCLQV2
tV2
8
ns
- 56 -
tCSS
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
9.7 AC Electrical Characteristics (cont’d)
SPEC
DESCRIPTION
SYMBOL
ALT
UNIT
MIN
Output Hold Time
tCLQX
/HOLD Active Setup Time relative to CLK
tHO
TYP
MAX
0
ns
tHLCH
5
ns
/HOLD Active Hold Time relative to CLK
tCHHH
5
ns
/HOLD Not Active Setup Time relative to CLK
tHHCH
5
ns
/HOLD Not Active Hold Time relative to CLK
tCHHL
5
ns
/HOLD to Output Low-Z
tHHQX(2)
tLZ
7
ns
/HOLD to Output High-Z
tHLQZ(2)
tHZ
12
ns
Write Protect Setup Time Before /CS Low
tWHSL(3)
20
ns
Write Protect Hold Time After /CS High
tSHWL(3)
100
ns
tDP(2)
3
µs
/CS High to Standby Mode without ID Read
tRES1(2)
3
µs
/CS High to Standby Mode with ID Read
tRES2(2)
1.8
µs
/CS High to next Instruction after Suspend
tSUS(2)
20
µs
/CS High to Power-down Mode
Write Status Register Time
tW
10
15
ms
Byte Program Time (First Byte) (4)
tBP1
15
30
µs
Additional Byte Program Time (After First Byte) (4)
tBP2
2.5
5
µs
Page Program Time
tPP
0.4
0.8
ms
Sector Erase Time (4KB)
tSE
30
300
ms
Block Erase Time (32KB)
tBE1
120
800
ms
Block Erase Time (64KB)
tBE2
150
1,000
ms
Chip Erase Time W25Q20CL
tce
0.5
2
s
Notes:
1.
Clock high + Clock low must be less than or equal to 1/fC.
2.
Value guaranteed by design and/or characterization, not 100% tested in production.
3.
Only applicable as a constraint for a Write Status Register instruction when SRP0 bit is set to 1.
4.
For multiple bytes after first byte within a page, tBPN = tBP1 + tBP2 * N (typical) and tBPN = tBP1 + tBP2 * N (max), where N =
number of bytes programmed.
- 57 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
9.8 Serial Output Timing
/CS
tCLH
CLK
tCLQV
tCLQX
tCLQX
IO
output
tCLQV
tCLL
MSB OUT
tSHQZ
LSB OUT
9.9 Serial Input Timing
/CS
tSHSL
tCHSL
tSLCH
tCHSH
tSHCH
CLK
tDVCH
IO
input
tCHDX
tCLCH
MSB IN
tCHCL
LSB IN
9.10 Hold Timing
/CS
tCHHL
tHLCH
tHHCH
CLK
tCHHH
/HOLD
tHLQZ
tHHQX
IO
output
IO
input
9.11 /WP Timing
/CS
tWHSL
tSHWL
/WP
CLK
IO
input
Write Status Register is allowed
- 58 -
Write Status Register is not allowed
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
10. PACKAGE SPECIFICATION
10.1 8-Pin SOIC 150-mil (Package Code SN)
8
c
5
E HE
L
1
4
θ
0.25
D
A
Y
e
SEATING PLANE
SYMBOL
GAUGE PLANE
A1
b
MILLIMETERS
Min
Max
INCHES
Min
Max
A
1.35
1.75
0.053
0.069
A1
0.10
0.25
0.004
0.010
b
0.33
0.51
0.013
0.020
c
0.19
0.25
0.008
0.010
E(3)
3.80
4.00
0.150
0.157
(3)
4.80
5.00
0.188
D
e(2)
HE
Y
(4)
1.27 BSC
0.196
0.050 BSC
5.80
6.20
0.228
0.244
-
0.10
-
0.004
L
0.40
1.27
0.016
0.050
∘
0°
10°
0°
10°
Notes:
1. Controlling dimensions: millimeters, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E do not include mold flash protrusions and should be measured from the bottom of the package.
4. Formed leads coplanarity with respect to seating plane shall be within 0.004 inches.
- 59 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
10.2 8-Pin VSOP8 150-mil (Package Code SV)
SYMBOL
MILLIMETER
INCHES
MIN
TYP.
MAX
MIN
TYP.
MAX
A
―
―
0.90
―
―
0.035
A1
0.00
0.05
―
0.00
0.002
―
A2
―
0.8
―
―
0.031
―
b
0.33
―
0.51
0.33
―
0.020
c
0.125 BSC
0.005 BSC
D
4.80
4.90
5.00
0.189
0.193
0.197
E
5.80
6.00
6.20
0.228
0.236
0.244
E1
3.80
3.90
4.00
0.150
0.154
0.157
e
1.27BSC
0.050 BSC
L
0.4
0.71
1.27
0.015
0.0280
0.050
y
―
―
0.10
―
―
0.004
θ
0°
―
10°
0°
―
10°
- 60 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
10.3 8-Pad 6x5mm WSON (Package Code ZP)
SYMBOL
MILLIMETERS
INCHES
MIN
TYP.
MAX
MIN
TYP.
MAX
A
0.70
0.75
0.80
0.028
0.030
0.031
A1
0.00
0.02
0.05
0.000
0.001
0.002
b
0.35
0.40
0.48
0.014
0.016
0.019
C
-
0.20 REF.
-
-
0.008 REF.
-
D
5.90
6.00
6.10
0.232
0.236
0.240
D2
3.35
3.40
3.45
0.132
0.134
0.136
E
4.90
5.00
5.10
0.193
0.197
0.201
E2
4.25
4.30
4.35
0.167
0.169
0.171
e
1.27 BSC
0.050 BSC
L
0.55
0.60
0.65
0.022
0.024
0.026
y
0.00
-
0.075
0.000
-
0.003
- 61 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
10.4 8-Pad WSON 6x5mm Cont’d.
SYMBOL
MILLIMETERS
MIN
TYP.
INCHES
MAX
MIN
TYP.
MAX
SOLDER PATTERN
M
3.40
0.1338
N
4.30
0.1692
P
6.00
0.2360
Q
0.50
0.0196
R
0.75
0.0255
Notes:
1.
2.
3.
Advanced Packaging Information; please contact Winbond for the latest minimum and maximum specifications.
BSC = Basic lead spacing between centers.
Dimensions D and E do not include mold flash protrusions and should be measured from the bottom of the package.
4.
The metal pad area on the bottom center of the package is connected to the device ground (GND pin). Avoid placement of
exposed PCB vias under the pad.
- 62 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
10.5 8-Pad USON 2x3-mm (Package Code UX)
A
PIN
INDENT
1
L1
A1
e
D2
D
b
L3
E
2
C
E
y
L
Note: Exposed pad dimension D2 & E2 may be different by die size .
SYMBOL
MILLIMETER
INCHES
MIN
TYP.
MAX
MIN
TYP.
MAX
A
0.50
0.55
0.60
0.020
0.022
0.024
A1
0.00
0.02
0.05
0.000
0.001
0.002
b
0.20
0.25
0.30
0.008
0.010
0.012
C
―
0.15 REF
―
―
0.006 REF
―
D
1.90
2.00
2.10
0.075
0.079
0.083
D2
1.55
1.60
1.65
0.061
0.063
0.065
E
2.90
3.00
3.10
0.114
0.118
0.122
E2
0.15
0.20
0.25
0.006
0.008
0.010
e
―
0.50
―
―
0.020
―
L
0.40
0.45
0.50
0.016
0.018
0.020
L1
―
0.10
―
―
0.004
―
L3
0.30
0.35
0.40
0.012
0.014
0.016
y
0.00
―
0.075
0.000
―
0.003
- 63 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
11. ORDERING INFORMATION
W(1) 25Q xxC L xx(2)
W
=
Winbond
25Q
=
SpiFlash Serial Flash Memory with 4KB sectors, Dual/Quad I/O
20C
=
2M-bit
L =
2.3V to 3.6V
SN = 8-pin SOIC 150-mil
ZP = 8-pad WSON 6x5-mm
I
=
SV = 8-pin VSOP 150-mil
UX = 8-pad USON 2x3-mm
Industrial (-40°C to +85°C)
(3,4)
G =
P =
Green Package (Lead-free, RoHS Compliant, Halogen-free (TBBA), Antimony-Oxide-free Sb2O3)
Green Package with Status Register Power-Down & OTP enabled
Notes:
1.
The “W” prefix is not included on the part marking.
nd
2.
Only the 2 letter is used for the part marking; WSON package type ZP is not used for the part marking.
3.
Standard bulk shipments are in Tube (shape E). Please specify alternate packing method, such as Tape and Reel (shape
T) or Tray (shape S), when placing orders.
4.
For shipments with OTP feature enabled, please specify when placing orders.
- 64 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
11.1 Valid Part Numbers and Top Side Marking
The following table provides the valid part numbers for the W25Q20CL SpiFlash Memory. Please
contact Winbond for specific availability by density and package type. Winbond SpiFlash memories
use an 12-digit Product Number for ordering. However, due to limited space, the Top Side Marking on
all packages use an abbreviated 10-digit number.
PACKAGE TYPE
DENSITY
PRODUCT NUMBER
TOP SIDE MARKING
SN
SOIC-8 150mil
2M-bit
W25Q20CLSNIG
25Q20CLNIG
SV
VSOP-8 150mil
2M-bit
W25Q20CLSVIG
25Q20CLVIG
ZP(1)
WSON-8 6x5mm
2M-bit
W25Q20CLZPIG
25Q20CLIG
UX(2)
USON-8 2X3mm
2M-bit
W25Q20CLUXIG
2Jxxx
0Gxxxx
Note:
1. WSON package type ZP is not used in the top side marking.
2. USON package type UX is not used in the top side marking.\
- 65 -
Publication Release Date: August 06, 2013
Revision A1
W25Q20CL
12. REVISION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
A
2012/12/27
All
New Create
A1
2013/08/06
13
52
Modify the typo of LB0-LB3
Modify absolute maximum ratings of Vcc
Trademarks
Winbond and SpiFlash are trademarks of Winbond Electronics Corporation.
All other marks are the property of their respective owner.
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in
systems or equipment intended for surgical implantation, atomic energy control instruments, airplane
or spaceship instruments, transportation instruments, traffic signal instruments, combustion control
instruments, or for other applications intended to support or sustain life. Further more, Winbond
products are not intended for applications wherein failure of Winbond products could result or lead to a
situation wherein personal injury, death or severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their own risk
and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
- 66 -
Publication Release Date: August 06, 2013
Revision A1