REJ03F0262-0100 Rev. 1.00 Jan. 16. 2008 R8A66161DD/SP 16-BIT LED DRIVER WITH SHIFT REGISTER AND LATCH DESCRIPTION R8A66161 is a LED array driver having a 16-bit serial input and parallel output shift register function with direct coupled reset input and output latch function. This product guarantees the output current of 24mA (Vcc =5V case) which is sufficient for anode common LED drive, capable of following 16-bits continuously at the same time. Parallel output is open drain output. In addition, as this product has been designed in complete CMOS, power consumption can be greatly reduced when compared with conventional BIPOLAR or Bi-CMOS products. Furthermore, pin layout ensures the realization of an easy printed circuit. R8A66161 is the succession product of M66311. FEATURES ● Anode common LED drive ● VCC 5V or 3.3V single power supply ● High output current: all parallel outputs QA~ QP IOL=24mA (at VCC =5.0V) IOL=12mA (at VCC =3.3V) simultaneous lighting available ● Low power dissipation: 100uW/package (max) (VCC=5.0V, Ta=25℃, quiescent state) ● High noise margin: Schmitt input circuit provides responsiveness to a long line length ● Equipped with direct-coupled reset ● Open drain output: (except serial data output SQP) ● Wide operating temperature range: Ta=-40oC~+85oC ● Pin layout facilitates printed circuit wiring. (This layout facilitates cascade connection and LED connection) APPLICATION ● LED array drive, The various LED display modules ● PPC, Printer, VCR, Mini-compo, Button-Telephone etc. All of LED display equipment BLOCK DIAGRAM LOGIC DIAGRAM SERIAL DATA OUTPUT PARALLEL DATA OUTPUTS QC QD QE QF QG QH QI QJ QK QL QM QN QO QP SQP 2 24 23 22 21 20 19 18 17 16 15 14 13 11 12 10 Q CK D S Q CK D S Q CK D S Q CK D S Q CK D S Q CK D S Q CK D S Q CK D S Q CK D S Q CK D S Q CK D S Q CK D S Q CK D S Q CK D S Q CK D S Q CK D S Q CK D S Q CK D S Q CK D S Q CK D S Q CK D S Q CK D S Q CK D S Q CK D S Q CK D S Q CK D S Q CK D S Q CK D S Q CK D S Q CK D S Q CK D S Q CK D S OE A ENABLE SERIAL INPUT DATA INPUT DATA signal OE signal PARALLEL DATA OUTPUTS QA∼QP OUTPUT FORMAT REJ03F0262-0100 Rev.1.00 Jan.16.2008 page 1 of 7 SERIAL DATA OUTPUT SQP S 4 S 5 8 7 6 CKS Vcc 3 S S QB 1 S QA 9 R CKL GND SHIFT DIRECT LATCH CLOCK RESET CLOCK INPUT INPUT INPUT R8A66161DD/SP PIN CONFIGURATION ( TOP VIEW ) QA 1 QA QC 24 QC QB 2 QB QD 23 QD VCC 3 QE 22 QE SERIAL DATA INPUT A 4 A QF 21 QF ENABLE INPUT OE 5 OE QG 20 QG LATCH CLOCK INPUT CKL 6 CKL QH 19 QH 7 R QI 18 QI CKS 8 CKS QJ 17 QJ GND 9 QK 16 QK PARALLEL DATA OUTPUTS DIRECT RESET INPUT R SHIFT CLOCK INPUT SERIAL DATA OUTPUT SQP PARALLEL DATA OUTPUTS 10 SQP QL 15 QL QO 11 QO QM 14 QM QP 12 QP QN 13 QN PARALLEL DATA OUTPUTS FUNCTIONAL DESCRIPTION As R8A66161 uses silicon gate CMOS process. It realizes high-speed and high-output currents sufficient for LED drive while maintaining low power consumption and allowance for high noises. Each bit of a shift register consists of two flip-flop having independent clocks for shifting and latching. As for clock input, shift clock input CKS and latch clock input CKL are independent from each other, shift and latch operations being made when “L” changes to “H”. Serial data input A is the data input of the first-step shift register and the signal of A shifts shifting registers one by one when a pulse is impressed to CKS. When A is “H”, the signal of “L” shifts. When the pulse is impressed to CKL, the contents of the shifting register at that time are stored in a latching register, and they appear in the parallel data outputs from QA ~ QP. Outputs QA ~ QP are open drain outputs. To extend the number of bits, use the serial data output SQP which shows the output of the shifting register of the 16th bit. When reset input R is changed to “L”, QA ~ QP and SQP are reset. In this case, shifting and latching register are set. If “H” is impressed to output enable input OE, QA ~ QP reaches the high impedance state, but SQP does not reach the high impedance state. Furthermore, change in OE does not affect shift operation. FUNCTION TABLE (Note: 1) Input Operation mode Reset Shift Latch operation R CKS CKL L X X A X OE X QA Z X H L ↑ X L QA L QB QC QD Z Z Z QE Z QF Z QG QH Z Z QI Z QJ Z QK QL QM Z Z Z QN QO Z Z Remarks QP SQP Z L 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QB QC QD QE QF QG QH QI QJ QK QL QM QN QO QP qO0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 qA qB qC qD qE qF qG qH qI qJ qK qL qM qN qO0 qO0 Output Lighting H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QB QC QD QE QF QG QH QI QJ QK QL QM QN QO QP qO0 qA0 qB0 qC0 qD0 qE0 qF0 qG0 qH0 qI 0 qJ 0 qK0 qL 0 qM0 qN0 qO0 qO0 Output Lights-out L Shift t1 H Latch t2 H ↑ X Shift t1 H ↑ X L L Latch t2 H X ↑ X L QA Z X X X X H Z Output disable Note1: ↑ 0 Q X q0 q t1, t2 Z Serial data output Parallel data output Z Z : Change from low-level to high-level : Output state Q before CKL changed : Irrelevant : Contents of shift register before CKS changed : Contents of shift register : t2 is set after t1 is set : High impedance REJ03F0262-0100 Rev.1.00 Jan.16.2008 page 2 of 7 Z Z Z Z Z Z Z Z Z Z Z Z Z qP R8A66161DD/SP ABSOLUTE MAXIMUM RATINGS (Ta=-40~+85℃, unless otherwise noted) Symbol VCC VI VO Parameter Conditions Ratings -0.5 ~ +7.0 -0.5 ~ VCC+0.5 -0.5 ~ VCC+0.5 50 ±25 -20, +410 500 -65 ~+150 Supply voltage Input voltage Output voltage IO Output current per output pin ICC Pd Tstg Supply / GND current Power dissipation Storage temperature range QA ~ QP SQP VCC, GND (Note 2) Unit V V V mA mA mW ℃ Note 2: R8A66161SP; Ta=-40∼+70℃, Ta=+70∼+85℃ are derated at -6mW/℃. RECOMMENDED OPERATING CONDITIONS (Ta=-40~+85℃, unless otherwise noted) Symbol Parameter VCC Supply voltage VI VO Topr Input voltage Output voltage Operating temperature range REJ03F0262-0100 Rev.1.00 Jan.16.2008 page 3 of 7 5.0V support 3.3V support Min. 4.5 3.0 0 0 -40 Limits Typ. 5.0 3.3 Max. 5.5 3.6 VCC VCC +85 Unit V V V V ℃ R8A66161DD/SP ELECTRICAL CHARACTERISTICS ■5.0V version support specifications (Ta=-40~+85 C,Vcc=4.5V~5.5V, unless otherwise noted) o Symbol VT+ VT- VOL Parameter Test conditions Positive-going threshold voltage Negative-going threshold voltage Low-level output voltage QA ~ QP Min. VO=0.1V, VCC-0.1V |IO|=20uA VO=0.1V, VCC-0.1V |IO|=20uA IOL= 20uA VI=VT+,VTVCC=4.5V IOL= 24mA (Note3) Limits Typ. Unit Max. 0.35xVCC 0.70xVCC V 0.20xVCC 0.55xVCC V 0.10 0.53 IOL= 40mA VOH High-level output voltage SQP VI=VT+,VTVCC=4.5V IOH= -20uA VCC-0.1 IOH= -4mA 3.66 VOL Low-level output voltage SQP VI=VT+,VTVCC=4.5V IOL= 20uA 0.10 IOL= 4mA 0.53 IIH High-level input current VI=VCC, VCC=5.5V IIL Low-level input current VI=GND, VCC=5.5V IO Maximum output leakage current VI=VT+,VTVCC=5.5V QA ~ QP V 0.94 V V 5 uA -5 uA VO=VCC 10 VO=GND -10 uA ICC Quiescent supply current VI=VCC,GND, VCC=5.5V 200 uA Note 3: R8A66161 is used under the condition of an output current IOL=40mA, the number of simultaneous drive outputs is restricted as shown in the Duty Cycle – IOL of TYPICAL CHARACTERISTICS. ■3.3V version support specifications (Ta=-40~+85 C,Vcc=3.0V~3.6V, unless otherwise noted) o Symbol VT+ VT- Parameter Test conditions Positive-going threshold voltage Negative-going threshold voltage VvOL Low-level output voltage VOH High-level output voltage VOL Low-level output voltage QA ~ QP VO=0.1V, VCC-0.1V |IO|=20uA VO=0.1V, VCC-0.1V |IO|=20uA IOL= 20uA VI=VT+,VTVCC=3.0V IOL= 12mA Min. Limits Typ. Unit Max. 0.35xVCC 0.70xVCC V 0.20xVCC 0.55xVCC V 0.10 0.54 IOL= 20mA V 0.72 SQP VI=VT+,VTVCC=3.0V IOH= -20uA VCC-0.1 IOH= -2mA 2.60 SQP VI=VT+,VTVCC=3.0V IOL= 20uA 0.10 IOL= 2mA 0.40 V V IIH High-level input current VI=VCC, VCC=3.6V 5 uA IIL Low-level input current VI=GND, VCC=3.6V -5 uA IO Maximum output leakage current VI=VT+,VTVCC=3.6V ICC Quiescent supply current QA ~ QP VO=VCC 10 VO=GND -10 VI=VCC,GND, VCC=3.6V REJ03F0262-0100 Rev.1.00 Jan.16.2008 page 4 of 7 200 uA uA R8A66161DD/SP o SWITCHING CHARACTERISTICS (Ta=-40~+85 C,Vcc=5.0V or 3.3V) Symbol fmax tPLH tPHL tPHL tPLZ tPZL tPLZ tPZL tPLZ CI Test conditions Parameter Maximum clock frequency Output “L”-“H” and “H”-“L” propagation time Output “H”-“L” propagation time Output “L”-“Z” propagation time Output “Z”-“L” propagation time Output “L”-“Z” propagation time Output “Z”-“L” propagation time Output “L”-“Z” propagation time Input capacitance CKS - SQP 5.0V specification Min. Typ. Max. 4 125 125 3.3V specification Min. Typ. Max. 3.3 150 150 125 150 ns 200 220 ns 125 150 ns 200 220 ns 125 150 ns 200 220 ns 10 10 pF 5.0V specification Min. Typ. Max. 3.3V specification Min. Typ. Max. Unit R – SQP R - QA ~ QP (turned off) CKL - QA ~ QP (turned on) CKL - QA ~ QP (turned off) OE - QA ~ QP (turned on) OE - QA ~ QP (turned off) CL=50pF RL=1KΩ (Note 4) Unit MHz ns ns o TIMING REQUIREMENTS (Ta=-40~+85 C,Vcc=5.0V or 3.3V) Symbol tw Test conditions Parameter tsu CKS, CKL, R pulse width A setup time with respect to CKS tsu CKS setup time with respect to CKL (Note 4) 125 150 ns 125 150 ns 125 150 ns th A hold time with respect to CKS 15 20 ns trec R recovery time with respect to CKS, CKL 70 80 ns Note 4 : Test Circuit INPUT VCC VCC RL QA∼QP DUT PG 50Ω SQP GND CL CL (1) The pulse generator (PG) has the following characteristics (10%~90%). :tr = 6ns, tf = 6ns. (2) The capacitance CL includes stray wiring capacitance and the probe input capacitance. REJ03F0262-0100 Rev.1.00 Jan.16.2008 page 5 of 7 R8A66161DD/SP TYPICAL CHARACTERISTICS ・Repetition frequency > 10 Hz ・Numbers in ○ indicate the number of output circuits that operate simultaneously. ・Current values are per circuit. Duty Cycle-IOL Characteristics Duty Cycle-IOL Characteristics IOL (mA) IOL (mA) From top to bottom Vcc=4.5V, Ta＝ 25℃ 0 20 40 60 Vcc=4.5V, Ta＝ 85℃ 80 100 Duty Cycle (%) Duty Cycle (%) TIMING DIAGRAM tw VCC VCC CKS 50% 50% CKL 50% tPLH tPHL 50% 50% 50% GND GND tPZL VOH SQP VOL 50% QA ∼ QP VOL tPLZ tw VCC 50% R 50% trec GND QA ∼ QP VOL VCC CKS 50% GND tPHL VCC 50% A VOH tsu 50% SQP 50% GND th VOL tPLZ VCC CKS 50% GND QA ∼ QP 10% VOL VCC OE 10% 50% VCC CKS 50% GND 50% GND tPLZ tPZL tsu tw VCC QA ∼ QP 50% 10% CKL VOL REJ03F0262-0100 Rev.1.00 Jan.16.2008 page 6 of 7 50% 50% GND R8A66161DD/SP PACKAGE OUTLINE Product name R8A66161DD R8A66161SP Package 24pin DIP 24pin SOP RENESAS Code PRDP0024AF-A PRSP0024DF-A Previous Code 24P4X-A 24P2X-B All trademarks and registered trademarks are the property of their respective owners. REJ03F0262-0100 Rev.1.00 Jan.16.2008 page 7 of 7