MITSUBISHI M54974P

MITSUBISHI <CONTROL / DRIVER IC>
M54974P
Bi-CMOS 12-BIT SERIAL-INPUT LATCHED DRIVER
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
The M54974P is a semiconductor integrated circuit consisting of 12
stages of CMOS shift registers and latches with serial inputs and
serial or parallel outputs. It is based on Bi-CMOS process
technology, and has 12 bipolar drivers at the parallel outputs.
28
Latch input LATCH →
2
27
EN →
3
26 ← S-IN
Serial input
O12 ←
4
25 ← T
Clock
O11 ←
5
24
6
23
Parallel outputs
● Serial input and serial or parallel output
● Serial output enables cascade connection
● Built-in latch for each stage
7
Driver GND P-GND
● Enable input provides output control
8
● Low supply current (standby current ICC≤10µA)
9
● Serial I/O level is compatible with typical CMOS devices
High withstand voltage (BVCEO≥30V)
● Driver features:
M54974P
1
Enable input
FEATURES
Capable of large drive currents (IO(max)=300mA)
Logic power
supply
L-GND Logic GND
Serial output S-OUT ←
L-VCC
P-VCC
22
P-GND Driver GND
21
20
O10 ← 10
19 → O1
O9 ← 11
18 → O2
O8 ← 12
17 → O3
O7 ← 13
16 → O4
O6 ← 14
15 → O5
Parallel outputs
● Wide operating temperature range Ta=-20 – +75°C
APPLICATION
Dot drivers for thermal print heads. Serial/parallel conversion.
Output power
supply
Parallel outputs
Outline 28P4B
Drivers for relay and solenoids.
registers is shifted sequentially.
FUNCTION
The serial output S-OUT is used to connect multiple M54974Ps to
The M54974P consists of 12 stages of D-type flip flops connected
expand the number of parallel outputs. S-OUT is connected to S-IN
to 12 latches.
of the next stage.
Data is input to serial input S-IN, and clock pulses are applied to
When the clock pulse changes from low to high, latch input
clock input T. When the clock changes from low to high, the input
(LATCH) is high and output enable input (EN) is low the serial input
data enters the first shift register and data already in the shift
data at S-IN appears at output O1 and the other data already
BLOCK DIAGRAM
Parallel outputs
O1
19
O2
18
O3
17
O4
16
O5
15
O6
14
O7
13
O8
12
O9
11
O10
10
O11
5
O12
4
6
P-GND
Driver GND
20
7
21
8
22
9
23
L-VCC
24 P-VCC
Output power supply
EN
3
Enable input
L-VCC
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
DQ
T
DQ
T
DQ
T
DQ
T
DQ
T
DQ
T
DQ
T
DQ
T
DQ
T
DQ
T
DQ
T
DQ
T
LATCH
2
Latch input
S-IN
26
Serial input
T
25
Clock
P-GND
Driver GND
L-VCC
23 Logic power supply
L-GND
27 Logic GND
1
S-OUT
Serial output
MITSUBISHI <CONTROL / DRIVER IC>
M54974P
Bi-CMOS 12-BIT SERIAL-INPUT LATCHED DRIVER
present is shifted sequentially to outputs O2 through O12.
input should be kept high (setting the outputs O1 through O12 off)
The parallel outputs are inverted.
until input data is set and the internal logic is initialized.
When the latch input is held low, the latch retains the stored data.
L-GND is the GND of CMOS logic circuit and P-GND is the GND of
When the EN input is high, outputs O1 through O12 all turn off. As
output driver circuits O1 through O12 which employ bipolar
the internal logic is unstable when the power is turned on, the EN
transistors capable of large drive currents.
TIMING CHART
Serial input
Clock
S-IN
T
Latch input LATCH
Enable input
EN
O1
O2
O3
O4
O5
O6
Parallel outputs
O7
O8
O9
O10
O11
O12
Serial output S-OUT
* The shaded area shows the unstable state.
MITSUBISHI <CONTROL / DRIVER IC>
M54974P
Bi-CMOS 12-BIT SERIAL-INPUT LATCHED DRIVER
INPUT/OUTPUT CIRCUIT DIAGRAM
1
Inputs with pullup resistor
2
(EN, LATCH)
Inputs with pulldown resistor
(T, S-IN)
L-VCC
L-VCC
RIN
RIN
L-GND
3
Serial output
L-GND
4
(S-OUT)
Parallel outputs
(O1 – O12)
P-VCC
L-VCC
L-GND
P-GND
L-GND
MITSUBISHI <CONTROL / DRIVER IC>
M54974P
Bi-CMOS 12-BIT SERIAL-INPUT LATCHED DRIVER
ABSOLUTE MAXIMUM RATINGS (Ta=-20 to 75°C, unless otherwise noted)
Symbol
Parameter
VCC
VI
Supply voltage
Input voltage
VO
Output voltage
IO
Pd
Topr
Tstg
Output current
Power dissipation
Operating temperature
Storage temperature
Conditions
P-VCC, L-VCC
S-IN, LATCH, T, EN
S-OUT
O1 – O12 : OFF
O1 – O12
Ta=25°C
Ratings
Unit
-0.5 – 8
-0.5 – VCC+0.5
-0.5 – VCC+0.5
-0.5 – 30
400
2.5
-20 – 75
-55 – 125
V
V
V
mA
W
°C
°C
RECOMMENDED OPERATING CONDITION (Ta=-20 to 75°C, unless otherwise noted)
Symbol
Parameter
VCC
VO
Supply voltage
Output apply voltage
IO
Output current (per circuit)
Conditions
P-VCC, L-VCC
O1 – O12 : OFF
All outputs go in the ON state simultaneously.
Duty cycle < 50%, Ta < 25°C
Min.
Limits
Typ.
4
5
Max.
Unit
6
30
V
V
300
mA
ELECTRICAL CHARACTERISTICS (Ta=25°C, L-VCC=5V, P-VCC=5V, unless otherwise noted)
Symbol
VIH
VIL
RIN
VOH
VOL
IOH
IOL
VOL1
VOL2
VOL3
IOLK
ICC1
ICC2
ICC3
Parameter
Test conditions
High-level input voltage
Low-level input voltage
Input resistance
High-level output voltage
Low-level output voltage
High-level output current
Low-level output current
S-OUT
S-OUT
S-OUT
S-OUT
Low-level output voltage
O1 – O12
Output leak current
O1 – O12
Supply current (L-VCC)
Output supply current (P-VCC)
Ta=-20 – 75°C
|IO|≤1µA
VOH=4.5V
VOL=0.4V
Min.
0.7VCC
0
50
4.9
Limits
Typ.
Max.
VCC
0.3VCC
0.1
-100
400
Unit
V
V
kΩ
V
V
µA
µA
IOL=120mA
0.4
V
IOL=400mA
VO=30V
Input: open, All driver outputs: OFF
One driver output is ON.
One driver output is ON.
0.7
50
10
0.2
14
V
µA
µA
mA
mA
MITSUBISHI <CONTROL / DRIVER IC>
M54974P
Bi-CMOS 12-BIT SERIAL-INPUT LATCHED DRIVER
TIMING REQUIREMENTS (Ta=-20 to 75°C, unless otherwise noted)
Symbol
f(T)
tw(T)
tw(L)
tsu
th
td(T-L)
tr(T)
tf(T)
Parameter
Test conditions
Min.
Limits
Typ.
2
Input duty: 40 – 60%
Clock frequency
Clock pulse width
Latch pulse width
Data setup time
Data hold time
Clock-latch time
Clock pulse rise time
Clock pulse fall time
Max.
200
200
100
100
400
500
500
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
TIMING CHART
Serial input
2.5V
S-IN
2.5V
tsu
th
90%
T
Clock
2.5V
90%
2.5V
10%
10%
tw(T)
tr(T)
tr(T)
td(T-L)
Latch input
2.5V
LATCH
2.5V
tw(L)
SWITCHING CHARACTERISTICS (Ta=25°C, VCC=5V, unless otherwise noted)
Symbol
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
Parameter
Test conditions
Low-to-high-level output propagation time, From input T to output S-OUT
High-to-low-level output propagation time, From input T to output S-OUT
Low-to-high-level output propagation time, From input T to output ON
High-to-low-level output propagation time, From input T to output ON
Low-to-high-level output propagation time, From input EN to output ON
High-to-low-level output propagation time, From input EN to output ON
VIH=5V
VIL=0V
RL(S-OUT)=∞
RL(ON)=100Ω
(N=1–12)
CL=15pF
Min.
Limits
Typ.
(0.15)
(0.15)
(2)
(1)
(2)
(1)
TIMING CHART
Clock
T
2.5V
2.5V
tPHL
tPLH
Serial output S-OUT
2.5V
Enable input
2.5V
EN
tPLH
Output
ON
2.5V
2.5V
tPHL
2.5V
tPLH
2.5V
tPHL
2.5V
2.5V
Max.
0.3
0.3
10
5
10
5
Unit
µs
µs
µs
µs
µs
µs
MITSUBISHI <CONTROL / DRIVER IC>
M54974P
Bi-CMOS 12-BIT SERIAL-INPUT LATCHED DRIVER
TEST CIRCUIT
Input
VCC
RL
PG
Output
M54974P
CL
50Ω
The input waveform: tr ≤ 20ns, tf ≤ 20ns
The capacitance CL includes the stray wiring
capacitance and probe input capacitance.
TYPICAL CHARACTERISTICS
Thermal derating
(Absolute maximum rating)
Duty cycle vs. allowable
output current
400
3.0
1
7
Output current Io (mA)
Power dissipation Pd (W)
8
2.0
1.0
10
11
12
200
Collector current : current per circuit
Repetitive frequency ≥ 10HZ
The figure in a circle shows the number
of output circuits which operate
simultaneously.
Ta = 25°C, VCC = 6.0V
Mounted on a board
100
0
0
0
25
50
75
0
100
Ambient temperature Ta (°C)
400
1
4
5
300
6
7
8
9
200
10
Collector current : current per circuit
Repetitive frequency ≥ 10HZ
The figure in a circle shows the number
of output circuits which operate
simultaneously.
Ta = 75°C, VCC = 6.0V
Mounted on a board
100
0
0
20
40
60
Duty cycle (%)
80
20
40
60
Duty cycle (%)
Duty cycle vs. allowable
output current
Output current Io (mA)
9
300
11
12
100
–
3
80
100
–
6