Standard ICs 8-bit shift register and latch driver BU2114 / BU2114F The BU2114 and BU2114F are CMOS ICs with low power consumption, and are equipped with an 8-bit shift register latch. Data in the shift register can be latched asynchronously. The outputs (O1 to O8) are open drain outputs (because there is no protection diode, a maximum voltage above VDD, of up to 7V, can be applied), and one output can drive 36 mA. A total output of up to 150 mA can be driven (when using static operation). Applications •These are designed for a wide range of applications in microcomputer peripheral circuits, such as in industrial equipment, office telephones, audio visual equipment, and expansion input and output boards. •1)Features The CMOS configuration enables low power con- 3) Latch to 8-bit shift register provided, enabling drive of up to 150mA. (ISINK = 36mA) 4) Cascade connections possible. sumption. 2) Open drain output. •Absolute maximum ratings (unless otherwise noted, Ta = 25°C) Parameter Symbol Limits Unit VDD – 0.3 ~ + 7.0 V VIN Applied voltage Input voltage – 0.3 ~ VDD0.3 V Operating temperature Topr – 25 ~ + 75 °C Storage temperature Tstg – 55 ~ + 150 Input protection diode current Power dissipation ± 20 ID BU2114 1100∗1 Pd BU2114F °C mA mW 400∗2 ∗1 Power dissipation is reduced by 8.8mW for each increase in Ta of 1°C over 25°C. ∗2 Power dissipation is reduced by 3.2mW for each increase in Ta of 1°C over 25°C. •Recommended operating conditions (unless otherwise noted, Ta = 25°C) Parameter Recommend voltage Input voltage Output voltage Symbol Min. Typ. Max. Unit VDD 4.5 5.0 5.5 V Conditions VIN 0 — VDD V SIN, CK, LATCH, EN, RST VOUT 0 — VDD V SOUT 䊊Not designed for radiation resistance. 1 Standard ICs BU2114 / BU2114F •Logic circuit diagram 01 02 03 04 05 06 07 08 EN LATCH D Q D Q D Q D Q D Q D Q D Q D Q CQB CQB CQB CQB CQB CQB CQB CQB R R R R R R R R SIN CK SOUT D Q D Q D Q D Q D Q D Q D Q D Q CQB CQB CQB CQB CQB CQB CQB CQB R R R R R R R R RST •Pin assignments SIN VDD CK 01 LATCH 02 SOUT 03 EN 04 RST 05 GND 06 GND 07 GND 08 Fig.1 2 Standard ICs BU2114 / BU2114F •Pin descriptions Pin No. Symbol I/O Function 1 SIN I Serial data input pin 2 CK I Shift clock for shift register 3 LATCH I Setting this pin to "L" holds the latch output. While it is "H", latch output changes simultaneously when the shift register output changes. 4 SOUT O This is the output for the final-stage shift register. This is the Enable pin for O1 to O8. When this pin is "L", the latch output appears as is. 5 EN I When the output is "H", however, output QN is "L", and when the latch output is "L", Qn becomes HighZ 6 RST I 7 GND — Resets the shift register and latch. 0V power supply 8 GND — 0V power supply 9 GND — 0V power supply 10 O8 O Latch output for 8th stage of shift register 11 O7 O Latch output for 7th stage of shift register 12 O6 O Latch output for 6th stage of shift register 13 O5 O Latch output for 5th stage of shift register 14 O4 O Latch output for 4th stage of shift register 15 O3 O Latch output for 3rd stage of shift register 16 O2 O Latch output for 2nd stage of shift register 17 O1 O Latch output for 1st stage of shift register 18 VDD — + VDD power supply Note 1) O1 to O8 are open drain output, and when the shift register output is "H", the output level goes "L". 3 Standard ICs BU2114 / BU2114F •Electrical characteristics (unless otherwise noted, Ta = 25°C, V DD Parameter Symbol Min. Typ. = 5.0V) Max. Unit Conditions Input low level voltage VIL 0 — 1.5 V SIN, LATCH, EN Input high level voltage VIH 3.5 — 5.0 V SIN, LATCH, EN Output low level current ISL — — 6 mA SOUT (VL = 0.4) Output high level current ISH — — –6 mA SOUT (VL = VDD – 0.4) Schmitt trigger "H" threshold value VP 2.31 — 3.28 V CK, RST Schmitt trigger "L" threshold value VN 1.5 — 2.58 V CK, RST Schmitt trigger hysteresis width VH 0.35 0.75 — V CK, RST Output low level voltage VOL VOL — — — — 0.15 0.4 V V O1 ~ O8ID = 12mA O1 ~ O8ID = 36mA Output leakage current IL — — ± 10 µA — Current dissipation IDD — 1 100 µA Pull-up resistance RUP 35 50 68 kΩ — Pull-down resistance RDN 35 50 68 kΩ — 4 VDD or GND Standard ICs BU2114 / BU2114F •Timing characteristics (unless otherwise noted, Ta = 25°C, V DD Parameter Symbol Conditions f Input duty 50% tcw — Clock frequency Clock pulse width = 5.0V) Min. Typ. Max. Unit 5 MHz 100 — — ns Latch pulse width trw — 100 — — ns Data setup time tsu CK→SIN 100 — — ns Data hold time th CK→SIN 100 — — ns Clock latch time tdtl — 100 — — ns 2.5V 2.5V SIN tsu th CK tcw tdtl LATCH trw Fig.2 Timing conditions 5 Standard ICs BU2114 / BU2114F •Switching characteristics (unless otherwise noted, Ta = 25°C, V Parameter Symbol Conditions DD = 5.0V) Min. Typ. Max. Unit Output "L - H" propagation time Input CK to output SOUT tSLH — — 100 ns Output "H - L" propagation time Input CK to output SOUT tSPLH — — 100 ns Output "L - H" propagation time Input CK to output ON tOLH — — 200 ns Output "H - L" propagation time Input CK to output ON tOHL — — 200 ns Output "L - H" propagation time Input EN to output ON tELH — — 100 ns Output "H - L" propagation time Input EN to output ON tEHL — — 100 ns VIH = 5v VIL = 0v CK tSLH tSLH SOUT EN tOLH tOHL tELH tEHL On Note) Measured with pull-up resistance of 1.0kΩ and load of 20pF applied to terminals O1 to O8. Fig.3 Switching characteristic 6 Standard ICs BU2114 / BU2114F •Timing chart + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CK RST SIN LATCH EN SOUT 01 02 03 04 05 06 07 08 Fig.4 • Input / output circuits 01 to 08 output SOUT output Pull-down input Pull-up input Fig.5 •Application example Expansion port 01 ~ 08 01 ~ 08 01 ~ 08 SIN BU2114 SOUT SIN BU2114 SOUT SIN BU2114 LATCH EN RST CK Fig.6 7 Standard ICs BU2114 / BU2114F •External dimensions (Units: mm) BU2114 BU2114F 22.9 ± 0.3 11.2 ± 0.2 10 0.3 ± 0.1 2.54 0.5 ± 0.1 0° ~ 15° 18 10 1 9 1.27 0.4 ± 0.1 0.15 ± 0.1 5.4 ± 0.2 7.8 ± 0.3 7.62 1.8 ± 0.1 9 0.51Min. 3.29 ± 0.2 3.95 ± 0.3 1 0.11 6.5 ± 0.3 18 0.3Min. 0.15 DIP18 8 SOP18