® RT9040 DDR Termination Regulator General Description Features The RT9040 is a sink/source tracking termination regulator. It is specifically designed for low-cost and low-external component count systems. The RT9040 possesses a high speed operating amplifier that provides fast load transient response and only requires a minimum 20μF of ceramic output capacitance. The RT9040 supports remote sensing functions and all features required to power the DDRI / DDRII / DDRIII and Low Power DDRIII VTT bus termination according to the JEDEC specification. In addition, the RT9040 provides an open drain PGOOD signal to monitor the output regulation and an EN signal that can be used to discharge VTT during S3 (suspend to RAM) for DDR applications . VIN Input Voltage Range : 1.1V to 3.5V VCNTL Input Voltage Range : 2.375V to 5.5V MLCC Stable PGOOD to Monitor Output Regulation ±10mA Reference (REFOUT) Meet DDRI, DDRII JEDEC Spec Supports DDRIII, Low Power DDRIII VTT Application Soft Start Function UVLO and OCP UVLO and OCP Protection Thermal Shutdown RoHS Compliant and Halogen Free The RT9040 is available in the thermal efficient WDFN10L 3x3 package. Ordering Information (2) Application Notebook/Desktop/Server Telecom/Datacom, GSM Base Station, LCD-TV/PDPTV ,Copier/Printer, Set-Top Box Pin Configurations (TOP VIEW) Pin 1 Orientation (2) : Quadrant 2, Follow EIA-481-D REFIN VIN VOUT PGND SENSE Package Type QW : WDFN-10L 3x3 (W-Type) Lead Plating System G : Green (Halogen Free and Pb Free) Z : ECO (Ecological Element with Halogen Free and Pb free) RoHS compliant and compatible with the current require- 4 5 11 10 9 8 7 6 VCNTL PGOOD GND EN REFOUT WDFN-10L 3x3 Marking Information RT9040GQW(2) Note : Richtek products are : 1 2 3 GND RT9040 G4= : Product Code G4=YM DNN YMDNN : Date Code ments of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. RT9040ZQW(2) G4 : Product Code G4 YM DNN Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS9040-04 January 2014 YMDNN : Date Code is a registered trademark of Richtek Technology Corporation. www.richtek.com 1 RT9040 Typical Application Circuit RT9040 2 VIN R1 10k 1 C1 10µF x 2 R2 10k C3 0.1µF Chip Enable 10 R3 100k REFIN PGOOD C2 1nF 6 REFOUT VCNTL VIN 9 PGND 7 EN GND VCNTL 2.5V/3.3V/5V Power Good Indicator VOUT 3 SENSE 5 REFOUT C4 4.7µF VOUT C5 10µF x 3 4 8, 11 (Exposed Pad) Functional Pin Description Pin No. Pin Name Pin Function 1 REFIN Reference Input. 2 VIN Supply Voltage for the LDO. 3 VOUT Power Output for the LDO. 4 PGND 5 SENSE 6 REFOUT Power Ground Output for the LDO. Voltage Sense Output for the LDO. Connect to positive terminal of the output capacitor or the load. Reference Output. Connect to GND through 0.1uF ceramic capacitor. 7 EN Chip Enable. For DDR VTT application, connect EN to SLP_S3. For any other application(s), use EN as the ON/OFF function. Signal Ground. Connect to negative terminal of the output capacitor. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. PGOOD Output. Indicates regulation. Connect to an internal open drain N-MOSFET. 2.5V, 3.3V or 5V power supply. A ceramic decoupling capacitor with a value between 1F and 4.7F is required. 8, GND 11 (Exposed Pad) 9 PGOOD 10 VCNTL Function Block Diagram EN VCNTL REFIN Control Logic Thermal Protection VIN + OCP - Buffer SENSE REFOUT VOUT OP + PGOOD Power Good GND Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 2 Driver + OCP - PGND is a registered trademark of Richtek Technology Corporation. DS9040-04 January 2014 RT9040 Absolute Maximum Ratings (Note 1) Supply Input Voltage, VIN, REFIN, VCNTL -------------------------------------------------------------------------Enable Voltage, EN ------------------------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C WDFN-10L 3x3 ------------------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2) WDFN-10L 3x3, θJA ------------------------------------------------------------------------------------------------------WDFN-10L 3x3, θJC ------------------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------Junction Temperature ----------------------------------------------------------------------------------------------------Storage Temperature Range -------------------------------------------------------------------------------------------ESD Susceptibility (Note 3) HBM (Human Body Model) ---------------------------------------------------------------------------------------------MM (Machine Model) ----------------------------------------------------------------------------------------------------- Recommended Operating Conditions 6V 6V 1.429W 70°C/W 8.2°C/W 260°C 150°C −65°C to 150°C 2kV 200V (Note 4) Supply Input Voltage, VCNTL ------------------------------------------------------------------------------------------ 2.375V to 5.5V Supply Input Voltage, VIN ------------------------------------------------------------------------------------------------ 1.1V to 3.5V Junction Temperature Range -------------------------------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range -------------------------------------------------------------------------------------------- −40°C to 85°C Electrical Characteristics (VIN = 1.8V, VEN = VCNTL = 3.3V, VREFIN = 0.9V, VSENSE = 0.9V, COUT = 10uF x 3, TA = 25°C, unless otherwise specification) Parameter Symbol Test Conditions Min Typ Max Unit VEN = 3.3V, No Load -- 0.9 2 mA VEN = 0V, VREFIN = 0, No Load -- 65 80 VEN = 0V, VREFIN > 0.4V, No Load -- 200 500 A Supply Current VCNTL Supply Current IVCNTL VCNTL Shutdown Current ISHDN_VCNTL VIN Supply Current IVIN VEN = 3.3V, No Load -- -- 2 mA VIN Shutdown Current ISHDN_VIN VEN = 0V, No Load -- 0.1 50 A IREFIN VEN = 3.3 V -- -- 1 A VIN = 1.5 V, VREFOUT = 0.75V (DDRIII), IOUT = 0A -10 -10 -10 1.25 -0.9 -0.75 -- -10 -10 -10 V mV V mV V mV –2A < IOUT < 2A 15 -- 15 mV Input Current REFIN Input Current Output VIN = 2.5 V, VREFOUT = 1.25 V (DDRI), IOUT = 0A Offset Voltage of Output DC Voltage VOUT Load Regulation VVOTOL VLOAD VIN = 1.8 V, VREFOUT = 0.9V (DDRII), I OUT = 0A Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS9040-04 January 2014 is a registered trademark of Richtek Technology Corporation. www.richtek.com 3 RT9040 Parameter Symbol VOUT Source Current I LIM_VOUT_sr Limit VOUT Sink Current I LIM_VOUT_sk Limit VOUT Discharge RDISCHARGE Resistance Power Good Comparator VOUT PGOOD Threshold V TH_PGOOD PGOOD Startup Delay Tpgdelay1 Output Low Voltage V LOW_PGOOD PGOOD Bad Delay Tpgdealy2 Leakage Current I LEAKAGE_PGOOD Test Conditions VCNTL = 5V (V OUT in PGOOD window) VCNTL = 5V (V OUT in PGOOD window) VREFIN = 0V, VOUT = 0.3V, VEN = 0V Min Typ Max Unit 3.5 -- 5.5 A 3.5 -- 5.5 A -- 18 25 23.5 20 17.5 PGOOD Hysteresis -- 5 -- Startup rising edge, VSENSE within 15% of REFOUT -- 2 -- ms -- -- 0.4 V -- 10 -- s -- -- 1 A 0.5 -- 1.8 V 360 390 420 -- 20 -- 15 -- 15 15 -- 15 15 -- 15 VREFOUT = 0V 10 40 -- mA VREFOUT = VIN 10 40 -- mA Wake up 2.2 2.3 2.375 V -- 50 -- mV PGOOD window lower threshold with respect to REFOUT ISINK = 4mA VSENSE is outside of the ±20% PGOOD window VSENSE = VREFIN (PGOOD high impedance), PGOOD = VCNTL + 0.2 V % REFIN and REFOUT REFIN Voltage Range V REFIN REFIN Under Voltage Lockout V UVLO_REFIN REFOUT Voltage Tolerance to VREFIN V TOL_REFOUT REFOUT Source I LIM_REFOUT_sr Current Limit REFOUT Sink Current I LIM_REFOUT_sk Limit UVLO / EN Logic Threshold UVLO Threshold High-Level Input Voltage Low-Level Input Voltage Hysteresis Voltage Logic Input Leakage Current Thermal Shutdown Thermal Shutdown Threshold V UVLO_VCNTL REFIN Rising Hysteresis 10mA < IREFOUT < 10mA, VREFIN = 1.25 V 10mA < IREFOUT < 10mA, VREFIN = 0.9 V 10mA < IREFOUT < 10mA, VREFIN = 0.75V Hysteresis mV V IN_H Enable 1.7 -- -- V V IN_L Enable -- -- 0.3 V V EN_hys Enable -- 0.5 -- V I LEAKAGE_EN Enable 1 -- 1 A Shutdown Temperature -- 160 -- Hysteresis -- 25 -- T SD Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 4 mV C is a registered trademark of Richtek Technology Corporation. DS9040-04 January 2014 RT9040 Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS9040-04 January 2014 is a registered trademark of Richtek Technology Corporation. www.richtek.com 5 RT9040 Typical Operating Characteristics Shutdown Current vs. Temperature 80 1100 79 Shutdown Current (µA)1 Supply Current (µA) Supply Current vs. Temperature 1150 1050 1000 950 900 850 800 750 78 77 76 75 74 73 700 VIN = 2.5V, REFIN = 0V, VCNTL = 5V, VEN = 0V VIN = 2.5V, REFIN = 1.25V, VCNTL = VEN = 5V 650 -40 -25 -10 5 20 35 50 65 80 72 -40 -25 -10 95 110 125 5 50 65 80 95 110 125 DDRI Output Voltage vs. Load Current Standby Current vs. Temperature 364 1.2495 362 VCNTL = 3.3V 1.2490 360 358 Output Voltage (V) Standby Current (µA) 35 Temperature (°C) Temperature (°C) VIN = 1.5V VIN = 1.8V VIN = 2.5V 356 354 352 350 348 1.2485 1.2480 1.2475 1.2470 1.2465 VCNTL = 5V 1.2460 346 VIN = 2.5V, REFIN = 1.25V, VEN = VCNTL VCNTL = 5V, VEN = 0V 344 1.2455 -40 -25 -10 5 20 35 50 65 80 95 110 125 0 0.25 0.5 Temperature (°C) 0.75 1 1.25 1.5 1.75 2 Load Current (A) DDRII Output Voltage vs. Load Current DDRIII Output Voltage vs. Load Current 0.74365 0.8990 VCNTL = 3.3V 0.8985 VCNTL = 5V 0.74360 0.8980 Output Voltage (V) Output Voltage (V) 20 0.8975 0.8970 0.8965 VCNTL = 5V 0.8960 0.74355 0.74350 0.74345 VCNTL = 3.3V 0.74340 0.8955 VIN = 1.5V, REFIN = 0.75V, VEN = VCNTL VIN = 1.8V, REFIN = 0.9V, VEN = VCNTL 0.74335 0.8950 0 0.25 0.5 0.75 1 1.25 1.5 1.75 Load Current (A) Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 6 2 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 Load Current (A) is a registered trademark of Richtek Technology Corporation. DS9040-04 January 2014 RT9040 DDRI Output Voltage vs. Load Current DDRII Output Voltage vs. Load Current 1.2464 0.8964 0.8962 VCNTL = 5V Output Voltage (V) Output Voltage (V) 1.2462 1.2460 1.2458 VCNTL = 3.3V 1.2456 1.2454 VCNTL = 5V 0.8960 VCNTL = 3.3V 0.8958 0.8956 0.8954 1.2452 VIN = 2.5V, REFIN = 1.25V, VEN = VCNTL VIN = 1.8V, REFIN = 0.9V, VEN = VCNTL 0.8952 1.2450 -1.5 -1.25 -1 -0.75 -0.5 -0.25 -1.5 0 -1.25 -1 -0.75 -0.5 Load Current (A) Load Current (A) DDRIII Output Voltage vs. Load Current Power On -0.25 0 0.7462 VIN = 1.8V, REFIN = 0.9V Output Voltage (V) 0.7460 REFOUT (1V/Div) VCNTL = 5V 0.7458 VCNTL = 3.3V 0.7456 VEN (5V/Div) 0.7454 0.7452 VOUT (1V/Div) 0.7450 PGOOD (5V/Div) VIN = 1.5V, REFIN = 0.75V, VEN = VCNTL ENON = 3.3V, VCNTL = 3.3V, No Load 0.7448 -1.5 -1.25 -1 -0.75 -0.5 -0.25 Time (400μs/Div) 0 Load Current (A) 1.25VOUT @ ±1.5A Transient Response Power Off VIN = 1.8V, REFIN = 0.9V REFOUT (1V/Div) VIN = 2.5V, REFIN = 1.25V ΔVOUT (20mV/Div) VEN (5V/Div) VOUT (1V/Div) PGOOD (5V/Div) IOUT (2A/Div) ENOFF = 0V, VCNTL = 3.3V, No Load Time (200ns/Div) Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS9040-04 January 2014 VCNTL = VEN = 3.3V, COUT = 10μF x 3 Time (200μs/Div) is a registered trademark of Richtek Technology Corporation. www.richtek.com 7 RT9040 0.75VOUT @ ±1.5A Transient Response 0.9VOUT @ ±1.5A Transient Response VIN = 1.5V, REFIN = 0.75V VIN = 1.8V, REFIN = 0.9V ΔVOUT (20mV/Div) ΔVOUT (20mV/Div) IOUT (2A/Div) IOUT (2A/Div) VCNTL = VEN = 3.3V, COUT = 10μF x 3 Time (200μs/Div) VCNTL = VEN = 3.3V, COUT = 10μF x 3 Time (200μs/Div) 1.25VREFOUT @ ±15mA Transient Response VIN = 2.5V, REFIN = 1.25V ΔVREFOUT (10mV/Div) IOUT (20mA/Div) VCNTL = VEN = 3.3V, COUT = 0.1μF Time (400μs/Div) Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 8 is a registered trademark of Richtek Technology Corporation. DS9040-04 January 2014 RT9040 Application Information The RT9040 is a sink/source tracking termination regulator. Operation State Setting It is specifically designed for low-cost and low-external component count systems such as notebook PC applications. The RT9040 possesses a high speed operating amplifier that provides fast load transient response and only requires a 10μF ceramic input capacitor and two 10μF ceramic output capacitors. The EN pin could be connected to SLP_S3 signal for DDR VTT application. Both VOUT and REFOUT are turned on at normal state( EN = High, REFIN >0.39V). In standby state( EN = Low, REFIN >0.39V), REFOUT voltage will be kept alive to discharge VOUT voltage via internal circuit and left VOUT high impedance. When EN = Low and REFIN <0.39V, the RT9040 enter shutdown state, both VOUT and REFOUT will be turned off and discharged to ground via internal MOSFETs. Table 1 summarizes the abovementioned operation state setting, and figure 1 shows a typical start up and shutdown timing diagram. REFOUT Regulator REFOUT is a reference output voltage with source/sink current capability up to 10mA. To ensure stable operation, a 0.1μF ceramic capacitor connected between REFOUT and GND is recommended. Table1. Operation State Settling Capacitor Selection To achieve best performance of the RT9040, it is recommended to follow the following descriptions for capacitor selection. STATE Normal Standby Shutdown EN High Low Low REFIN > 0.39V > 0.39V < 0.39V VOUT ON OFF OFF REFOUT ON ON OFF VCNTL Capacitor : Add a ceramic capacitor 4.7μF placed to VCNTL pin as close as possible to stabilize the supply voltage (2.5V, 3.3V or 5.0V rail) from any parasitic impedance from the supply. VIN Capacitor : Good bypassing is recommended from VIN to GND to improve transient response. It is recommended to place two 10μF or greater input capacitor located as close as possible to the IC the capacitor must be placed at less than 0.5 inch from the VIN pin. VCNTL VIN 0.37V 0.39V REFIN REFOUT EN VOUT PGOOD 2ms Figure 1. Typical Start Up and Shutdown Timing Diagram VOUT Capacitor : For stable operation, the total capacitance of the VTT output terminal must be greater than 20μF. The RT9040 is designed specifically to work with low ESR ceramic output capacitor in space-saving and performance consideration. Larger output capacitance can reduce the noise and improve load transient response, stability and PSRR. Three 10μF ceramic capacitors are used in the typical application circuit. The output capacitor should be located near the VOUT pin as close as possible. Thermal Considerations For continuous operation, do not exceed absolute maximum operation junction temperature. The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula : PD(MAX) = (TJ(MAX) − TA) / θJA Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS9040-04 January 2014 is a registered trademark of Richtek Technology Corporation. www.richtek.com 9 RT9040 Where T J(MAX) is the maximum operation junction temperature, TA is the ambient temperature and the θJA is the junction to ambient thermal resistance. For recommended operating conditions specification, where TJ(MAX) is 125°C and TA is the maximum ambient temperature. The junction to ambient thermal resistance θJA is layout dependent. For WDFN-10L 3x3 packages, the thermal resistance θJA is 70°C/W on the standard JEDEC 51-7 four layers thermal test board. The maximum power dissipation at TA = 25°C can be calculated by following formula : PD(MAX) = (125°C − 25°C) / (70°C/W) = 1.429W for WDFN-10L 3x3 packages The maximum power dissipation depends on operating ambient temperature for fixed T J(MAX) and thermal resistance θJA. The Figure 2 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power allowed. Maximum Power Dissipation (W) 1.60 Four Layers PCB 1.40 1.20 WDFN-10L 3x3 1.00 0.80 0.60 0.40 0.20 0.00 0 25 50 75 100 125 Ambient Temperature (°C) Figure 2. Derating Curve of Maximum Power Dissipation Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 10 is a registered trademark of Richtek Technology Corporation. DS9040-04 January 2014 RT9040 Outline Dimension D2 D L E E2 1 e SEE DETAIL A 2 b 2 1 DETAIL A Pin #1 ID and Tie Bar Mark Options A A1 1 A3 Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 2.950 3.050 0.116 0.120 D2 2.300 2.650 0.091 0.104 E 2.950 3.050 0.116 0.120 E2 1.500 1.750 0.059 0.069 e L 0.500 0.350 0.020 0.450 0.014 0.018 W-Type 10L DFN 3x3 Package Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. DS9040-04 January 2014 www.richtek.com 11