RT9041E - Richtek

®
RT9041E
500mA, Low Voltage, LDO Regulator with External Bias Supply
General Description
The RT9041E is a low voltage, low dropout linear regulator
with an external bias supply input. The bias supply drives
the gate of the internal N-MOSFET pass transistor, making
these devices ideal for applications that require low voltage
outputs from low voltage inputs. The RT9041E provides
fixed output voltage from 1V to 2V with 0.1V increments.
Adjustable output voltage is available for the RT9041E by
using external resistors. Other features include current
limit and thermal shutdown to protect regulator from fault
conditions.
The RT9041E is available in a WDFN-8L 2x2 package.
Features
±2% Output Voltage Accuracy
No Minimum Load Current Required
1V to 5.5V Input Supply Voltage
3V to 5.5V Input Bias Supply Voltage
PGOOD Open-Drain Output
Supports Fixed/Adjustable Output Voltage
Low Supply Current
5μ
μA (max) Shutdown Supply Current
RoHS Compliant and Halogen Free
Applications
Set Top Box
RT9041EPackage Type
QW : WDFN-8L 2x2
Lead Plating System
G : Green (Halogen Free and Pb Free)
Output Voltage
10 : 1.0V/Adj
11 : 1.1V/Adj
:
19 : 1.9V/Adj
20 : 2.0V/Adj
Note :
Richtek products are :
`
RoHS compliant and compatible with the current require-
Notebook Computers
VID Power Supplies
PDAs
Cell Phones
Low Dropout Regulators with External Bias Supply
Pin Configurations
(TOP VIEW)
VOUT
ADJ
PGOOD
GND
1
2
3
4
GND
Ordering Information
9
8
7
6
5
VIN
NC
VDD
EN
WDFN-8L 2x2
ments of IPC/JEDEC J-STD-020.
`
Suitable for use in SnPb or Pb-free soldering processes.
Marking Information
For marking information, contact our sales representative
directly or through a Richtek distributor located in your
area.
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS9041E-02 January 2013
is a registered trademark of Richtek Technology Corporation.
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RT9041E
Typical Application Circuit
RT9041E
VIN
1V to 5.5V
8
CIN
10µF
VOUT 1
VIN
R1
ADJ
VDD
3.3V to 5.5V
2
VOUT
R2
6 VDD
CVDD
0.1µF
COUT
10µF
PGOOD 3
Chip Enable 5
EN
GND
4, Exposed pad (9)
R3
100k
Function Pin Description
Pin No.
Pin Name
Pin Function
1
VOUT
Output Voltage.
2
ADJ
Output Voltage Adjust Pin. Set the output voltage by the internal feedback
resistors when ADJ is ground. If external feedback resistors is used,
VOUT = VREF x (R1 + R2)/R2.
3
PGOOD
Power Good Open Drain Output.
4, 9 (Exposed pad) GND
Ground. The exposed pad must be soldered to a large PCB and connected to
GND for maximum power dissipation.
5
EN
Chip Enable (Active-High).
6
VDD
Supply Voltage of Control Circuitry.
7
NC
No Internal Connection.
8
VIN
Supply Input Voltage.
Function Block Diagram
VIN
VOUT
Driver
OTP
+
VIN
EN
VDD
UVLO
-
OCP
Error
Amplifier
Mode
0.8V
ADJ
PGOOD
-
0.7V
+
GND
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DS9041E-02 January 2013
RT9041E
Absolute Maximum Ratings
(Note 1)
Bias Supply Input Voltage, VDD --------------------------------------------------------------------------------------Supply Input Voltage, VIN ----------------------------------------------------------------------------------------------Other Input/Output Pins ------------------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C
WDFN-8L 2x2 -------------------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2)
WDFN-8L 2x2, θJA -------------------------------------------------------------------------------------------------------WDFN-8L 2x2, θJC ------------------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------Junction Temperature ----------------------------------------------------------------------------------------------------Storage Temperature Range -------------------------------------------------------------------------------------------ESD Susceptibility (Note 3)
HBM (Human Body Model) ----------------------------------------------------------------------------------------------
Recommended Operating Conditions
6V
6V
6V
0.833VW
120°C/W
8.2°C/W
260°C
150°C
−65°C to 150°C
2kV
(Note 4)
Bias Supply Input Voltage, VDD --------------------------------------------------------------------------------------- 3V to 5.5V
Supply Input Voltage, VIN ----------------------------------------------------------------------------------------------- 1V to 5.5V
Junction Temperature Range -------------------------------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range -------------------------------------------------------------------------------------------- −40°C to 85°C
Electrical Characteristics
(VIN = 1.8V, ILOAD = 1mA, COUT = 10μF, TA = 25°C unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Adjustable Output Voltage Range VOUT
0.8
--
2.5
V
Bias Input Under Voltage Lockout VUVLO
--
2.7
--
V
Input
VIN Shutdown Current
I SHDN
1V < VIN < 5.5V, VIN = VOUT + 0.6V
--
1
5
μA
Quiescent Current
IQ
3V < VDD < 5.5V
--
160
250
μA
VDD Shutdown Current
I SHDN
3V < VDD < 5.5V
--
1
5
μA
−0.15
--
0.15
%/V
--
0.2
1
%
−2
--
2
%
0.784
0.8
0.816
V
IOUT = 300mA, VDD − VOUT ≥ 2.1V
--
200
300
IOUT = 500mA, VDD − VOUT ≥ 2.1V
--
300
500
550
700
1400
mA
--
160
--
°C
--
20
--
°C
Regulator Characteristics
Line Regulation
Load Regulation
= 10mA, 1.5V < VIN < 5.5V,
I
ΔVOUT / ΔVIN OUT
VIN = VOUT + 0.6V
VIN = VOUT + 0.6V,
ΔVOUT / ΔI IN
ILOAD = 1mA to 300mA
Fixed Output Voltage Accuracy
ΔVOUT
Short ADJ to GND, IOUT = 10mA
Reference Voltage
VREF
IOUT = 10mA
Dropout Voltage
VDROP
Current Limit
I LIM
RLOAD = 0
Thermal-Shutdown
TSD
3V < VDD < 5.5V
Thermal-Shutdown Hysteresis
ΔTSD
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS9041E-02 January 2013
mV
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3
RT9041E
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
--
0.2
--
V
% of regulated output voltage
--
88
--
%
(Note 5)
--
10
--
mV
ADJ
ADJ Pin Threshold
PGOOD Comparator
Comparator Threshold
Comparator Hysteresis
VHYST
Logic and I/O
EN Input Voltage
Logic-High
VIH
2.4
--
--
Logic-Low
VIL
--
--
0.8
VEN = 5V
--
12
--
μA
PGOOD sinking 1mA
--
--
0.1
V
0 < VPGOOD < VIN
−1
--
1
μA
Rising edge within 5% of regulation
level
1
--
5
ms
EN Current
IEN
PGOOD Output Low Voltage
PGOOD Output High Leakage
Current
Dynamics
PGOOD Propagation Delay
tPGOOD
V
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Guaranteed by Design.
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RT9041E
Typical Operating Characteristics
Reference Voltage vs. Temperature
0.84
2.15
0.83
Reference Voltage (V)
Output Voltage (V)
Output Voltage vs. Temperature
2.20
2.10
2.05
2.00
1.95
1.90
0.82
0.81
0.80
0.79
0.78
0.77
1.85
VDD = 5V, VIN = 3.3V, VOUT = 2V, IOUT = 0mA
1.80
-50
-25
0
25
50
75
100
VDD = 5V, VIN = 3.3V, VADJ = 0.8V, IOUT = 0mA
0.76
-50
125
-25
0
50
75
100
125
Current Limit vs. Temperature
210
0.90
200
0.85
190
0.80
Current Limit (A)
Quiescent Current (μA)1
Quiescent Current vs. Temperature
180
170
160
150
140
0.75
0.70
0.65
0.60
0.55
VDD = 5V, VIN = 3.3V, VOUT = 2V, IOUT = 0mA
130
VDD = 5V, VIN = 3.3V, VOUT = 2V, IOUT = 0mA
0.50
-50
-25
0
25
50
75
100
125
-50
-25
0
Temperature (°C)
25
50
75
100
125
Temperature (°C)
Dropout Voltage vs. Output Current
EN Threshold Voltage vs. Temperature
1.6
600
1.5
125°C
400
25°C
300
−40°C
200
100
Threshold Voltage (V)
500
Dropout Voltage (mV)
25
Temperature (°C)
Temperature (°C)
Rising
1.4
1.3
Falling
1.2
1.1
1.0
0.9
VDD = 5V
0
0
100
200
300
400
Output Current (mA)
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DS9041E-02 January 2013
500
VDD = 5V, VOUT = 1V
0.8
-50
-25
0
25
50
75
100
125
Temperature (°C)
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RT9041E
VIN UVLO vs. Temperature
VDD UVLO vs. Temperature
1.0
3.0
0.9
0.8
Rising
2.6
2.4
UVLO (V)
UVLO (V)
2.8
Falling
2.2
0.7
0.6
Falling
0.5
VDD = 5V, VOUT = 1V
2.0
-50
-25
0
25
50
75
100
VDD = 5V, VOUT = 1V
0.4
-50
125
-25
0
25
50
75
Temperature (°C)
Temperature (°C)
PGOOD Timing vs. Temperature
PGOOD Response
5
PGOOD Timing (ms)
Rising
100
125
Rising
VEN
(5V/Div)
4
3
VOUT
(1V/Div)
2
1
VDD = 5V, VIN = 3.3V, VOUT = 1V
0
-50
-25
0
25
50
75
100
PGOOD
(1V/Div)
VDD = 5V, VIN = 4V, IOUT = 40mA
Time (2.5ms/Div)
125
Temperature (°C)
Line Transient Response
Load Transient Response
VDD = 5V, VIN = 3.3V, VOUT = 2V
IOUT = 10mA to 0.5A
4
VIN
(V) 3
IOUT
(500mA/Div)
VOUT
(50mV/Div)
VOUT
(5mV/Div)
VDD = 5V, VIN = 3V to 4V, VOUT = 1V, IOUT = 10mA
Time (100μs/Div)
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Time (500μs/Div)
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DS9041E-02 January 2013
RT9041E
Line Transient Response
EN Response
VDD = 5V, VIN = 3.3V, VOUT = 1V, IOUT = 0.5A
4
VIN
(V) 3
VEN
(5V/Div)
VOUT
(5mV/Div)
VDD = 5V, VIN = 3V to 4V, VOUT = 1V, IOUT = 100mA
0
VOUT
(500mV/Div)
Time (500μs/Div)
Time (500μs/Div)
PSRR
Noise
VDD = 5V, VIN = 3.3V to 3.4V, CIN = 1μF, COUT = 10μF
VDD = VIN = 4.5V (By Battery),
VOUT = 1V, IOUT = 1mA
PSRR (dB)
-20
-40
VOUT
(200μV/Div)
IOUT = 10mA
IOUT = 100mA
-60
-80
-100
10
100
100
1000
1k
10000
10k
100000
100k
1000000
1M
Time (10ms/Div)
Frequency (Hz)
Noise
VDD = VIN = 4.5V (By Battery),
VOUT = 1V, IOUT = 10mA
VOUT
(200μV/Div)
Time (10ms/Div)
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS9041E-02 January 2013
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
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RT9041E
Application Information
The RT9041E is a low voltage, low dropout linear regulator
with an external bias supply input, capable of supporting
an input voltage range from 1V to 5.5V with a fixed output
voltage from 1V to 2V in 0.1V increments.
Supply Voltage Setting
The bias supply voltage (VDD) operates from 3V to 5.5V.
For better efficiency, it is suggested to operate VDD at 5V
when the output voltage is higher than 1V. Figure 1 shows
the curves of the recommended VDD − VOUT range vs. the
dropout voltage (VIN − VOUT) values.
Dropout Voltage vs. VDD - VOUT
Dropout Voltage (mV)
400
350
IO = 500mA
250
200
150
IO = 300mA
50
0
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
Current Limit
The RT9041E contains an independent current limit
circuitry, which monitors and controls the pass transistor’s
gate voltage, limiting the output current to 0.7A (typ.).
Like any low dropout regulator, the external capacitors of
the RT9041E must be carefully selected for regulator
stability and performance. Using a capacitor of at least
10μF is suitable. The input capacitor must be located at a
distance of not more than 0.5 inch from the input pin of
the IC. Any good quality ceramic capacitor can be used.
However, a capacitor with larger value and lower ESR
(Equivalent Series Resistance) is recommended since it
will provide better PSRR and line transient response.
450
100
The RT9041E goes into sleep mode when the EN pin is in
a logic low condition. In this condition, the pass transistor,
error amplifier, and band gap are all turned off, reducing
the supply current to 1μA (typ.). The EN pin can be directly
tied to VIN to keep the part on.
CIN and COUT Selection
500
300
Chip Enable Operation
3.6
3.8
4.0
VDD - VOUT (V)
Figure 1. Dropout Voltage vs.VDD − VOUT
Output Voltage Setting
The RT9041E output voltage is also adjustable from 0.8V
to 2.5V via the external resistive voltage divider. The voltage
divider resistors can have values up to 800kΩ because of
the very high impedance and low bias current of the sense
comparator. The output voltage is set according to the
following equation :
VOUT = VREF x ⎛⎜ 1 + R1 ⎞⎟
⎝
R2 ⎠
The RT9041E is designed specifically to work with low
ESR ceramic output capacitor for space saving and
performance consideration. Using a ceramic capacitor with
value at least 10μF and ESR larger than 40mΩ on the
RT9041E output ensures stability. Nevertheless, the
RT9041E can still work well with other types of output
capacitors due to its wide range of stable ESR. Figure 2
shows the allowable ESR range as a function of load
current for various output capacitance. Output capacitors
with larger capacitance can reduce noise and improve load
transient response, stability, and PSRR. The output
capacitor should be located at a distance of not more than
0.5 inch from the output pin of the RT9041E.
where VREF is the reference voltage with a typical value of
0.8V.
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DS9041E-02 January 2013
RT9041E
The maximum power dissipation depends on the operating
ambient temperature for fixed T J(MAX) and thermal
Region of Stable COUT ESR vs. Load Current
resistance, θJA. The derating curve in Figure 3 allows the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
Unstable Range
10.00
0.9
Stable Range
1.00
VDD = 5, VIN = 2.5V, VOUT = 1V,
0.10
CVDD = 0.1μF, CIN = COUT = 10μF/X7R
Simulation Verify
0.01
0
100
200
300
400
500
Load Current (mA)
Figure 2. Region of Stable COUT ESR vs. the Load
Current
Maximum Power Dissipation (W)1
Region of Stable COUT ESR (Ω)
100.00
Four-Layer PCB
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Thermal Considerations
Figure 3. Derating Curve of Maximum Power Dissipation
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
WDFN-8L 2x2 packages, the thermal resistance, θJA, is
120°C/W on a standard JEDEC 51-7 four-layer thermal
test board. The maximum power dissipation at TA = 25°C
can be calculated by the following formula :
PD(MAX) = (125°C − 25°C) / (120°C/W) = 0.833W for
WDFN-8L 2x2 package
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS9041E-02 January 2013
is a registered trademark of Richtek Technology Corporation.
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9
RT9041E
Outline Dimension
D2
D
L
E
E2
1
e
SEE DETAIL A
b
2
1
2
1
A
A1
A3
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.200
0.300
0.008
0.012
D
1.950
2.050
0.077
0.081
D2
1.000
1.250
0.039
0.049
E
1.950
2.050
0.077
0.081
E2
0.400
0.650
0.016
0.026
e
L
0.500
0.300
0.020
0.400
0.012
0.016
W-Type 8L DFN 2x2 Package
Richtek Technology Corporation
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
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DS9041E-02 January 2013