HD74LV2GT08A Dual 2-input AND Gates / CMOS Logic Level Shifter REJ03D0140–0200Z (Previous ADE-205-665A (Z)) Rev.2.00 Oct.16.2003 Description The HD74LV2GT08A has dual two-inputs AND gates in a 8 pin package. The input protection circuitry on this device allows over voltage tolerance on the input, allowing the device to be used as a logic–level translator from 3.0 V CMOS Logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic while operating at the high-voltage power supply. Low voltage and high-speed operation is suitable for the battery powered products (e.g., notebook computers), and the low power consumption extends the battery life. Features • The basic gate function is lined up as Renesas uni logic series. • Supplied on emboss taping for high-speed automatic mounting. • TTL compatible input level. Supply voltage range : 3.0 to 5.5 V Operating temperature range : –40 to +85°C • Logic-level translate function 3.0 V CMOS logic → 5.0 V CMOS logic (@VCC = 5.0 V) 1.8 V or 2.5 V CMOS logic → 3.3 V CMOS logic (@VCC = 3.3 V) • All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO (Max.) = 5.5 V (@VCC = 0 V) • Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V) • All the logical input has hysteresis voltage for the slow transition. • Ordering Information Part Name Package Type HD74LV2GT08AUSE SSOP-8 pin Rev.2.00, Oct.16.2003, page 1 of 8 Package Code Package Abbreviation Taping Abbreviation (Quantity) TTP-8DBV US E (3,000 pcs/reel) HD74LV2GT08A Outline and Article Indication • HD74LV2GT08A Index band Lot No. Y M W T 0 8 SSOP-8 Marking Function Table Inputs A B Output Y L L L H L L L H L H H H H : High level L : Low level Rev.2.00, Oct.16.2003, page 2 of 8 Y : Year code (the last digit of year) M : Month code W : Week code HD74LV2GT08A Pin Arrangement 1A 1 8 VCC 1B 2 7 1Y 2Y 3 6 2B GND 4 5 2A (Top view) Absolute Maximum Ratings Item Symbol Ratings Unit Supply voltage range VCC –0.5 to 7.0 V Input voltage range *1 VI –0.5 to 7.0 V VO –0.5 to VCC +0.5 V Output voltage range *1, 2 –0.5 to 7.0 Test Conditions Output : H or L VCC : OFF Input clamp current IIK –20 mA VI < 0 Output clamp current IOK ±50 mA VO < 0 or VO > VCC Continuous output current IO ±25 mA VO = 0 to VCC Continuous current through VCC or GND ICC or IGND ±50 mA Maximum power dissipation *3 at Ta = 25°C (in still air) PT 200 mW Storage temperature Tstg –65 to 150 °C Notes: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore no two of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The maximum package power dissipation was calculated using a junction temperature of 150°C. Rev.2.00, Oct.16.2003, page 3 of 8 HD74LV2GT08A Recommended Operating Conditions Item Symbol Ratings Unit Supply voltage VCC 3.0 to 5.5 V Input voltage VIN 0 to 5.5 V Output voltage VOUT 0 to VCC V Operating temperature Topr –40 to +85 °C Input rise / fall time tr, tf 0 to 100 (VCC = 3.0 to 3.6 V) ns 0 to 20 (VCC = 4.5 to 5.5 V) Electrical Characteristic • Ta = –40 to 85°C Item Symbol VCC (V) * Input voltage VIH VIL Hysteresis voltage Output voltage VH VOH VOL Min Typ Max Unit Test condition 3.0 to 3.6 1.5 — — V 4.5 to 5.5 2.0 — — 3.0 to 3.6 — — 0.6 4.5 to 5.5 — — 0.8 3.3 — 0.10 — 5.0 — 0.15 — Min to Max VCC–0.1 — — 3.0 2.48 — — IOH = –6 mA 4.5 3.8 — — IOH = –12 mA Min to Max — — 0.1 IOL = 50 µA 3.0 — — 0.44 IOL = 6 mA 4.5 — — 0.55 IOL = 12 mA V VT+ – VT– V IOH = –50 µA Input current IIN 0 to 5.5 — — ±1 µA VIN = 5.5 V or GND Quiescent supply current ICC 5.5 — — 10 µA VIN = VCC or GND, IO = 0 ∆ICC 5.5 — — 1.5 mA One input VIN = 3.4 V, other input VCC or GND Output leakage current IOFF 0 — — 5 µA VO = 5.5 V Input capacitance 5.0 — 2.5 — pF VIN = VCC or GND CIN Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions. Rev.2.00, Oct.16.2003, page 4 of 8 HD74LV2GT08A Switching Characteristics • VCC = 3.3 ± 0.3 V Ta = 25°C Test Ta = –40 to 85°C FROM Item Symbol Min Typ Max Min Max Unit Conditions (Input) Propagation delay time tPLH tPHL — 6.5 10.5 1.0 12.0 ns — 7.5 12.5 1.0 14.0 CL = 15 pF TO (Output) A or B Y FROM TO CL = 50 pF • VCC = 5.0 ±0.5 V Ta = 25°C Test Ta = –40 to 85°C Item Symbol Min Typ Max Min Max Unit Conditions (Input) Propagation delay time tPLH tPHL — 5.0 6.9 1.0 8.0 ns — 5.5 7.9 1.0 9.0 CL = 15 pF A or B (Output) Y CL = 50 pF Operating Characteristics • CL = 50 pF Ta = 25°C Item Symbol VCC (V) Min Typ Max Unit Test Conditions Power dissipation capacitance CPD 5.0 10.0 — pF f = 10 MHz Rev.2.00, Oct.16.2003, page 5 of 8 — HD74LV2GT08A Test Circuit VCC Pulse generator Output Input 50 Ω Note: Operating current test time, output is open. Rev.2.00, Oct.16.2003, page 6 of 8 CL HD74LV2GT08A • Waveforms tr tf 90% Input VI 90% Vref Vref 10% 10% GND VOH 50% Output 50% VOL t PLH t PHL INPUTS VCC (V) VI Vref tr / tf 3.3±0.3 2.5 V ≤ 3.0 ns 50% ≤ 3.0 ns 1.5 V 5.0±0.5 3V Notes: 1. Input waveform : PRR ≤ 1 MHz, Zo = 50 Ω. 2. The output are measured one at a time with one transition per measurement. Rev.2.00, Oct.16.2003, page 7 of 8 HD74LV2GT08A Package Dimensions 2.0 ± 0.2 1.5 ± 0.2 + 0.1 (0.17) 8 − 0.2 − 0.05 *Sn-Bi plating Rev.2.00, Oct.16.2003, page 8 of 8 + 0.1 0.13 − 0.05 0 − 0.1 0.7 ± 0.1 (0.4) 2.3 ± 0.1 (0.5) (0.5) (0.5) 3.1 ± 0.3 (0.4) Unit: mm Hitachi Code JEDEC JEITA Mass (reference value) TTP-8DBV 0.010 g Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. 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