RENESAS RD74VT1G240

RD74VT1G240
Bus Buffer Inverted with 3-state Output /
Dual Supply Voltage Translator
REJ03D0518–0100
Rev.1.00
Jun. 01, 2005
Description
The RD74VT1G240 has a bus buffer inverted with 3-state output in a 6 pin package. Output is disabled when the
associated output enable (OE) input is high. To ensure the high impedance state during power up or power down, OE
should be connected to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current
sinking capability of the driver. The input is designed to track VCCIN, which accepts voltages from 1.2V to 3.6V, and
the output is designed to track VCCOUT, which operates at 1.2V to 3.6V. Low voltage and high-speed operation is
suitable for the battery powered products (e.g., notebook computers), and the low power consumption extends the
battery life.
Features
• This product function as level shift that change VCCIN input level to VCCOUT output level by providing different
supply voltage to VCCIN and VCCOUT.
• The basic gate function is lined up as Renesas uni logic series.
• Supplied on emboss taping for high-speed automatic mounting.
• Supply voltage range: VCCIN = 1.2 V to 3.6 V
VCCOUT = 1.2 V to 3.6 V
Operating temperature range: −40
40 to +85°C
• All inputs VIH (Max.) = 3.6 V (@VCCIN = 0 V to 3.6 V)
Outputs VO (Max.) = 3.6 V (@VCCOUT = 0 V)
• Output current
±2 mA (@VCCOUT = 1.2 V)
±44 mA (@VCCOUT = 1.4 V to 1.6 V)
±66 mA (@VCCOUT = 1.65 V to 1.95 V)
±18
18 mA (@VCCOUT = 2.3 V to 2.7 V)
±24
24 mA (@VCCOUT = 3.0 V to 3.6 V)
• Ordering Information
Part Name
RD74VT1G240CLE
Package Type
Package Code
(Previous Code)
Package
Abbreviation
WCSP-6 pin
SXBG0006KB–A
(TBS-6AV)
CL
Article Indication
Marking
Year code
Month code
VHYM
Rev.1.00 Jun. 01, 2005 page 1 of 9
Taping Abbreviation
(Quantity)
E (3,000 pcs/reel)
RD74VT1G240
Function Table
Inputs
A
Output Y
L
L
H
L
H
L
H
X
Z
OE
H: High level
L: Low level
X: Immaterial
Z: High impedance
Pin Arrangement
Height 0.5 mm
0.5 mm pitch
0.23 mm 6–Ball (CL)
GND
3
4
Y
A
2
5
VCCOUT
OE
1
6
1.4 mm
0.9 mm
VCCIN
(Bottom view)
(Top view)
Logic Diagram
OE
A
Rev.1.00 Jun. 01, 2005 page 2 of 9
Pin#1 INDEX
Y
RD74VT1G240
Absolute Maximum Ratings
Item
Supply voltage range
Symbol
Ratings
Unit
VCCIN, VCCOUT
–0.5 to 4.6
V
VI
–0.5 to 4.6
V
A port or OE
VO
–0.5 to VCCOUT+0.5
V
Output: “H” or “L”
Input voltage range *1
Output voltage range
*1, 2
–0.5 to 4.6
Conditions
Output: “Z” or
VCCOUT: OFF
Input clamp current
IIK
–50
mA
VI < 0
Output clamp current
IOK
–50
mA
VO < 0
50
VO > VCC+0.5
Continuous output current
IO
±50
mA
Continuous output current
VCC or GND
ICCIN, ICCOUT, IGND
±100
mA
θja
123
°C/W
Tstg
–65 to 150
°C
Package Thermal impedance
Storage temperature
Notes:
The absolute maximum ratings are values, which must
st not individually be exceeded, and furthermore, no two
of which may be realized at the same time.
1. The input and output voltage ratings
ngs may be exceeded if the input and output clamp-current ratings are
observed.
2. This value is limited to 4.6 V maximum.
Recommended Operating Conditions
Item
Supply voltage range
Input/Output voltage
Symbol
Ratings
Unit
VCCIN
1.2 to 3.6
V
VCCOUT
1.2 to 3.6
VI
0 to 3.6
V
A port or OE
VO
0 to VCCOUT
V
Output: “H” or “L”
0 to 3.6
Output current
IOH
–2
Output: “Z” or VCCOUT: OFF
mA
VCCOUT = 1.5±0.1 V
–6
VCCOUT = 1.8±0.15 V
–18
VCCOUT = 2.5±0.2 V
2
VCCOUT = 3.3±0.3 V
mA
VCCOUT = 1.2 V
4
VCCOUT = 1.5±0.1 V
6
VCCOUT = 1.8±0.15 V
18
VCCOUT = 2.5±0.2 V
VCCOUT = 3.3±0.3 V
24
Input transition rise or fall time
∆t / ∆v
10
ns / V
Operation free-air temperature
Ta
–40 to 85
°C
Rev.1.00 Jun. 01, 2005 page 3 of 9
VCCOUT = 1.2 V
–4
–24
IOL
Conditions
RD74VT1G240
Electrical Characteristics
(Ta = −40 to 85°C)
Symbol VCCIN (V) *
VIH
1.2
1.5±0.1
1.8±0.15
2.5±0.2
3.3±0.3
1.2
VIL
1.5±0.1
1.8±0.15
2.5±0.2
3.3±0.3
Output voltage
VOH
1.2 to 3.6
Item
Input voltage
VCCOUT (V) *
Min
1.2 to 3.6
VCCIN×0.75
VCCIN×0.70
VCCIN×0.65
1.6
2.0
1.2 to 3.6





1.2 to 3.6 VCCOUT−0.2
1.2
0.9
1.5±0.1
1.1
1.8±0.15
1.25
2.5±0.2
1.7
3.3±0.3
2.2
1.2 to 3.6

1.2

1.5±0.1

1.8±0.15

2.5±0.2

3.3±0.3

3.6
–1.0
Typ























Max





VCCIN×0.25
VCCIN×0.30
VCCIN×0.35
0.7
0.8






0.2
0.3
0.3
0.3
0.6
0.55
1.0
Unit
Test conditions
V A port
Control input
V
A port
Control input
V
IOH = –100 µA
IOH = –2 mA
IOH = –4 mA
IOH = –6 mA
IOH = –18 mA
IOH = –24 mA
IOL = 100 µA
IOL = 2 mA
IOL = 4 mA
IOL = 6 mA
IOL = 18 mA
IOL = 24 mA
VIN = GND or VCCIN
control input
VIN = VIH or VIL
VOL
1.2 to 3.6
Input current
IIN
3.6
Off state output
current
Output leakage
current
Quiescent
supply current
IOZ
3.6
3.6
–1.5

1.5
µA
IOFF
0
0


1.5
µA
ICCIN
1.2 to 3.6
1.2 to 3.6
–3.0

3.0
µA
ICCOUT
1.2 to 3.6
1.2 to 3.6
–3.0

3.0
∆ICC
3.6
3.6


250
µA
CIN
3.3
3.3

3.5

pF
Increase in ICC
per input
Input
capacitance
V
µA
VIN, VOUT =
0 to 3.6 V
IO(Y port) = 0
VIN = VCCIN or GND
IO(Y port) = 0
VIN = VCCIN or GND
A port or control
VCCIN–0.6 (1 input)
VIN = VCC or GND
Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions.
Switching Characteristics
VCCIN = 3.3±0.3 V
Ta = –40 to 85°C
From
Item
To
Symbol (input) (output)
Propagation
tPLH
delay time
tPHL
Output
tZH
enable time
tZL
Output
tHZ
disable time
tLZ
A
OE
OE
Y
Y
Y
Rev.1.00 Jun. 01, 2005 page 4 of 9
VCCOUT=
VCCOUT=
VCCOUT=
VCCOUT=
VCCOUT=
1.2 V
1.5±0.1 V
1.8±0.15 V
2.5±0.2 V
3.3±0.3 V
Test
Typ
Min
Max
Min
Max
Min
Max
Min
Max
Unit conditions
9.6
2.0
9.4
1.0
6.0
1.0
4.0
1.0
3.4
ns CL = 15pF
9.6
2.0
9.4
1.0
6.0
1.0
4.0
1.0
3.4
11.2
2.0
10.6
1.5
6.8
1.0
4.2
1.0
3.8
11.2
2.0
10.6
1.5
6.8
1.0
4.2
1.0
3.8
5.0
2.0
5.4
1.5
4.7
1.0
4.0
1.0
3.8
5.0
2.0
5.4
1.5
4.7
1.0
4.0
1.0
3.8
RL = 2.0kΩ
ns CL = 15pF
RL = 2.0kΩ
ns CL = 15pF
RL = 2.0kΩ
RD74VT1G240
Switching Characteristics (Cont)
VCCIN = 2.5±0.2 V
Ta = –40 to 85°C
VCCOUT=
From
Item
To
Symbol (input) (output)
Propagation
tPLH
delay time
tPHL
Output
tZH
enable time
tZL
Output
tHZ
disable time
tLZ
A
OE
OE
Y
Y
Y
1.2 V
VCCOUT=
1.5±0.1 V
VCCOUT=
VCCOUT=
1.8±0.15 V
2.5±0.2 V
VCCOUT=
3.3±0.3 V
Test
Typ
Min
Max
Min
Max
Min
Max
Min
Max
Unit conditions
10.0
2.0
9.4
1.5
6.0
1.0
4.0
1.0
3.5
ns CL = 15pF
10.0
2.0
9.4
1.5
6.0
1.0
4.0
1.0
3.5
11.6
2.0
11.4
1.5
7.2
1.0
4.8
1.0
3.8
11.6
2.0
11.4
1.5
7.2
1.0
4.8
1.0
3.8
5.2
2.0
5.0
1.5
4.7
1.0
4.0
1.0
4.0
5.2
2.0
5.0
1.5
4.7
1.0
4.0
1.0
4.0
RL = 2.0kΩ
ns CL = 15pF
RL = 2.0kΩ
ns CL = 15pF
RL = 2.0kΩ
VCCIN = 1.8±0.15 V
Ta = –40 to 85°C
VCCOUT=
From
Item
To
Symbol (input) (output)
Propagation
tPLH
delay time
tPHL
Output
tZH
enable time
tZL
Output
tHZ
disable time
tLZ
A
OE
OE
Y
Y
Y
1.2 V
VCCOUT=
1.5±0.1 V
VCCOUT=
VCCOUT=
1.8±0.15 V
2.5±0.2 V
VCCOUT=
3.3±0.3 V
Test
Typ
Min
Max
Min
Max
Min
Max
Min
Max
Unit conditions
10.2
2.0
9.8
1.5
6.5
1.0
4.4
1.0
4.1
ns CL = 15pF
10.2
2.0
9.8
1.5
6.5
1.0
4.4
1.0
4.1
11.6
2.0
11.8
1.5
7.6
1.0
5.2
1.0
4.4
11.6
2.0
11.8
1.5
7.6
1.0
5.2
1.0
4.4
5.8
2.0
5.6
1.5
5.4
1.0
4.8
1.0
5.0
5.8
2.0
5.6
1.5
5.4
1.0
4.8
1.0
5.0
RL = 2.0kΩ
ns CL = 15pF
RL = 2.0kΩ
ns CL = 15pF
RL = 2.0kΩ
VCCIN = 1.5±0.1 V
Ta = –40 to 85°C
VCCOUT=
From
Item
To
Symbol (input) (output)
Propagation
tPLH
delay time
tPHL
Output
tZH
enable time
tZL
Output
tHZ
disable time
tLZ
A
OE
OE
Y
Y
Y
1.2 V
VCCOUT=
1.5±0.1 V
VCCOUT=
VCCOUT=
1.8±0.15 V
2.5±0.2 V
VCCOUT=
3.3±0.3 V
Test
Typ
Min
Max
Min
Max
Min
Max
Min
Max
Unit conditions
11.4
2.0
10.5
1.5
7.2
1.0
4.8
1.0
4.7
ns CL = 15pF
11.4
2.0
10.5
1.5
7.2
1.0
4.8
1.0
4.7
12.2
2.0
12.6
1.5
8.6
1.0
5.4
1.0
4.8
12.2
2.0
12.6
1.5
8.6
1.0
5.4
1.0
4.8
6.2
2.0
7.0
1.5
6.0
1.0
5.4
1.0
5.2
6.2
2.0
7.0
1.5
6.0
1.0
5.4
1.0
5.2
RL = 2.0kΩ
ns CL = 15pF
RL = 2.0kΩ
ns CL = 15pF
RL = 2.0kΩ
VCCIN = 1.2 V
Ta = –40 to 85°C
From
Item
To
Symbol (input) (output)
Propagation
tPLH
delay time
tPHL
Output
tZH
enable time
tZL
Output
tHZ
disable time
tLZ
A
OE
OE
Y
Y
Y
Rev.1.00 Jun. 01, 2005 page 5 of 9
VCCOUT=
VCCOUT=
VCCOUT=
VCCOUT=
VCCOUT=
1.2 V
1.5±0.1 V
1.8±0.15 V
2.5±0.2 V
3.3±0.3 V
Typ
Typ
Typ
Typ
Typ
Unit conditions
ns CL = 15pF
11.0
7.5
6.0
4.5
4.0
11.0
7.5
6.0
4.5
4.0
12.8
9.5
7.2
5.2
4.5
12.8
9.5
7.2
5.2
4.5
7.0
6.0
5.7
5.5
5.5
7.0
6.0
5.7
5.5
5.5
Test
RL = 2.0kΩ
ns CL = 15pF
RL = 2.0kΩ
ns CL = 15pF
RL = 2.0kΩ
RD74VT1G240
Operating Characteristics
Ta = 25°C
Item
Symbol
VCCIN (V)
VCCOUT (V)
Min
Typ
Max
Unit
CPD
3.3
3.3

12

pF
Power dissipation
capacitance
Test conditions
f = 10 MHz
CL = 0
Power-up Considerations
Level-translation devices offer an opportunity for successful mixed-voltage signal design.
A proper power-up sequence always should be followed to avoid excessive supply current, bus contention, oscillations,
or other anomalies caused by improperly biased device pins.
Take these precautions to guard against such power-up problems.
1. Connect ground before any supply voltage is applied.
2. Next, power up the control side of the device.
(Power up of VCCIN is first. Next power up is VCCOUT)
3. Tie OE to VCCIN with a pull-up resistor so that it ramps with VCCIN.
Test Circuit
Input
Pulse Generator
Z OUT = 50 Ω
VCCOUT
See Function Table
VCCIN
Output
RL=2.0kΩ
CL=15pF
Symbol
S1
t PLH / tPHL
OPEN
t HZ / t ZH
GND
t LZ / t ZL
2 × VCC
RL=2.0kΩ
Note: CL includes probe and jig capacitance.
Rev.1.00 Jun. 01, 2005 page 6 of 9
S1
OPEN
*1 see under table
GND
RD74VT1G240
Waveforms–1
tr
tf
Input A
VIH
90%
90%
V ref
V ref
10%
10%
t PHL
GND
t PLH
VOH
V ref
Output Y
V ref
VOL
Symbol
V CC = 1.2 V to 3.6 V
tr / t f
2.0 ns
V IH
VCC
V ref
1/2 VCC
Note: 1. Input waveform : PRR ≤ 10 MHz, Zo = 50 Ω, duty cycle 50%.
Rev.1.00 Jun. 01, 2005 page 7 of 9
RD74VT1G240
Waveforms–2
Input OE
tr
tf
90%
90%
V ref
VIH
V ref
10%
10%
GND
t ZL
t LZ
VOH
V ref
Waveform–1
VL
t ZH
Output Y
VOL
t HZ
VOH
VH
V ref
Waveform–2
VOL
Symbol
V CC = 1.2 V,
1.5±0.1
0.1 V
V CC = 1.8
1.8±0.15 V V CC = 2.5
2.5±0.2 V
V CC = 3.3±0.3 V
tr / t f
2.0 ns
2.0 ns
2.0 ns
2.0 ns
V IH
VCC
VCC
VCC
VCC
V ref
1/2VCC
1/2VCC
1/2VCC
1/2VCC
VH / V L
VH = VOH-0.1 V
VL = VOL+0.1 V
VH = VOH-0.15 V VH = VOH-0.15 V VH = VOH-0.3 V
VL = VOL+0.15 V VL = VOL+0.15 V VL = VOL+0.3 V
Notes: 1. Input waveform : PRR ≤ 10 MHz, ZO = 50 Ω, duty cycle 50%
2. Waveform – 1 is for an output with internal conditions such that the output is low
except when disabled by the output control.
3. Waveform – 2 is for an output with internal conditions such that the output is high
except when disabled by the output control.
4. The output are measured one at a time with one transition per measurement.
Rev.1.00 Jun. 01, 2005 page 8 of 9
RD74VT1G240
Package Dimensions
JEITA Package Code
S-XFBGA6-0.9x1.4-0.50
RENESAS Code
SXBG0006KB-A
Previous Code
TBS-6AV
MASS[Typ.]
0.001g
e
ZD
D
ZE
C
E
B
e
B
A
1
Pin#1 index area
2
A
6 × φb
y1 C
φ× M C A B
φ× M C
Reference
Symbol
* Reference value.
Rev.1.00 Jun. 01, 2005 page 9 of 9
Max
0.50
A1
0.155
0.185
(0.315) *
A2
0.25
0.20
D
0.90
E
1.40
e
0.50
x
0.05
y
0.05
A
A1
y C
A2
Seating plane
Nom
A
b
C
Dimension in Millimeters
Min
0.20
y
1
Z
D
0.20
Z
E
0.20
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Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits,
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