RD74LVC16373B 16-bit D-type Transparent Latches with 3-state Outputs REJ03D0500–0100 Rev.1.00 Jan. 24, 2005 Description The RD74LVC16373B has sixteen D type latches with three state outputs in a 48 pin package. When the latch enable input is high, the Q outputs will follow the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control input (1G, 2G), all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. Low voltage and high-speed operation is suitable at the battery drive product (note type personal computer) and low power consumption extends the life of a battery for long time operation. Features • • • • • • VCC = 1.65 V to 5.5 V All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VOUT (Max.) = 5.5 V (@VCC = 0 V or output off state) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C) High output current ±4 mA (@VCC = 1.65 V) ±8 mA (@VCC = 2.3 V) ±12 mA (@VCC = 2.7 V) ±24 mA (@VCC = 3.0 V to 5.5 V) • Ordering Information Part Name RD74LVC16373BTEL Package Type TSSOP–48 pin Package Code (Previous Code) PTSP0048KA–A (TTP–48DBV) Package Abbreviation T Taping Abbreviation (Quantity) EL (1,000 pcs/reel) Function Table Inputs G LE D Output Q H X X Z L H L L L H H H L L X Q0 H: High level L: Low level X: Immaterial Z: High impedance Q0 : Level of Q before the indicated steady input conditions were established. Rev.1.00 Jan. 24, 2005 page 1 of 9 RD74LVC16373B Pin Arrangement 48 1LE 1G 1 1Q1 2 G Q D 47 1D1 1Q2 3 G Q D 46 1D2 GND 4 45 GND G Q D 44 1D3 G Q D 43 1D4 1Q5 8 G Q D 41 1D5 1Q6 9 G Q D 40 1D6 G Q D G Q D 37 1D8 2Q1 13 G Q D 36 2D1 2Q2 14 G Q D 35 2D2 1Q3 5 1Q4 6 VCC 7 GND 10 1Q7 11 1Q8 12 GND 15 2Q3 16 2Q4 17 VCC 18 2Q5 19 2Q6 20 G Q G Q G Q G Q 42 VCC 39 GND 34 GND D 33 2D3 D 32 2D4 31 VCC D 30 2D5 D 29 2D6 GND 21 2Q7 22 2Q8 23 28 GND G Q G Q D 27 2D7 D 26 2D8 2G 24 25 2LE (Top view) Rev.1.00 Jan. 24, 2005 page 2 of 9 38 1D7 RD74LVC16373B Absolute Maximum Ratings Item Symbol Ratings Unit VCC –0.5 to 7.0 V Supply voltage Input diode current IIK –50 mA Input voltage VI –0.5 to 7.0 V Output diode current IOK –50 mA Output voltage VO –0.5 to VCC+0.5 Output current IO ±50 mA ICC or IGND 100 mA Tstg –65 to +150 °C 50 Storage temperature VI = –0.5 V VO = –0.5 V VO = VCC+0.5 V V Output "H" or "L" Output "Z" or VCC: OFF –0.5 to 7.0 VCC, GND current / pin Conditions Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. Recommended Operating Conditions Item Supply voltage Symbol Ratings Unit VCC 1.5 to 5.5 V 1.65 to 5.5 Input/output voltage At operation V VI 0 to 5.5 VO 0 to VCC Operating temperature Ta –40 to 85 °C Output current IOH –4 mA *1 Input rise / fall time Output "Z" or VCC: OFF –8 VCC = 2.3 V VCC = 2.7 V –24 VCC = 3.0 V to 5.5 V mA VCC = 1.65 V 8 VCC = 2.3 V 12 VCC = 2.7 V 24 VCC = 3.0 V to 5.5 V 20 ns/V 10 Notes: 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics. Rev.1.00 Jan. 24, 2005 page 3 of 9 VCC = 1.65 V –12 4 tr, tf G, LE, D Output "H" or "L" 0 to 5.5 IOL Conditions Data hold VCC = 1.65 V to 2.7 V VCC = 3.0 V to 5.5 V RD74LVC16373B Electrical Characteristics Ta = –40 to 85°C Item Input voltage Unit VCC×0.65 — V 1.7 — 2.7 to 3.6 2.0 — VCC (V) Min VIH 1.65 to 1.95 2.3 to 2.7 VIL Output voltage Max Symbol VOH VOL Test Conditions 4.5 to 5.5 VCC×0.7 — 1.65 to 1.95 — VCC×0.35 2.3 to 2.7 — 0.7 2.7 to 3.6 — 0.8 4.5 to 5.5 — VCC×0.3 1.65 to 5.5 VCC–0.2 — 1.65 1.2 — IOH = –4 mA 2.3 1.7 — IOH = –8 mA 2.7 2.2 — IOH = –12 mA 3.0 2.4 — V IOH = –100 µA 3.0 2.2 — 4.5 3.8 — IOH = –24 mA 1.65 to 5.5 — 0.2 1.65 — 0.45 IOL = 4 mA 2.3 — 0.7 IOL = 8 mA 2.7 — 0.4 IOL = 12 mA 3.0 — 0.55 IOL = 24 mA 4.5 — 0.55 IOL = 100 µA IIN 0 to 5.5 — ±5.0 µA VIN = 5.5 V or GND Output leak current IOFF 0 — ±5.0 µA VIN / VOUT = 5.5 V Off state output current IOZ 2.7 to 5.5 — ±5.0 µA VIN = VCC or GND VOUT = 5.5 V or GND Quiescent supply current ICC 2.7 to 3.6 — ±10.0 µA VIN = 3.6 to 5.5 V 2.7 to 5.5 — 10.0 µA VIN = VCC or GND 2.7 to 3.6 — 500 µA VIN = one input at (VCC–0.6)V, other inputs at VCC or GND Input current ∆ICC Rev.1.00 Jan. 24, 2005 page 4 of 9 RD74LVC16373B Switching Characteristics Ta = –40 to 85°C Item Propagation delay time Output enable time Output disable time Setup time VCC (V) Min Typ Max Unit (Input) (Output) tPLH 1.8±0.15 1.0 — 19.1 ns D Q tPHL 2.5±0.2 1.0 — 9.6 2.7 1.0 — 7.7 3.3±0.3 1.5 — 7.0 5.0±0.5 1.0 — 5.5 tPLH 1.8±0.15 1.0 — 19.1 ns LE Q tPHL 2.5±0.2 1.0 — 9.6 2.7 1.0 — 7.7 3.3±0.3 1.5 — 7.0 5.0±0.5 1.0 — 5.5 tZH 1.8±0.15 1.0 — 20.0 ns G Q tZL 2.5±0.2 1.0 — 10.5 2.7 1.0 — 8.0 3.3±0.3 1.5 — 7.0 5.0±0.5 1.0 — 6.0 tHZ 1.8±0.15 1.0 — 20.0 ns G Q tLZ 2.5±0.2 1.0 — 10.5 2.7 1.0 — 8.0 3.3±0.3 1.5 — 7.0 5.0±0.5 1.0 — 6.0 1.8±0.15 6.0 — — th Pulse width tw Between output *1 pins skew 2.5±0.2 4.0 — — 2.7 2.0 — — 3.3±0.3 2.0 — — 5.0±0.5 2.0 — — 1.8±0.15 4.0 — — 2.5±0.2 2.0 — — 2.7 1.5 — — 3.3±0.3 1.5 — — 5.0±0.5 1.5 — — 1.8±0.15 9.0 — — 2.5±0.2 4.0 — — 2.7 3.3 — — 3.3±0.3 3.3 — — 5.0±0.5 3.3 — — tOSLH 1.8±0.15 — — — tOSHL 2.5±0.2 — — — 2.7 — — — 3.3±0.3 — — 1.0 5.0±0.5 — — 1.0 ns ns ns ns Input capacitance CIN 3.3 — 4.0 — pF Output capacitance CO 3.3 — 8.0 — pF Note: To Symbol tsu Hold time From 1. This parameter is characterized but not tested. tosLH = | tPLHm - tPLHn|, tosHL = | tPHLm - tPHLn| Rev.1.00 Jan. 24, 2005 page 5 of 9 RD74LVC16373B Operating Characteristics Ta = 25°C Item Symbol VCC (V) Min Typ Max Unit CPD 1.8 27 pF 2.5 28 3.3 30 5.0 35 Power dissipation capacitance Test Conditions f = 10 MHz Test Circuit VCC VCC Output 1G, 2G Input Zout = 50 Ω Input See Function Table Pulse generator RL 1Q1 to 2Q8 OPEN VTT CL GND RL 1D1 to 2D8 Symbol t PLH / t PHL Pulse generator 1LE, 2LE Zout = 50 Ω Note: S1 t su / t h / t w t ZH/ t HZ t ZL / t LZ S1 OPEN GND VTT 1. CL includes probe and jig capacitance. Waveforms – 1 tf tr VIH 90 % 90 % Input LE Vref Vref 10 % tr Input D 10 % tf VIH 90 % 90 % 10 % 10 % t PHL t PLH Output Q GND GND VOH Vref Vref VOL Note: Input waveform: PRR = 10 MHz, duty cycle 50%. Rev.1.00 Jan. 24, 2005 page 6 of 9 RD74LVC16373B Waveforms – 2 tr VIH 90 % Input LE 10 % 90 % Input D GND tf tr VIH 90 % Vref Vref 10 % t PHL 10 % t PLH GND VOH Vref Output Q Vref VOL Note: Input waveform: PRR = 10 MHz, duty cycle 50%. Waveforms – 3 tf tr VIH 90 % 90 % Vref Vref Input LE 10 % tw ts 10 % GND th VIH Input D Vref Vref GND Note: Input waveform: PRR = 10 MHz, duty cycle 50%. Rev.1.00 Jan. 24, 2005 page 7 of 9 RD74LVC16373B Waveforms – 4 tf Input G tr 90 % Vref 10 % VIH 90 % Vref 10 % t ZL GND t LZ ≈1/2 VTT Vref Waveform - A VOL + ∆V t ZH Waveform - B t HZ VOH – ∆V Vref VOL VOH ≈GND VCC (V) VCC = 1.8±0.15 V VCC = 2.5±0.2 V VCC = 2.7 V VCC = 3.3±0.3 V VCC = 5.0±0.5 V Notes: INPUTS VIH VCC VCC 2.7 V 2.7 V VCC tr/tf ≤ 2 ns ≤ 2 ns ≤ 2.5 ns ≤ 2.5 ns ≤ 2.5 ns Vref 1/2 VCC 1/2 VCC VTT 2× VCC 2× VCC 1.5 V 6V 6V 2× VCC 1.5 V 1/2 VCC CL RL 30 pF 30 pF 50 pF 50 pF 50 pF 1.0 kΩ 500 Ω 500 Ω 500 Ω 500 Ω ∆V 0.15 V 0.15 V 0.3 V 0.3 V 0.3 V 1. Input waveform :PRR = 10 MHz, duty cycle 50% 2. Waveform – A shows input conditions such that the output is "L" level when enable by the output control. 3. Waveform – B shows input conditions such that the output is "H" level when enable by the output control. Rev.1.00 Jan. 24, 2005 page 8 of 9 RD74LVC16373B Package Dimensions JEITA Package Code P-TSSOP48-6.1x12.5-0.50 RENESAS Code PTSP0048KA-A *1 MASS[Typ.] 0.2g Previous Code TTP-48DBV NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. D F 48 25 HE *2 E c bp Reference Symbol Index mark Terminal cross section ( Ni/Pd/Au plating ) Dimension in Millimeters Min Nom Max D 12.5 12.7 E 6.10 A2 Z A1 24 1 e *3 bp L1 x 0.08 0.13 A M 0.18 1.20 bp 0.14 0.19 0.24 0.10 0.15 0.20 8.10 8.30 b1 c A c A1 θ y L Detail F 1 θ 0° HE 7.90 e 0.50 x 0.08 y 0.10 Z 0.65 L L Rev.1.00 Jan. 24, 2005 page 9 of 9 8° 0.4 1 0.5 1.0 0.6 Sales Strategic Planning Div. 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