RENESAS HD74CBT32160C

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April 1, 2003
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HD74CBT32160C
16-bit to 32-bit Demux PCI Hot-plug Bus Switch
ADE-205-673 (Z)
Preliminary
Rev. 0
Feb. 2002
Description
The HD74CBT32160C device provides 16-bit to 32-bit demux PCI Hot-plug bus switching. The low on
state resistance of the switch allows connections to be made with minimal propagation delay. Select
control (SEL1, SEL2) inputs, select the appropriate B1 and B2 outputs for the A-input data.
Features
• Minimal propagation delay through the switch.
• 5 Ω switch connection between two ports.
Pullup on B1 and B2 ports.
• TTL-compatible input levels.
• Ultra low quiescent power.
-Ideally suited for notebook applications.
• Package type
Product code example: HD74CBT32160CTEL
Package type
Package code
Package suffix
Taping code
TSSOP-56pin
TTP-56DAV
T
EL (1,000 pcs / Reel)
Function Table
Inputs
SEL1
SEL2
Function
L
H
nA to nB1
H
L
nA to nB2
L
L
nA to nB1 and nB2
H
H
nB1, nB2 = VBIAS
H:
L:
High level
Low level
HD74CBT32160C
Pin Arrangement
1B1 1
56 1A
2B1 2
55 1B2
2A 3
54 2B2
3B1 4
53 3A
4B1 5
52 3B2
4A 6
51 4B2
5B1 7
50 5A
6B1 8
49 5B2
6A 9
48 6B2
7B1 10
47 7A
8B1 11
46 7B2
8A 12
45 8B2
GND 13
44 GND
Vcc 14
43 Vcc
9B1 15
42 9A
10B1 16
41 9B2
10A 17
40 10B2
11B1 18
39 11A
12B1 19
38 11B2
12A 20
37 12B2
13B1 21
36 13A
14B1 22
35 13B2
14A 23
34 14B2
15B1 24
33 15A
16B1 25
32 15B2
16A 26
31 16B2
VBIAS1 27
30 VBIAS2
SEL1 28
29 SEL2
(Top view)
Rev.0, Feb. 2002, page 2 of 2
HD74CBT32160C
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
VCC
−0.5 to 7.0
V
VI
−0.5 to 7.0
V
Input clamp current
IIK
−50
mA
VI < 0
Continuous output current
IO
128
mA
VO = 0 to VCC
Continuous current through
VCC or GND
ICC or IGND
±100
mA
Maximum power dissipation
*2
at Ta = 25°C (in still air)
PT
1.32
W
Storage temperature
Tstg
−65 to 150
°C
Supply voltage range
Input voltage range
Notes:
*1
Conditions
The absolute maximum ratings are values which must not individually be exceeded, and
furthermore, no two of which may be realized at the same time.
1. The input and output voltage ratings may be exceeded even if the input and output clamp-current
ratings are observed.
2. The maximum package power dissipation was calculated using a junction temperature of 150°C.
Recommended Operating Conditions
Item
Symbol
Min
Max
Unit
Supply voltage range
VCC
4.5
5.5
V
VBIAS
1.3
VCC
Input voltage range
VI
0
5.5
V
Output voltage range
VI/O
0
5.5
V
Input transition rise or fall rate
∆t / ∆v
0
5
ns / V
Operating free-air temperature
Ta
−40
85
°C
Conditions
VCC = 4.5 to 5.5 V
Note: Unused or floating inputs must be held high or low.
Rev.0, Feb. 2002, page 3 of 3
HD74CBT32160C
Logic Diagram
VBIAS1
1A
1B1
VBIAS2
1B2
VBIAS1
16A
16B1
VBIAS2
16B2
SEL1
SEL2
Rev.0, Feb. 2002, page 4 of 4
HD74CBT32160C
DC Electrical Characteristics
(Ta = −40 to 85°C)
Item
Symbol
VCC (V)
Min
Typ
Clamp diode voltage
VIK
4.5

Input voltage
VIH
4.0 to 5.5
VIL
RON
On-state switch
*2
resistance
*1
Max
Unit
Test conditions

−1.2
V
IIN = −18 mA
2.0


V
4.0 to 5.5


0.8
4.5

5
8
4.5

10
15
Ω
VIN = 0 V,
IIN = 48 mA
VIN = 2.4 V,
IIN = 15 mA
Input current
IIN
0 to 5.5


±1.0
µA
VIN = 5.5 V or GND
Off-state leakage
current
IOZA
5.5


20
µA
A = 5.5 V, VBIAS = 5.5 V
IOZB
–1.0


A = 0 V, VBIAS = 5.5 V


±1.0
B = 5.5 V, VBIAS = 5.5 V
–5

–0.25
mA
B = 0 V, VBIAS = 5.5 V
Quiescent supply
current
ICC
5.5


3
µA
VIN = VCC or GND,
IO = 0 mA
Increase in ICC
*3
per input
∆ICC
5.5


2.5
mA
One input at 3.4 V,
other inputs at VCC or
GND
Notes:
For condition shown as Min or Max use the appropriate values under recommended operating
conditions.
1. All typical values are at VCC = 5 V (unless otherwise noted), Ta = 25°C.
2. Measured by the voltage drop between the A and B terminals at the indicated current through the
switch. On-state resistance is determined by the lower voltage of the two (A or B) terminals.
3. This is the increase in supply current for each input that is at the specified TTL voltage level
rather than VCC or GND.
Capacitance
(Ta = 25°C)
Item
Symbol
VCC (V)
Min
Typ
Max
Unit
Test conditions
Control input
capacitance
CIN
5.0

5

pF
VIN = 0 or 3 V
CI/O (OFF)
5.0

10

pF

7

VO = 0 or 3 V
SEL1, SEL2 = VCC
Input / output
capacitance
A port
B port
Note: This parameter is determined by device characterization is not production tested.
Rev.0, Feb. 2002, page 5 of 5
HD74CBT32160C
Switching Characteristics
(Ta = −40 to 85°C)
•
VCC = 5.0±0.5 V, VBIAS = VCC
Test
conditions
FROM
(Input)
TO
(Output)
ns
CL = 50 pF
RL = 500 Ω
A or B
B or A
7.0
ns
CL = 50 pF
RL = 500 Ω
SEL
A or B
2.0
6.0
ns
SEL
A or B
2.0
7.0
CL = 50 pF
RL = 500 Ω
Item
Symbol
Min
Max
Unit
Propagation delay
*1
time
tPLH
tPHL

0.25
Enable time
tZH
tZL
2.0
Disable time
tHZ
tLZ
Notes: 1. The propagation delay is the calculated RC time constant of the typical on-state resistance of the
switch and the specified load capacitance, when driven by an ideal voltage source (zero output
impedance).
Test Circuit
See under table
500 Ω
S1
OPEN
GND
*1
CL = 50 pF
500 Ω
Load circuit for outputs
Symbol
S1
t PLH / tPHL
OPEN
t ZH / t HZ
OPEN
t ZL / t LZ
7V
Note: 1. CL includes probe and jig capacitance.
Rev.0, Feb. 2002, page 6 of 6
HD74CBT32160C
Waveforms – 1
tr
tf
90 %
1.5 V
Input
3V
90 %
1.5 V
10 %
10 %
t PLH
GND
t PHL
V OH
1.5 V
Output
1.5 V
V OL
Waveforms – 2
tf
tr
90 %
Output
Control
3V
90 %
1.5 V
1.5 V
10 %
t ZL
10 %
GND
t LZ
3.5 V
Waveform - A
1.5 V
V OL + 0.3 V
t ZH
t HZ
V OH - 0.3 V
Waveform - B
V OL
V OH
1.5 V
GND
Notes: 1. All input pulses are supplied by generators having the following characteristics :
PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
2. Waveform - A is for an output with internal conditions such that the output is low except
when disabled by the output control.
3. Waveform - B is for an output with internal conditions such that the output is high except
when disabled by the output control.
4. The output are measured one at a time with one transition per measurement.
Rev.0, Feb. 2002, page 7 of 7
HD74CBT32160C
Package Dimensions
As of July, 2001
14.0
14.2 Max
29
6.10
56
Unit: mm
1
*0.19 ± 0.05
0.50
28
0.08 M
1.0
8.10 ± 0.20
0.65 Max
*Pd plating
Rev.0, Feb. 2002, page 8 of 8
0.10 ± 0.05
0.10
*0.15 ± 0.05
1.20 Max
0˚ – 8˚
0.50 ± 0.1
Hitachi Code
JEDEC
JEITA
Mass (reference value)
TTP-56DAV
—
—
0.32 g
HD74CBT32160C
Disclaimer
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
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contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
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products.
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Copyright © Hitachi, Ltd., 2002. All rights reserved. Printed in Japan.
Colophon 5.0
Rev.0, Feb. 2002, page 9 of 9