Datasheet

UNISONIC TECHNOLOGIES CO., LTD
UTRS485
Preliminary
CMOS IC
FAIL-SAFE, 2.5MBPS, RS-485 /
RS-422 TRANSCEIVERS WITH
±15KV ESD-PROTECTED

DESCRIPTION
The UTC UTRS485 is a half-duplex transceiver designed for
RS-485 data bus network, which contains one transmitter and one
receiver. The UTC UTRS485 features a fail-safe receiver, which
guarantees the receiver to output high when the receiver inputs are
open, short or idle.
The UTC UTRS485 also features a hot-swap glitch free protection
circuits which guarantee outputs of both the transmitter and the
receiver in a high impedance state during the power up period. So that
the large short current from power to ground will be disable by glitch
free function, which will save the power and enhance the efficiency of
the power up.
The UTC UTRS485 is optimized for signal rates up to 2.5Mbps
with differential voltage of 2.3V. The UTC UTRS485 also has the
thermal shutdown function when the temperature is over 150℃ and
the protection of the current limitation in the transmitter to protect the
itself from the damage by the system-fault conditions during normal
operation.

SOP-8
FEATURES
* Meet the requirements of the EIA/TIA-485 standards.
* 5.0V single power supply.
* True fail-safe receiver while maintaining EIA/TIA-485 compatibility.
* Hot-Swap glitch free protection on control inputs.
* Up to 256 transceivers on the bus.
* Driver short circuit current limit.
* Thermal shutdown for overload protection.

ORDERING INFORMATION
Ordering Number
UTRS485G-S08-R
Package
SOP-8
Packing
Tape Reel
UTRS485G-S08-R
(1)Packing Type
(1) R: Tape Reel
(2)Package Type
(2) S08: SOP-8
(3)Green Package
(3) G: Halogen Free and Lead Free
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Copyright © 2015 Unisonic Technologies Co., Ltd
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Preliminary

MARKING

PIN CONFIGURATION
RO 1
8 VCC
RE
2
7 B
DE 3
6 A
DI 4

CMOS IC
5 GND
PIN DESCRIPTION
PIN NO.
1
PIN NAME
RO
2
RE
3
DE
4
DI
5
6
7
8
GND
A
B
VCC
DESCRIPTION
Receiver output: if A>B by 200mV, RO will be high; if A<B by 200mV, RO will be low.
Receiver output enable. RO is enable when RE is low; RO is high impedance when
RE is high.
Driver output enable. The driver outputs, Y and Z, are enabled by bringing DE high. They
are high impedance when DE is low. If the driver outputs are enabled, the parts function
as line drivers. While they are high impedance, they function as line receivers if RE is
low.
Driver Input. A low on DI forces output Y low and output Z high. Similarly, a high on DI
forces output Y high and output Z low.
Ground
Non-inverting receiver input and non-inverting driver output
Inverting receiver input and inverting driver output
Positive supply; 4.75V≤VCC≤5.25V
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
Preliminary
CMOS IC
BLOCK DIAGRAM
RO 1
RX
8
VCC
RE
2
7
B
DE
3
6
A
DI 4
TX
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5 GND
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Preliminary
CMOS IC
ABSOLUTE MAXIMUM RATING
PARAMETER
SYMBOL
VCC
Supply Voltage
RATINGS
12
UNIT
V
V
-0.5~(VCC+0.5)
Control Input Voltage ( RE , DE)
Driver Input Voltage (DI)
DI
-0.5~(VCC+0.5)
V
Driver Output Voltage (A, B)
-8~+12.5
V
Receiver Input Voltage (A, B)
-8~+12.5
V
Receiver Output Voltage (RO)
-0.5~(VCC+0.5)
V
Continuous Power Dissipation
Derate 5.88mW/°C above +70°C
471
mW
(TA=+70°C)
Lead Temperature (Soldering, 10sec)
TL
+300
°C
Operating Temperature Ranges
TOPR
-40~+85
°C
Storage Temperature Range
TSTG
-65~+160
°C
Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.

DC ELECTRICAL CHARACTERISTICS
(VCC=5.0V ±5%, TA=TMIN to TMAX, unless otherwise noted. (Note 1, 2)
PARAMETER
SYMBOL
TEST CONDITIONS
Differential Driver Output
VOD1
(No Load)
Differential Driver Output
R=50Ω (RS-422)
VOD2
(with Load)
Fig.1, R=27Ω (RS-485)
Change in Magnitude of Driver
Differential Output Voltage for
∆VOD Fig.1, R=27Ω or 50Ω
Complementary Output States
Driver Common-Mode Output
VOC
Fig.1, R=27Ω or 50Ω
Voltage
Change in Magnitude of Driver
Common-Mode Output Voltage
∆VOD Fig.1, R=27Ω or 50Ω
for Complementary Output
States
Input High Voltage
VIH1
Input Low Voltage
VIL1
DE, DI, RE
Input Current
IIN1
DE, DI, RE
DE=0V;
VCC=0V or 5.25V
Input Current (A, B)
Receiver Differential Threshold
Voltage
Receiver Input Hysteresis
Receiver Output High Voltage
Receiver Output Low Voltage
Three-State (High Impedance)
Output Current at Receiver
Receiver Input Resistance
No-Load Supply Current
(Note 3)
Driver Short-Circuit Current,
VO=High
Driver Short-Circuit Current,
VO=Low
Receiver Short-Circuit Current
IIN2
VTH
MIN
2.0
1.5
UNIT
5.0
V
5
V
V
0.2
V
3.0
V
0.2
V
0.8
V
V
VIN=12V
VIN=-7V
-0.2
∆VTH
VOH
VOL
VCM=0V
IO=-4mA, VID=200mV
IO=4mA, VID=-200mV
3.5
IOZR
0.4V≤VO≤ 2.4V
RIN
-7V≤VCM≤+12V
RE =0V or VCC
MAX
2.0
DE, DI, RE
-7V≤VCM≤+12V
ICC
TYP
±2.0
µA
1.0
-0.8
mA
mA
0.2
V
0.5
mV
V
V
±1.0
µA
900
500
kΩ
µA
µA
70
12
DE=VCC
DE=0V
500
300
IOSD1
-7V≤VO≤12V (Note 4)
35
250
mA
IOSD2
-7V≤VO≤12V (Note 4)
35
250
mA
IOSR
0V≤VO≤VCC
7
95
mA
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Preliminary
CMOS IC
SWITCHING CHARACTERISTICS
(VCC=+5.0V ±5%, TA=TMIN to TMAX, unless otherwise noted.) (Note 1, 2)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNIT
tPLH
10
50
100
ns
Fig.3 and 5, RDIFF=54Ω, CL1=CL2=100pF
Driver Input to Output
tPHL
10
50
100
ns
Driver Output Skew to Output
tSKEW Fig.3 and 5, RDIFF=54Ω, CL1=CL2=100pF
10
ns
Driver Rise or Fall Time
tDR, tDF Fig.3 and 5, RDIFF=54Ω, CL1=CL2=100pF
3
15
40
ns
Driver Enable to Output High
tZH
Fig.4 and 6, CL=100pF, S2 Closed
80
150
ns
Driver Enable to Output Low
tZL
Fig.4 and 6, CL=100pF, S1 Closed
80
150
ns
Driver Disable Time from Low
tLZ
Fig.4 and 6, CL=15pF, S1 Closed
80
150
ns
Driver Disable Time from High
tHZ
Fig.4 and 6, CL=15pF, S2 Closed
80
150
ns
tPLH,
Fig.3 and 7, RDIFF=54Ω, CL1=CL2=100pF
Receiver Input to Output
20
500 1000
ns
tPHL
|tPLH - tPHL| Differential
tSKD
Fig.3 and 7, RDIFF=54Ω, CL1=CL2=100pF
100
ns
Receiver Skew
Receiver Enable to Output Low
tZL
Fig.2 and 8, CRL=15pF, S1 Closed
30
60
ns
Receiver Enable to Output High
tZH
Fig.2 and 8, CRL=15pF, S2 Closed
30
60
ns
Receiver Disable Time from Low
tLZ
Fig.2 and 8, CRL=15pF, S1 Closed
30
60
ns
Receiver Disable Time from
tHZ
Fig.2 and 8, CRL=15pF, S2 Closed
30
60
ns
High
Notes: 1. All currents into the device are positive; all currents out of the device are negative. All voltages are
referenced to device ground unless otherwise specified.
2. All typical specifications are given for VCC=5V and TA=+25°C
3. Supply current specification is valid for loaded transmitters when DE=0V
4. Applies to peak current
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Preliminary
CMOS IC
FUNCTION TABLE
Table 1 TRANSMITTING
INPUTS
RE
X
X
0
1
OUTPUTS
DE
DI
B
A
1
1
0
0
1
0
X
X
0
1
High-Z
High-Z
1
0
High-Z
High-Z
Table 2
RECEIVING
INPUTS
RE
0
0
0
1
X = Don’t care
High-Z = High impedance
OUTPUTS
DE
A-B
RO
0
0
0
0
≥+0.2V
≤-0.2V
Inputs open
X
1
0
1
High-Z
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
Preliminary
CMOS IC
TEST CIRCUIT
Y
RECEIVER
OUTPUT
R
TEST POINT
CRL
VOD
+
VCC
1kΩ
15pF
VOC
R
1kΩ
S1
S2
Z
Fig. 2 Receiver Timing Test Load
Fig. 1 Driver DC Test Load
3V
DE
Y
DI
VID
OUTPUT
UNDER TEST
A
CL1
RO
RDIFF
Z
CL2
CL
RO
Fig. 4 Driver Timing Test Load
1.5V
Output
3V
1.5V
1.5V
0V
tZL(SHDN), tZL
VOL
tLZ
VCC
tPHL
A-B VID
-VID
500Ω
S2
RE
1.5V
+
RE
B
Fig. 3 Driver/Receiver Timing Test Circuit
VOH
VCC
S1
0V
Input
1.5V OUTPUT NORMALLY LOW
RO
1.5V
VOL+0.5V
OUTPUT NORMALLY HIGH
0V
Fig. 7 Receiver Propagation Delays
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RO
tPLH
0V
tZH(SHDN), tZH
VOH-0.5V
tHZ
Fig. 8 Receiver Enable and Disable Times
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
Preliminary
CMOS IC
TYPICAL APPLICATION CIRCUIT
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
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