ETC TPS767D318PWPR

TPS767D301, TPS767D318, TPS767D325
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
SLVS209C – JULY 1999 – REVISED FEBRUARY 2002
D
D
D
D
D
D
D
D
D
D
D
Dual Output Voltages for Split-Supply
Applications
Output Current Range of 0 mA to 1.0 A Per
Regulator
3.3-V/2.5-V, 3.3-V/1.8-V, and 3.3-V/Adjustable
Output
Fast-Transient Response
2% Tolerance Over Load and Temperature
Dropout Voltage Typically 350 mV at 1 A
Ultra Low 85 µA Typical Quiescent Current
1 µA Quiescent Current During Shutdown
Dual Open Drain Power-On Reset With
200-ms Delay for Each Regulator
28-Pin PowerPAD TSSOP Package
Thermal Shutdown Protection for Each
Regulator
PWP PACKAGE
(TOP VIEW)
NC
NC
1GND
1EN
1IN
1IN
NC
NC
2GND
2EN
2IN
2IN
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1RESET
NC
NC
1FB/NC
1OUT
1OUT
2RESET
NC
NC
NC
2OUT
2OUT
NC
NC
NC – No internal connection
description
The TPS767D3xx family of dual voltage regulators offers fast transient response, low dropout voltages and dual
outputs in a compact package and incorporating stability with 10-µF low ESR output capacitors.
DROPOUT VOLTAGE
vs
FREE-AIR TEMPERATURE
LOAD TRANSIENT RESPONSE
103
VO = 3.3 V
CL =100 µF
TA = 25°C
50
IO = 1 A
VDO – Dropout Voltage – mV
I O – Output Current – A
∆ VO – Change in
Output Voltage – mV
100
0
–50
–100
1
0.5
0
102
101
IO = 10 mA
100
10–1
VO = 3.3 V
CO = 10 µF
0
20
40
60
80 100 120 140 160 180 200
t – Time – µs
10–2
–60 –40 –20
IO = 0
0
20
40
60
80 100 120 140
TA – Free-Air Temperature – °C
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments Incorporated.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
TPS767D301, TPS767D318, TPS767D325
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
SLVS209C – JULY 1999 – REVISED FEBRUARY 2002
description (continued)
The TPS767D3xx family of dual voltage regulators is designed primarily for DSP applications. These devices
can be used in any mixed-output voltage application, with each regulator supporting up to 1 A. Dual active-low
reset signals allow resetting of core-logic and I/O separately.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 350 mV
at an output current of 1 A for the TPS767D325) and is directly proportional to the output current. Additionally,
since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent
of output loading (typically 85 µA over the full range of output current, 0 mA to 1 A). These two key specifications
yield a significant improvement in operating life for battery-powered systems. This LDO family also features a
sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent current
to 1 µA at TJ = 25°C.
The RESET output of the TPS767D3xx initiates a reset in microcomputer and microprocessor systems in the
event of an undervoltage condition. An internal comparator in the TPS767D3xx monitors the output voltage of
the regulator to detect an undervoltage condition on the regulated output voltage.
The TPS767D3xx is offered in 1.8-V, 2.5-V, and 3.3-V fixed-voltage versions and in an adjustable version
(programmable over the range of 1.5 V to 5.5 V). Output voltage tolerance is specified as a maximum of 2%
over line, load, and temperature ranges. The TPS767D3xx family is available in 28 pin PWP TSSOP package.
They operate over a junction temperature range of –40°C to 125°C.
AVAILABLE OPTIONS
TA
– 40°C to 125°C
REGULATOR 1
VO (V)
REGULATOR 2
VO (V)
TSSOP
(PWP)
Adj (1.5 – 5.5 V)
3.3 V
TPS767D301PWP
1.8 V
3.3 V
TPS767D318PWP
2.5 V
3.3 V
TPS767D325PWP
The TPS767D301 is adjustable using an external resistor divider (see application
information). The PWP packages are available taped and reeled. Add an R suffix
to the device type (e.g., TPS767D301PWPR).
TPS767D3xx
VI
5
6
C1
0.1 µF
50 V
IN
RESET
RESET
250 kΩ
IN
OUT
4
28
EN
OUT
GND
24
VO
23
+
CO
10 µF
3
Figure 1. Typical Application Circuit (Fixed Versions) for Single Channel
2
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• DALLAS, TEXAS 75265
TPS767D301, TPS767D318, TPS767D325
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
SLVS209C – JULY 1999 – REVISED FEBRUARY 2002
functional block diagram—adjustable version (for each LDO)
IN
EN
RESET
_
+
OUT
+
_
200 ms Delay
R1
Vref = 1.1834 V
R2
GND
functional block diagram—fixed-voltage version (for each LDO)
IN
EN
RESET
_
+
OUT
+
_
200 ms Delay
Vref = 1.1834 V
R1
FB/NC
R2
GND
External to the device
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3
TPS767D301, TPS767D318, TPS767D325
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
SLVS209C – JULY 1999 – REVISED FEBRUARY 2002
Terminal Functions
TERMINAL
NAME
1GND
I/O
NO.
3
DESCRIPTION
Regulator #1 ground
1EN
4
I
Regulator #1 enable
1IN
5, 6
I
Regulator #1 input supply voltage
2GND
9
Regulator #2 ground
2EN
10
I
Regulator #2 enable
2IN
11, 12
I
Regulator #2 input supply voltage
2OUT
17, 18
O
Regulator #2 output voltage
22
O
Regulator #2 reset signal
23, 24
O
Regulator #1 output voltage
2RESET
1OUT
1FB/NC
25
I
Regulator #1 output voltage feedback for adjustable and no connect for fixed output
1RESET
28
O
Regulator #1 reset signal
NC
1, 2, 7, 8,
13–16, 19, 20,
21, 26, 27
No connection
timing diagram
VI
Vres†
Vres
t
VO
VIT +‡
VIT +‡
Threshold
Voltage
VIT –
Less than 5% of the
output voltage
VIT –
t
RESET
Output
Output
Undefined
ÎÎ
ÎÎ
ÎÎ
ÎÎ
200 ms
Delay
200 ms
Delay
ÎÎ
ÎÎ
ÎÎ
ÎÎ
Output
Undefined
t
† Vres is the minimum input voltage for a valid RESET. The symbol Vres is not currently listed within EIA or JEDEC standards
for semiconductor symbology.
‡ VIT –Trip voltage is typically 5% lower than the output voltage (95%VO)
4
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• DALLAS, TEXAS 75265
TPS767D301, TPS767D318, TPS767D325
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
SLVS209C – JULY 1999 – REVISED FEBRUARY 2002
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Input voltage range‡, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 13.5 V
Input voltage range, VI (1IN, 2IN, EN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VI + 0.3 V
Output voltage, VO (1OUT, 2OUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Output voltage, VO (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5 V
Peak output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited
ESD rating, HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See dissipation rating tables
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡ All voltage values are with respect to network terminal ground.
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
DISSIPATION RATING TABLE
PACKAGE
PWP†
AIR FLOW
(CFM)
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
0
3.58 W
35.8 mW/°C
1.97 W
1.43 W
250
5.07 W
50.7 mW/°C
2.79 W
2.03 W
† This parameter is measured with the recommended copper heat sink pattern on a 4–layer PCB, 1 oz. copper on 4–in x 4–in
ground layer. For more information, refer to TI technical brief literature number SLMA002.
recommended operating conditions
Input voltage, VI# (1IN, 2IN)
Output current for each LDO, IO (Note 1)
Output voltage range, VO (1OUT, 2OUT)
MIN
MAX
2.7
10
UNIT
V
0
1.0
A
1.5
5.5
V
Operating virtual junction temperature, TJ
– 40
125
°C
# To calculate the minimum input voltage for your maximum output current, use the following equation: VI(min) = VO(max) + VDO(max load).
NOTE 1: Continuous current and operating junction temperature are limited by internal protection circuitry, but it is not recommended that the
device operate under conditions beyond those specified in this table for extended periods of time.
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5
TPS767D301, TPS767D318, TPS767D325
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
SLVS209C – JULY 1999 – REVISED FEBRUARY 2002
electrical characteristics, Vi = VO(nom) + 1 V, IO = 1 mA, EN = 0, CO = 10 µF(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
1.5 V ≤ VO ≤ 5.5 V,,
10 µA < IO < 1 A
TJ = 25°C
TJ = –40°C to 125°C
1 8 V Ouput
1.8
2.8 V < VI < 10 V,,
10 µA < IO < 1 A
TJ = 25°C
TJ = –40°C to 125°C
1.764
2 5 V Output
2.5
3.5 V < VI < 10 V,,
10 µA < IO < 1 A
TJ = 25°C
TJ = –40°C to 125°C
2.45
3 3 V Output
3.3
4.3 V < VI < 10 V,,
10 µA < IO < 1 A
TJ = 25°C
TJ = –40°C to 125°C
3.234
10 µA < IO < 1 A,
TJ = 25°C
IO = 1 A,
TJ = –40°C to 125°C
Output voltage line regulation for each LDO
(∆VO/VO) (see Notes 2 and 3)
VO + 1 V < VI ≤ 10 V,
TJ = 25°C
Output noise voltage
BW = 200 Hz to 100 kHz, VO = 1.8 V,
IC = 1 A, CO = 10 µF, TJ = 25°C
Output current Limit for each LDO
VO = 0 V
Adjustable
Output voltage
g ((VO)
(see Note 2)
Quiescent current (GND current) for each LDO
(see Note 2)
TYP
0.98VO
1.836
Standby current for each LDO
FB input current
Adjustable
2.7 < VI < 10V,
TJ = –40°C to 125°C
EN = VI,
2.55
3.3
3.366
85
0.01
µVrms
2
FB = 1.5 V
°C
1
µA
2
Trip threshold voltage
VO decreasing
Hysteresis voltage
Measured at VO
Output low voltage
VI = 2.7 V,
Leakage current
V(RESET) = 7 V
V
CO = 10 µF
dB
1.1
V
98
0.5
0.15
RESET time-out delay
200
Line Reg. (mV)
+ ǒ%ńVǓ
V
O
If VO ≥ 2.5 V, VImin = Vo + 1 V, and VImax = 10 V:
Line Reg. (mV)
+ ǒ%ńVǓ
V
POST OFFICE BOX 655303
O
ǒ
V
ǒ
* 2.7 V
Imax
100
V
Imax
*
ǒ
V
O
100
• DALLAS, TEXAS 75265
Ǔ
1000
)1 V
ǓǓ
1000
V
60
92
IO(RESET) = 1 mA
µA
nA
0.8
Minimum input voltage for valid RESET
A
150
10
NOTES: 2. Minimum IN operating voltage is 2.7 V or VO(typ) + 1 V, whichever is greater. maximum IN voltage 10V.
3. If VO ≤ 1.8 V, VImin = 2.7 V, and VImax = 10 V:
6
%/V
55
Low level enable input voltage
Reset
µA
2.0
Power supply ripple rejection (see Note 2)
V
125
High level enable input voltage
f = 1 KHz,
TJ = 25°C,
IO(RESET) = 300µA
V
2.5
1.7
EN = VI,
UNIT
1.02VO
1.8
Thermal shutdown juction temperature
2.7 < VI < 10V,
TJ = 25°C,
MAX
VO
%VO
%VO
0.4
V
1
µA
mA
TPS767D301, TPS767D318, TPS767D325
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
SLVS209C – JULY 1999 – REVISED FEBRUARY 2002
electrical characteristics, Vi = VO(nom) + 1 V, IO = 1 mA, EN = 0, CO = 10 µF(unless otherwise noted)
(continued)
PARAMETER
Input current (EN)
MIN
TYP
MAX
EN = 0 V
TEST CONDITIONS
–1
0
1
EN = VI
–1
Load regulation
Dropout voltage (see Note 4)
UNIT
µA
1
3
VO = 3.3 V,,
IO = 1 A
TJ = 25°C
TJ = –40°C to 125°C
mV
350
mV
575
NOTE 4: IN voltage equals Vo(Typ) – 100mV; Adjustable output voltage set to 3.3V nominal with external resistor divider. 1.8V, and 2.5V dropout
voltage is limited by input voltage range limitations.
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
vs Output current
2, 3, 4
vs Free-air temperature
5, 6, 7
Ground current
vs Free-air temperature
8, 9
Power supply ripple rejection
vs Frequency
10
Output spectral noise density
vs Frequency
11
Output impedance
vs Frequency
12
Dropout voltage
vs Free-air temperature
Output voltage
Line transient response
13
14, 16
Load transient response
15, 17
Output voltage
vs Time
18
Dropout voltage
vs Input voltage
19
vs Output current, TA = 25°C
21
vs Output current, TJ = 125°C
22
vs Output Current, TA = 25°C
23
vs Output current, TJ = 125°C
24
Equivalent series resistance (ESR)
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7
TPS767D301, TPS767D318, TPS767D325
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
SLVS209C – JULY 1999 – REVISED FEBRUARY 2002
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
1.7965
3.2835
VO = 1.8 V
VI = 2.8V
TA = 25°C
VO = 3.3 V
VI = 4.3 V
TA = 25°C
1.7960
VO – Output Voltage – V
3.2830
VO – Output Voltage – V
3.2825
3.2820
3.2815
3.2810
1.7955
1.7950
1.7945
3.2805
1.7940
3.2800
0
0.1
0.2 0.3 0.4 0.5 0.6 0.7 0.8
IO – Output Current – A
0.9
1
0
0.1
0.2 0.3
Figure 2
0.6 0.7
0.8
0.9
1
OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
2.4960
3.32
VO = 2.5 V
VI = 3.5 V
TA = 25°C
2.4955
3.31
VO – Output Voltage – V
2.4950
VO – Output Voltage – V
0.5
Figure 3
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
2.4945
2.4940
2.4935
2.4930
VO = 3.3 V
VI = 4.3 V
3.30
3.29
IO = 1 A
IO = 1 mA
3.28
3.27
3.26
2.4925
2.4920
0
0.1 0.2 0.3
0.4 0.5
0.6 0.7
0.8 0.9
1
3.25
–60 –40 –20
0
20
40
Figure 4
Figure 5
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60
80
100 120 140
TA – Free-Air Temperature – °C
IO – Output Current – A
8
0.4
IO – Output Current – A
• DALLAS, TEXAS 75265
TPS767D301, TPS767D318, TPS767D325
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
SLVS209C – JULY 1999 – REVISED FEBRUARY 2002
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
2.515
1.815
VO = 1.8 V
VI = 2.8 V
2.510
1.805
IO = 1 A
1.800
IO = 1 mA
1.795
1.790
VO – Output Voltage – V
VO – Output Voltage – V
1.810
VO = 2.5 V
VI = 3.5 V
2.505
2.500
IO = 1 A
2.495
IO = 1 mA
2.490
2.485
1.785
–60 –40 –20
0
20
40
60
80
100 120 140
2.480
–60 –40
TA – Free-Air Temperature – °C
–20
0
Figure 6
60
80
100 120
GROUND CURRENT
vs
FREE-AIR TEMPERATURE
96
92
VO = 3.3 V
VI = 4.3 V
94
VO = 1.8 V
VI = 2.8 V
92
88
IO = 1 mA
90
86
84
82
IO = 1 mA
80
IO = 1 A
78
IO = 500 mA
76
Ground Current – µ A
Ground Current – µ A
40
Figure 7
GROUND CURRENT
vs
FREE-AIR TEMPERATURE
90
20
TA – Free-Air Temperature – °C
88
86
IO = 500 mA
84
82
80
78
74
76
72
–60 –40 –20
0
20
40
60
80
100 120 140
IO = 1 A
74
–60 –40 –20
TA – Free-Air Temperature – °C
0
20
40
60
80
100 120 140
TA – Free-Air Temperature – °C
Figure 8
Figure 9
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• DALLAS, TEXAS 75265
9
TPS767D301, TPS767D318, TPS767D325
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
SLVS209C – JULY 1999 – REVISED FEBRUARY 2002
TYPICAL CHARACTERISTICS
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
POWER SUPPLY RIPPLE REJECTION
vs
FREQUENCY
10–5
Vn – Output Spectral Noise Density – V/ Hz
PSRR – Power Supply Ripple Rejection – dB
90
VO = 3.3 V
VI = 4.3 V
CO = 10 µF
IO = 1 A
TA = 25°C
80
70
60
50
40
30
20
10
0
– 10
10
100
1k
10k
100k
VI = 4.3 V
CO = 10 µF
TA = 25°C
IO = 7 mA
10–6
IO = 1 A
10–7
10–8
102
1M
103
f – Frequency – Hz
Figure 11
DROPOUT VOLTAGE
vs
FREE-AIR TEMPERATURE
OUTPUT IMPEDANCE
vs
FREQUENCY
103
0
IO = 1 A
VDO – Dropout Voltage – mV
Zo – Output Impedance – Ω
VI = 4.3 V
CO = 10 µF
TA = 25°C
IO = 1 mA
10–1
IO = 1 A
102
101
IO = 10 mA
100
10–1
VO = 3.3 V
CO = 10 µF
102
103
104
f – Frequency – kHz
105
106
10–2
–60 –40 –20
IO = 0
0
20
40
Figure 13
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60
80 100 120 140
TA – Free-Air Temperature – °C
Figure 12
10
105
f – Frequency – Hz
Figure 10
10–2
101
104
• DALLAS, TEXAS 75265
TPS767D301, TPS767D318, TPS767D325
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
SLVS209C – JULY 1999 – REVISED FEBRUARY 2002
TYPICAL CHARACTERISTICS
LINE TRANSIENT RESPONSE
LOAD TRANSIENT RESPONSE
∆ VO – Change in
Output Voltage – mV
3.8
2.8
VO = 1.8 V
IL = 10 mA
CL = 10 µF
TA = 25°C
20
0
–20
0
20
40
VO = 1.8 V
VI = 2.8 V
CL = 100 µF
TA = 25°C
50
0
–50
–100
I O – Output Current – A
∆ VO – Change in
Output Voltage – mV
VI – Input Voltage – V
100
60
1
0.5
0
0
80 100 120 140 160 180 200
t – Time – µs
20
40
60
Figure 15
Figure 14
LOAD TRANSIENT RESPONSE
100
∆ VO – Change in
Output Voltage – mV
VI – Input Voltage – V
LINE TRANSIENT RESPONSE
VO = 3.3 V
CL = 10 µF
TA = 25°C
5.3
I O – Output Current – A
4.3
∆ VO – Change in
Output Voltage – mV
80 100 120 140 160 180 200
t – Time – µs
10
0
–10
0
20
40
60
80 100 120 140 160 180 200
t – Time – µs
VO = 3.3 V
CL =100 µF
TA = 25°C
50
0
–50
–100
1
0.5
0
0
20
40
60
80 100 120 140 160 180 200
t – Time – µs
Figure 17
Figure 16
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• DALLAS, TEXAS 75265
11
TPS767D301, TPS767D318, TPS767D325
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
SLVS209C – JULY 1999 – REVISED FEBRUARY 2002
TYPICAL CHARACTERISTICS
DROPOUT VOLTAGE
vs
INPUT VOLTAGE
4
900
3
800
IO = 1A
VDO – Dropout Voltage – mV
VO– Output Voltage – V
OUTPUT VOLTAGE
vs
TIME (AT STARTUP)
2
1
Enable Pulse – V
0
0
700
600
500
TA = 25°C
400
TA = 125°C
300
200
TA = –40°C
100
0
0
20
40
60
80 100 120 140 160 180 200
t – Time – µs
2.5
Figure 18
VI
3
3.5
4
VI – Input Voltage – V
4.5
5
Figure 19
To Load
IN
OUT
+
EN
CO
GND
RL
ESR
Figure 20. Test Circuit for Typical Regions of Stability (Figures 21 through 24) (fixed output options)
12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS767D301, TPS767D318, TPS767D325
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
SLVS209C – JULY 1999 – REVISED FEBRUARY 2002
TYPICAL CHARACTERISTICS
TYPICAL REGION OF STABILITY
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE†
vs
OUTPUT CURRENT
EQUIVALENT SERIES RESISTANCE†
vs
OUTPUT CURRENT
10
ESR – Equivalent Series Resistance – Ω
ESR – Equivalent series restance – Ω
10
Region of Instability
1
Region of Stability
Vo = 3.3V
CL = 4.7µF
VI = 4.3V
TA = 25°C
0.1
0
200
400
600
800
Region of Instability
1
Region of Stability
VO = 3.3 V
Cl = 4.7 µF
VI = 4.3 V
TJ = 125°C
0.1
1000
0
200
IO – Output Current – mA
400
Figure 21
800
1000
Figure 22
TYPICAL REGION OF STABILITY
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE†
vs
OUTPUT CURRENT
EQUIVALENT SERIES RESISTANCE†
vs
OUTPUT CURRENT
10
10
ESR – Equivalent Series Resistance – Ω
ESR – Equivalent series restance – Ω
600
IO – Output Current – mA
Region of Instability
1
Region of Stability
VO = 3.3V
CL = 22µF
VI = 4.3V
TA = 25°C
0.1
0
200
400
600
800
1000
Region of Instability
1
Region of Stability
VO = 3.3V
Cl = 22µF
VI = 4.3V
TJ = 125°C
0.1
0
IO – Output Current – mA
200
400
600
800
1000
IO – Output Current – mA
Figure 23
Figure 24
† Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any series resistance added
externally, and PWB trace resistance to CO.
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TPS767D301, TPS767D318, TPS767D325
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
SLVS209C – JULY 1999 – REVISED FEBRUARY 2002
APPLICATION INFORMATION
The features of the TPS767D3xx family (low-dropout voltage, ultra low quiescent current, power-saving shutdown
mode, and a supply-voltage supervisor) and the power-dissipation properties of the TSSOP PowerPAD package
have enabled the integration of the dual LDO regulator with high output current for use in DSP and other multiple
voltage applications. Figure 25 shows a typical dual-voltage DSP application.
R1
100 kΩ
R2
100 kΩ
U1
TPS767D325
2
3
4
5
5V
6
C0
1 µF
7
8
9
10
11
12
13
14
PG
NC
1RESET
NC
NC
1GND
1EN
NC
1FB/NC
1IN
1OUT
1IN
1OUT
NC
2RESET
NC
NC
2GND
2EN
NC
NC
2IN
2OUT
2IN
2OUT
NC
NC
NC
NC
28
27
RESET to DSP
26
VC549
DSP
25
24
23
2.5 V
22
D1
21
20
C3
33 µF
19
18
17
+
DL4148
1
CVDD
(Core
Supply)
D3
DL5817
16
D2
15
3.3 V
C1
1 µF
DVDD
(I/O Supply)
C2
33 µF
GND
GND
Figure 25. Dual-Voltage DSP Application
DSP power requirements include very high transient currents that must be considered in the initial design. This design
uses higher-valued output capacitors to handle the large transient currents.
device operation
The TPS767D3xx features very low quiescent current, which remain virtually constant even with varying loads.
Conventional LDO regulators use a pnp pass element, the base current of which is directly proportional to the
load current through the regulator (IB = IC/β). Close examination of the data sheets reveals that these devices
are typically specified under near no-load conditions; actual operating currents are much higher as evidenced
by typical quiescent current versus load current curves. The TPS767D3xx uses a PMOS transistor to pass
current; because the gate of the PMOS is voltage driven, operating current is low and invariable over the full
load range. The TPS767D3xx specifications reflect actual performance under load condition.
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS767D301, TPS767D318, TPS767D325
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
SLVS209C – JULY 1999 – REVISED FEBRUARY 2002
Another pitfall associated with the pnp-pass element is its tendency to saturate when the device goes into
dropout. The resulting drop in β forces an increase in IB to maintain the load. During power up, this translates
to large start-up currents. Systems with limited supply current may fail to start up. In battery-powered systems,
it means rapid battery discharge when the voltage decays below the minimum required for regulation. The
TPS767D3xx quiescent current remains low even when the regulator drops out, eliminating both problems.
The TPS767D3xx family also features a shutdown mode that places the output in the high-impedance state
(essentially equal to the feedback-divider resistance) and reduces quiescent current to under 2 µA. If the
shutdown feature is not used, EN should be tied to ground. Response to an enable transition is quick; regulated
output voltage is typically reestablished in 120 µs.
minimum load requirements
The TPS767D3xx family is stable even at zero load; no minimum load is required for operation.
FB - pin connection (adjustable version only)
The FB pin is an input pin to sense the output voltage and close the loop for the adjustable option. The output
voltage is sensed through a resistor divider network as is shown in Figure 27 to close the loop. Normally, this
connection should be as short as possible; however, the connection can be made near a critical circuit to
improve performance at that point. Internally, FB connects to a high-impedance wide-bandwidth amplifier and
noise pickup feeds through to the regulator output. Routing the FB connection to minimize/avoid noise pickup
is essential. In fixed output options this pin is a no connect.
external capacitor requirements
An input capacitor is not required; however, a ceramic bypass capacitor (0.047 pF to 0.1 µF) improves load
transient response and noise rejection when the TPS767D3xx is located more than a few inches from the power
supply. A higher-capacitance electrolytic capacitor may be necessary if large (hundreds of milliamps) load
transients with fast rise times are anticipated.
Like all low dropout regulators, the TPS767D3xx requires an output capacitor connected between OUT and
GND to stabilize the internal control loop. The minimum recommended capacitance value is 10 µF and the ESR
(equivalent series resistance) must be between 50 mΩ and 1.5 Ω. Capacitor values 10 µF or larger are
acceptable, provided the ESR is less than 1.5 Ω. Solid tantalum electrolytic, aluminum electrolytic, and
multilayer ceramic capacitors are all suitable, provided they meet the requirements described previously.
POST OFFICE BOX 655303
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TPS767D301, TPS767D318, TPS767D325
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
SLVS209C – JULY 1999 – REVISED FEBRUARY 2002
external capacitor requirements (continued)
When necessary to achieve low height requirements along with high output current and/or high ceramic load
capacitance, several higher ESR capacitors can be used in parallel to meet the previous guidelines.
TPS767D3xx
5
VI
6
IN
28
RESET
250 kΩ
IN
24
OUT
C1
0.1 µF
50 V
4
RESET
EN
VO
23
OUT
+
GND
CO
10 µF
3
Figure 26. Typical Application Circuit (Fixed Versions) for Single Channel
programming the TPS767D301 adjustable LDO regulator
The output voltage of the TPS767D301 adjustable regulator is programmed using an external resistor divider
as shown in Figure 27. The output voltage is calculated using:
V
O
ǒ) Ǔ
+ Vref
R1
R2
1
(1)
Where:
Vref = 1.1834 V typ (the internal reference voltage)
Resistors R1 and R2 should be chosen for approximately 50-µA divider current. Lower value resistors can be
used but offer no inherent advantage and waste more power. Higher values should be avoided as leakage
currents at FB increase the output voltage error. The recommended design procedure is to choose
R2 = 30.1 kΩ to set the divider current at 50 µA and then calculate R1 using:
R1
+
ǒ Ǔ
V
V
O
ref
*1
(2)
R2
OUTPUT VOLTAGE
PROGRAMMING GUIDE
TPS767D301
VI
0.1 µF
IN
RESET
RESET Output
250 kΩ
>2.7 V
EN
OUT
<0.5V
R1
FB / NC
GND
+
OUTPUT
VOLTAGE
R1
33.2
30.1
kΩ
3.3 V
53.6
30.1
kΩ
VO
3.6 V
61.9
30.1
kΩ
CO
4 75V
90.8
30.1
kΩ
10 µF
R2
POST OFFICE BOX 655303
UNIT
2.5 V
Figure 27. TPS767D301 Adjustable LDO Regulator Programming
16
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• DALLAS, TEXAS 75265
TPS767D301, TPS767D318, TPS767D325
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
SLVS209C – JULY 1999 – REVISED FEBRUARY 2002
Reset indicator
The TPS767D3xx features a RESET output that can be used to monitor the status of the regulator. The internal
comparator monitors the output voltage: when the output drops to 95% (typical) of its regulated value, the
RESET output transistor turns on, taking the signal low. The open-drain output requires a pullup resistor. If not
used, it can be left floating. RESET can be used to drive power-on reset circuitry or as a low-battery indicator.
regulator protection
The TPS767D3xx PMOS-pass transistor has a built-in back-gate diode that safely conducts reverse currents
when the input voltage drops below the output voltage (e.g., during power down). Current is conducted from
the output to the input and is not internally limited. When extended reverse voltage is anticipated, external
limiting may be appropriate.
The TPS767D3xx also features internal current limiting and thermal protection. During normal operation, the
TPS767D3xx limits output current to approximately 1.7 A. When current limiting engages, the output voltage
scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross
device failure, care should be taken not to exceed the power dissipation ratings of the package. If the
temperature of the device exceeds 150°C(typ), thermal-protection circuitry shuts it down. Once the device has
cooled below 130°C(typ), regulator operation resumes.
power dissipation and junction temperature
Specified regulator operation is assured to a junction temperature of 125°C; the maximum junction temperature
should be restricted to 125°C under normal operating conditions. This restriction limits the power dissipation
the regulator can handle in any given application. To ensure the junction temperature is within acceptable limits,
calculate the maximum allowable dissipation, PD(max), and the actual dissipation, PD, which must be less than
or equal to PD(max).
The maximum-power-dissipation limit is determined using the following equation:
P
T max * T
J
A
+
D(max)
R
qJA
Where:
TJmax is the maximum allowable junction temperature
RθJA is the thermal resistance junction-to-ambient for the package, i.e., 27.9°C/W for the 28-terminal
PWP with no airflow.
TA is the ambient temperature.
ǒ
Ǔ
The regulator dissipation is calculated using:
P
D
+ VI * VO
I
O
Power dissipation resulting from quiescent current is negligible. Excessive power dissipation will trigger the
thermal protection circuit.
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TPS767D301, TPS767D318, TPS767D325
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
SLVS209C – JULY 1999 – REVISED FEBRUARY 2002
MECHANICAL DATA
PWP (R-PDSO-G**)
PowerPAD PLASTIC SMALL-OUTLINE PACKAGE
20-PIN SHOWN
0,30
0,19
0,65
20
0,10 M
11
Thermal Pad
(See Note D)
4,50
4,30
0,15 NOM
6,60
6,20
Gage Plane
1
10
0,25
A
0°– 8°
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
14
16
20
24
28
A MAX
5,10
5,10
6,60
7,90
9,80
A MIN
4,90
4,90
6,40
7,70
9,60
DIM
4073225/E 03/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusions.
The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically
and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO-153
PowerPAD is a trademark of Texas Instruments Incorporated.
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